JP3300066B2 - Semiconductor device and multi-input logic circuit element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a logic circuit device using the same, and more particularly to a semiconductor device utilizing high-speed traveling of one-conduction type hot carrier and a multi-input logic circuit device using the same.

An exclusive NOR circuit (Exclusive NOR, XN
OR) is one of the basic elements of a logic circuit, and is usually configured using a large number of transistors. If an XNOR circuit can be configured with a circuit element having a simpler configuration, it is extremely effective for a large-scale integrated circuit and the like.

[0003]

2. Description of the Related Art Hot electron transistors (HET) and resonant hot electron transistors (RHET) have been proposed as new transistors utilizing hot electrons.

In HET, a high potential emitter barrier region is provided between an emitter region and a base region of the same conductivity type, and a high potential collector barrier region is provided between a base region and a collector region of the same conductivity type. Is provided.

The barrier height of the collector barrier region is set lower than the barrier height of the emitter barrier region. When electrons are injected from the emitter region into the base region by tunneling, the electrons in the hot state must lose energy. Are set so that they can pass through the collector barrier region as they are.

Electrons that have been injected from the emitter region into the base region but have lost energy are extracted from the base region and constitute a base current. In the HET, electrons injected from the emitter region to the base region are hot electrons until energy is lost, and high-speed operation is possible.

In RHET, the emitter barrier region is formed with a resonance structure composed of two emitter barriers and a quantum well therebetween, and only discrete energy levels are allowed in the quantum well.

In RHET, when a forward bias is applied between the emitter and the base, a tunnel current flows and hot electrons are injected into the base region only when the energy in the emitter region matches the energy level in the quantum well. . Therefore, the IV characteristics of the transistor as a whole indicate negative resistance.

As shown in FIG. 2A, an RHET is usually formed on an n-type semiconductor, for example, an n-type G
Collector 12 made of aAs or n-type InGaAs, undoped semiconductor having a large band gap such as i-type AlGaAs or collector barrier 13 made of i-type In (AlGa) As, and n-type semiconductor such as n-type GaAs a base 14 made of n-type InGaAs,
A single quantum well structure composed of a pair of undoped barrier layers 15a and 15c and a quantum well layer 15b therebetween, for example, i-type AlGaAs / i-type GaAs / i-type A
lGaAs or i-type InAlAs / i-type InGaAs
The emitter barrier 15 has a resonant tunneling diode (RTD) structure made of / i-type InAlAs, and an emitter 16 made of an n-type semiconductor, for example, n-type GaAs or n-type InGaAs, is stacked thereon.

For the emitter, base and collector, ohmic electrodes such as Au / Ge / Ni for n-type GaAs and Cr / Au for n-type InGaAs are deposited and heat-treated, respectively. 18, an emitter electrode 19.

The emitter barrier 15 is formed on the quantum well layer 1.
5b and a pair of barrier layers 15a sandwiching it, the thickness of which is set, for example, to around each layer 40A.

In a quantum well layer having such a thickness,
The state of the electron takes a discrete value by one-dimensional quantization. When a forward bias voltage is applied between the emitter and the base, when the energy of the electrons of the emitter approaches the allowed energy level in the quantum well layer, the emitter
Tunneling occurs between the quantum well layers, and electrons tunneled to the quantum well layer also tunnel through other barrier layers and are injected into the base.

[0013] If the energy of the electrons of the emitter is further increased, the energy level does not match the energy level in the quantum well layer, and tunneling from the emitter to the base is reduced. Therefore, as shown in FIG. 2B, the characteristic of the collector current with respect to the base-emitter voltage shows a negative resistance.

Various functional elements can be realized by utilizing the negative characteristics of RHET. For example, one RHE
An exclusive NOR circuit can be formed using T, a resistor, and a diode. FIG. 2C shows a configuration of an exclusive NOR circuit using RHET.

[0015] As shown in FIG.
The load resistor R1 is connected to the_CCConnect to
You. Also, from the point of interconnection between the collector and the load resistor R1
Output V _OUTTake out.

The emitter of the RHET is grounded, a resistor R2 is connected to the base, and two diodes D1 and D2 are connected.
Connect. Note that these diodes D1 and D2 are
It can also be realized by forming a Schottky electrode in the base region.

By inputting two binary signals A and B to such two diodes, a NOR logic operation can be performed by a combination of binary values. In the circuit configuration shown in FIG. 2C, a signal input from the two input terminals A and B to the RHET base is Lo (Low) or Hi (High).
h) (binary).

When the input terminal becomes Hi, a corresponding current flows through the resistor R2, and the base potential V _IN changes. The voltage generated in the resistor R2 by one of Hi voltage level of the input A or B in advance in accordance with the V _M levels of the I-V characteristic, both input signals A, approximately twice the voltage V _H generated by Hi voltage level B It is designed to correspond to.

In this way, when Lo is applied to both A and B, the base voltage of RHET is Low and the collector current does not flow, so that the voltage V _OUT of the output terminal C becomes Hi.
Level. When both inputs are Hi, the base-emitter voltage becomes _VH and the collector current stops flowing. Therefore, the voltage of the output terminal C becomes Hi similarly.
If either one is Hi and one is Lo, V _IN is V _M
V _OUT becomes Lo because the collector current flows.

Since RHET has both a large negative resistance as shown in FIG. 2C and a high speed by one-conduction type hot carrier, it can be used for various functional circuits such as flip-flops in addition to exclusive NOR. Can be used.

[0021]

The functions and application circuits of HET and RHET have not been sufficiently developed. An object of the present invention is to provide a HET semiconductor device having a new configuration and function.

Another object of the present invention is to provide a HET type multiple-input logic circuit element having a simpler and novel structure and capable of realizing an exclusive NOR circuit function.

[0023]

According to the present invention, there is provided a semiconductor device comprising:
A first conductive layer having a predetermined bandgap and a first conductivity type; a barrier layer of an i-type semiconductor formed on the first conductive layer and having a bandgap wider than the predetermined bandgap; A second conductive layer having a band gap narrower than a band gap of the barrier layer and the first conductivity type; an ohmic electrode formed on the first conductive layer; A first Schottky electrode and a second Schottky electrode formed on the substrate, and a bias in both a forward direction and a reverse direction is provided between the first Schottky electrode and the second Schottky electrode. A voltage can be applied.

[0024] A multiple-input logic circuit element according to the present invention includes a first conductive layer having a predetermined bandgap and a first conductivity type, and a bandgap formed on the first conductive layer and wider than the predetermined bandgap. A second conductive layer formed on the barrier layer, having a band gap narrower than a band gap of the barrier layer, and having the first conductivity type, and a first conductive layer formed on the first conductive layer. And a plurality of Schottky electrodes formed on the second conductive layer, wherein a plurality of inputs are applied to the plurality of Schottky electrodes to obtain outputs from the ohmic electrodes.

[0025]

The barrier layer corresponds to a collector barrier in the conventional HET. Further, the Schottky electrode has both functions of an emitter and an emitter barrier in the HET, and also functions as a base electrode by a bias voltage.

For simplicity, the Schottky electrode is now 2
Only the case (1) will be described with reference to FIG. The case where carriers are electrons will be described.
If the carrier is a hole and the polarity of the bias voltage is reversed, the carrier is a hole.

The semiconductor device has a structure as shown in FIG. A collector barrier layer CB made of an i-type semiconductor having a band gap wider than the collector region C is formed on a collector region C which is an n-type semiconductor layer having a predetermined band gap.
Is formed with a base region B of an n-type semiconductor layer.

The base region B and the collector region C do not need to be made of the same semiconductor, but both are in the collector barrier region CB.
It has a narrower bandgap. An ohmic electrode OE is formed on the collector region C, and the base region B
Are formed with two Schottky electrodes SE1 and SE2.

The basic operation of this semiconductor device is shown in FIG.
(A) As shown on the right side, a power supply voltage, for example, V _CC is applied to the ohmic electrode OE connected to the collector region C via the load R, and the output V _{OUT is} output from the interconnection point with the load R.
Take out. The two Schottky electrodes SE1, SE2 are
It is equivalent, but basically, on the other hand, for example, B
Are applied with a low voltage, while, for example, A is applied with a high voltage.

FIGS. 1B and 1C show the case where one Schottky electrode SE2 is grounded, a positive high voltage is applied to the ohmic electrode OE, and an intermediate voltage is applied to the other Schottky voltage SE1. 3 shows a potential distribution inside the semiconductor device.

FIG. 1B shows a potential distribution along the direction from the Schottky electrode SE2 to the ohmic electrode OE. Schottky electrode SE2 is at ground potential,
Schottky barrier SB adjacent to Schottky electrode SE2
Two potential barriers are formed.

The potential of the base region B is reduced by the positive intermediate voltage applied to the other Schottky electrode SE1, and the height of the Schottky barrier SB1 in front of the Schottky electrode SE1 is reduced.

The collector barrier region CB is
A potential barrier is formed on the surface in contact with the ohmic electrode OE, and the potential is gradually lowered by the potential of the ohmic electrode OE.

When the potential of the base region B drops to a certain degree or more, the barrier width of the Schottky barrier SB2 in front of the Schottky electrode SE2 decreases, and hot electrons are injected from the Schottky electrode SE2 into the base region B.

If the hot electrons pass through the base region B as they are, they pass through the collector barrier CB and are drawn to the ohmic electrode OE. When the electrons lose energy in the base region B, they are blocked by the collector barrier CB and fall into the base region B.

FIG. 1C shows a horizontal potential distribution of the base region B. Schottky electrodes SE1 and SE2
Forms a Schottky barrier between itself and the base region B, but the Schottky electrode SE2 is grounded and a positive voltage is applied to the Schottky electrode SE1, so that the Schottky barrier SB2 on the front surface of the Schottky electrode SE2 has a reverse bias. As a result, the barrier height is maintained, and the Schottky barrier SE1 in front of the Schottky electrode SE1 is forward-biased and the barrier height is reduced.

When the voltage applied to the Schottky electrode SE1 increases to a certain extent or more, the potential of the base region B is reduced, and the width of the Schottky barrier SB2 on the front surface of the Schottky electrode SE2 is reduced.

When the width of the Schottky barrier SB2 is reduced to a certain extent or more, hot electrons are injected from the Schottky electrode SE2 through the Schottky barrier SB2 into the base region B.

As shown in FIG. 1B, the electrons injected from the Schottky electrode SE2 into the base region B are:
Initially it has higher energy than the barrier height of the collector barrier. These electrons are in a hot electron state, and have energy exceeding the collector barrier CB when passing through the base region without being scattered.

Hot electrons that have passed through the collector barrier CB are drawn out to the ohmic electrode OE, and constitute a collector current. On the other hand, electrons that have lost energy in the base region B fall into the base region B and are extracted from the Schottky electrode SE1.

As described above, the two Schottky electrodes SE
When one of SE1 and SE2 is grounded and kept at a low voltage and a bias voltage (intermediate voltage) is applied to the other, the semiconductor device having the configuration shown in FIG. 1A performs the same operation as a hot electron transistor (HET). .

Here, if the fact that the Schottky electrodes SE1 and SE2 have the same configuration is used, it is understood that the roles of the Schottky electrodes SE1 and SE2 may be exchanged. Therefore, a case where two input signals A and B are applied to the Schottky electrodes SE1 and SE2 as shown in FIG.

If one of the inputs A and B is Hi and the other is Low, one of the Schottky electrodes SE1 and SE2 is forward-biased as shown in FIGS.
The semiconductor device in FIG. 1A functions as a turned-on transistor.

Inputs A and B are both Low or Hi.
, Two Schottky electrodes SE1, SE2
There is no bias between the Schottky barriers SB1, SB
2 maintain the barrier height, and no tunnel current is generated as shown in FIGS. 1 (B) and 1 (C). Therefore, in this case, the semiconductor device shown in FIG. 1A is turned off, and carrier injection is not performed.

The above operation indicates that the equivalent circuit shown on the right side of FIG. 1A has the exclusive NOR function as it is. That is, an exclusive NOR circuit can be realized by one Schottky HET and one load.

Hereinafter, the present invention will be described based on specific examples.
I will describe it in more detail.

[0047]

FIG. 3 shows InGaAs according to an embodiment of the present invention.
The configuration of an s / In (AlGa) As-based semiconductor device is shown in a cross-sectional view.

On a semi-insulating InP substrate 1, an n-type InP
_0.53Ga_0.47As collector layer 2 is formed epitaxially
And an i-type In_0.52(Al_0.5Ga
_0.5) _0.48As collector barrier layer 3 becomes epitaxial
Formed, and an n-type In_{0. 53}Ga_0.47As base layer
4 is formed epitaxially.

A collector electrode 7 for forming an ohmic contact is formed on the collector layer 2, and Schottky emitters 5 and 6 for forming a Schottky electrode on the base layer 4.
Are formed.

The n-type In _0.53 Ga _0.47 As base layer 4 is
It has a relatively low doping amount of about 1 × 10 ¹⁸ cm ⁻³ . Schottky emitters 5 and 6 are made of Cr / Au, Ti /
Pt / Au, WSi or the like, and In _0.53 Ga _0.47 A
A Schottky electrode having a barrier height of about 0.2 eV with respect to the s base layer 4 is formed.

The n-type In _0.53 Ga _0.47 As collector layer 2 has a high doping amount of about 5 × 10 ¹⁸ cm ⁻³ . The collector electrode 7 on the collector layer 2 is made of AuGe / A
and an ohmic contact with the collector layer 2.

That is, the base layer 4 of the n-type semiconductor layer having the two Schottky electrodes 5 and 6 is connected to the n-type semiconductor layer 2 having the ohmic electrode 7 via a potential barrier.

When a bias voltage is applied between the Schottky electrodes 5 and 6, the Schottky barrier on the front surface of one Schottky electrode that is forward-biased is lowered, and controls the potential of the base layer 4 disposed therebetween.

By controlling the potential of the base layer 4, the width of the Schottky barrier in front of the other Schottky electrode is controlled, and carrier injection from the Schottky electrode to the base layer 4 by tunneling is controlled. Once injected carriers can pass through the base layer 4 in a hot state, jump over the collector barrier layer 3 and be extracted to the collector region 2.

Such a semiconductor device can be formed by the following manufacturing process. First, MB
E or semi-insulating In
On a P substrate 1, Si-doped, carrier concentration 5 × 10 ¹⁸ c
m ⁻³ n-type In _0.53 Ga _0.47 As collector layer 2
Epitaxially grow to a thickness of nm.

An undoped i-type In _0.52 (A
l _0.5 Ga _0.5 ) _0.48 As collector barrier layer 3 is 200
nm, and further thereon Si doping, carrier concentration 1 × 1
An n-type In _0.53 Ga _0.47 As base layer 4 of 0 ¹⁸ cm ^-3 is epitaxially grown to a thickness of 30 nm.

Next, the base layer 4 and the collector barrier layer 3 are patterned by dry etching as shown in the figure. An appropriate mask is formed on the n-type In _0.53 Ga _0.47 As base layer 4 and Cr / Au or Ti /
After depositing Pt / Au or WSi, the Schottky emitter 5 and the Schottky emitter 6 are formed by lift-off. These Schottky emitter materials form a Schottky barrier having a height of about 0.2 eV with respect to the n-type In _0.53 Ga _0.47 As base layer 4.

When a metal such as AuGe / Au is deposited on the n-type In _0.53 Ga _0.47 As collector layer 2,
An ohmic collector electrode 7 is formed. The separation of the Schottky emitters 5 and 6 can be performed only by lift-off,
There is no need for etching. For this reason, there is no concern that the base resistance changes during the processing process.

Further, the height difference between the collector electrode and the Schottky emitter electrode (emitter) is reduced as compared with the conventional case of HET or RHET, which is also effective in preventing accidents in a processing process such as disconnection of wiring. .

As another embodiment of the present invention, it is possible to form a semiconductor device using an InP substrate as a GaAs substrate. In this case, the substrate may be made of semi-insulating GaAs, the collector barrier layer and the emitter barrier layer may be made of AlGaAs, and the collector layer and the base layer may be made of n-type GaAs.

However, in GaAs, the separation energy between the Γ valley and the L valley in the conduction band is relatively small, about 0.3 eV. Therefore, a part of the hot electrons injected into the base layer by tunneling the Schottky barrier transits to the L valley and is slowed down.

On the other hand, in the InGaAs base layer, since the エ ネ ル ギ -L separation energy is as large as about 0.55 eV, it is considered that both the high speed and the current gain are superior to the GaAs system.

If the device shown in FIG. 3 is connected to a load as shown in FIG. 1A and is a two-input logic circuit device, an exclusive NOR gate can be constituted by itself as described above. In the above, the case of two emitters has been described for simplicity. However, it is clear that a multi-input logic circuit element can be formed by further increasing the number of Schottky emitters. The load may be formed by a transistor or the like in addition to the resistor.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0065]

As described above, according to the present invention,
A HET type semiconductor device and a HET type multiple input logic element having a simple configuration are provided.

The Schottky electrode functioning as an emitter can be easily formed without etching for separating the semiconductor layer, and a high production yield can be easily secured. Also, the step between the electrodes is low, and the probability of a disconnection accident can be reduced.

Further, the basic gate of the exclusive NOR circuit can be easily constituted by only the HET type semiconductor device and one load, and the number of elements of the logic integrated circuit can be greatly reduced.

[Brief description of the drawings]

FIG. 1 shows a basic embodiment. FIG. 1A is a cross-sectional view showing the configuration and a circuit diagram showing a connection example as an exclusive NOR gate, and FIGS. 1B and 1C respectively show a case where one Schottky electrode SE1 is forward-biased. FIG. 4 is a conduction band energy diagram for explaining the flow of electrons in a vertical direction and a horizontal direction.

FIG. 2 shows a prior art example. FIG. 2A is a cross-sectional view of RHET, FIG. 2B is a graph showing its IV characteristics, FIG.
(C) is a circuit diagram when the exclusive NOR circuit is used as a unit gate.

FIG. 3 is a sectional view of a semiconductor device according to an embodiment.

[Explanation of symbols]

_Reference Signs _List 1 semi-insulating InP substrate 2 n-type In _0.53 Ga _0.47 As collector layer 3 i-type In _0.52 (Al _0.5 Ga _0.5 ) _0.48 As collector barrier layer 4 n-type In _0.53 Ga _0.47 As base layer 5, 6 Schottky emitter 7 collector electrode Reference Signs List 11 semi-insulating substrate 12 collector 13 collector barrier 14 base 15 emitter barrier 15a barrier layer 15b well layer 16 emitter 17 collector electrode 18 base electrode 19 emitter electrode B base region CB collector barrier region C collector region SE Schottky electrode OE ohmic electrode R resistance (load)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 21/8222 H01L 27/06 H01L 29/205 H01L 29/737

Claims (5)

(57) [Claims] A first conductive layer having a predetermined bandgap and a first conductivity type; and an i-type semiconductor barrier layer formed on the first conductive layer and having a bandgap wider than the predetermined bandgap. A second conductive layer formed on the barrier layer and having a band gap narrower than a band gap of the barrier layer and the first conductivity type; an ohmic electrode formed on the first conductive layer; A first Schottky electrode and a second Schottky electrode formed on a second conductive layer, wherein a forward direction and a reverse direction are provided between the first Schottky electrode and the second Schottky electrode. Semiconductor device capable of applying both bias voltages. 2. An n-type InG substrate further comprising a semi-insulating InP substrate, wherein the first conductive layer is formed on the InP substrate.
aAs layer, and the i-type barrier layer is an i-type In (AlG
a) an As layer, wherein the second conductive layer is n-type InGaAs
The ohmic electrode is an Au / Ge / Au layer, and the first and second Schottky electrodes are Cr / A
2. The semiconductor device according to claim 1, wherein the semiconductor device is a u or Ti / Au layer. 3. The semiconductor device further comprises a semi-insulating GaAs substrate, wherein the first conductive layer is an n-type GaAs layer, the i-type barrier layer is an i-type AlGaAs layer, and the second conductive layer is an n-type GaAs layer. Wherein the ohmic electrode is AuGe / A
2. The semiconductor device according to claim 1, wherein the semiconductor device is a u layer, and the Schottky electrode is a Cr / Au or Ti / Au layer. 4. The first Schottky electrode and the second Schottky electrode
4. The semiconductor device according to claim 1, wherein the Schottky electrode alternates between the role of the emitter electrode and the role of the base electrode based on the order of the bias voltage. 5. 5. A first conductive layer having a predetermined band gap and a first conductivity type; and an i-type semiconductor barrier layer formed on the first conductive layer and having a band gap wider than the predetermined band gap. A second conductive layer formed on the barrier layer and having a band gap narrower than a band gap of the barrier layer and the first conductivity type; an ohmic electrode formed on the first conductive layer; And a plurality of Schottky electrodes formed on a second conductive layer, wherein a plurality of inputs are applied to the plurality of Schottky electrodes and an output is obtained from the ohmic electrode.