JP3301264B2 - Decoding circuit of compressed video playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a depacking process for decoding coded and packed data efficiently in a decoding circuit of a compressed moving picture reproducing apparatus. And a circuit for realizing the above.

[0002]

2. Description of the Related Art A depacking circuit in a decoding circuit of a compressed moving picture reproducing apparatus is constituted by a moving picture compression encoding apparatus or the like.
This is a circuit for extracting image data that has been subjected to packing processing for recording on a recording medium such as a magnetic tape, for decoding.

[0003] Packing and depacking are described in JP-A-4-79681 and JP-A-3-262332.

[0004] The compressed moving image data input to the decoding circuit in the compressed moving image reproducing apparatus of the present invention is, for example,
A format standardized by the HD Digital VTR Council, which is led by Matsushita, Sony, Philips, and Thomson, ie, DVC (Digital VCR f
or Consumer use) is compressed moving image data according to an image compression method called "consumer use".

[0005] In a moving picture compression apparatus for generating compressed moving picture data to be input to a decoding circuit in a compressed moving picture reproducing apparatus, the input image data has the following specifications. SD, which is a standard digital VTR standard for home use compatible with current TV
In the case of the format, in the [4: 1: 1] format, the input image data is a frame composed of 720 pixels × 480 lines of luminance (Y) and 180 pixels × 480 lines of color difference (CR, CB). The frequency is 13.5 MHz.

A DCT block is composed of 8 × 8 pixels on a frame, and a macroblock is composed of six DCT blocks. DCT constituting a macroblock
The block includes four luminance (Y) blocks and two color difference blocks (CR, CB). Further, a video segment as a unit for fixing the amount of compressed data is constituted by five macro blocks.

[0007] Also, HDTV-compatible home digital V
In the HD format, which is a draft of the TR standard, [12: 4:
0] format, the input image data has a luminance of 100
It is a frame of 8 pixels × 1024 lines and 336 pixels × 512 lines of color difference, and the sampling frequency of the luminance is 4
0.5 MHz. At this time, one frame is 42 × 64
The macroblock is first converted into a frame of 45 × 60 macroblock, and the moving image compression encoding apparatus performs processing on the converted frame.

[0008] The image data compressed by the moving image compression encoding apparatus is subjected to a packing process in order to be recorded on a recording medium such as a magnetic tape. As shown in FIG. 4, in packing, data for one video segment (5 macroblocks) is arranged in five sync blocks. A collection of data arranged in each sync block is called a unit.
The data amount for one video segment is suppressed to less than the data amount for 5 units by rate control.

One unit corresponds to one macro block. In the unit, there are six DCT areas corresponding to each DCT block (Y is 14 bytes, CR,
(CB is 10 bytes). In the packing, data converted into Huffman codes of AC coefficients is arranged in this DCT area.

[0010] The conversion into the Huffman code is performed by rearranging the quantized AC coefficient data (two-dimensional) of each DCT block into one-dimensional data by zigzag scanning. This is performed by using the combination of the coefficient values as the entry. At the end of each DCT block, a 4-bit EOB code is added.

In the packing process, Huffman code data is arranged in the DCT area in three stages (pass 1, pass 2, pass 3). The data for one video segment once stored in the buffer memory
The code of the CT block is packed until each fixed area becomes full, and the overflow data is the first DCT.
The excess data is stored in the excess data memory 1 for each unit by sequentially connecting the blocks. In pass 2, data overflowing in pass 1 is sequentially packed from the beginning into a free area in the same unit. The overflowing data is stored in the excess data memory 2 for 5 units by sequentially connecting the data from the head unit. In pass 3, the data overflowing in pass 2 is packed in the empty area of all five units from the beginning.

The depacking circuit in the decoding circuit of the compressed moving picture reproducing apparatus has one video segment (5 units).
Is a circuit for depacking the packed Huffman code data with a constant data amount unit.

The depacking process for one video segment is performed in the following procedure. First, the code (ACL) packed in pass 1 of the packing process
Is decoded for one macroblock. Next, the code (ACM) packed in pass 2 is decoded for one macroblock. After repeating the above operation for 5 macroblocks, the code (ACH) packed in pass 3
To decode.

[0014]

In the packing process,
As described above, a total of three memories are required, one buffer memory for temporarily storing data for one video segment and two memories for storing excess data. In the depacking process, three processes are required if the process is simply performed in the reverse of the packing.

An object of the present invention is to enable a depacking circuit in a decoding circuit of a compressed moving picture reproducing apparatus to realize depacking processing on compressed input moving picture data with a smaller memory capacity than before. is there.

[0016]

In order to achieve the above object, a buffer memory means for storing Huffman code data for one video segment in a depacking circuit in a decoding circuit of a compressed moving picture reproducing apparatus, and said buffer memory means Barrel shifter means for performing a bit shift on the output code data according to the code length information and latching the output,
Decoding the output code data by said barrel shifter means, a decoding means for returning a code length, the buffer
Data from the memory means into first, second and third steps.
Memory control means for reading data and the block being decoded.
Block address that generates the block address that identifies the block
Address generation means, and the block address generation means
The memory control procedure is performed according to the block address where
The stage switches between the first, second and third steps.
Configuration. Furthermore, which D in which macroblock
Block count means for indicating whether a CT block is being decoded, area count means for indicating which area of which unit is being decoded, and flag memory means for storing a flag indicating that an EOB is found for each block. Flag memory means for storing, for each area, a flag indicating whether or not decoding of the area ends with EOB, and area end detecting means for generating a no code flag (NC) indicating that there is no code to be decoded in the area. Further, a code address storage means is provided for storing the number of bytes and the number of bits for which decoding of the code in the area is completed.

[0017]

When performing depacking processing on input code data, the buffer memory stores Huffman code data for one video segment, and the barrel shifter stores the Huffman code data that has not been decoded by the code length information. On the other hand, a bit shift is performed, and the code data output by the buffer memory means is added to the bit-shifted code data to obtain code data to be decoded next. The decoding means decodes the code data received from the barrel shifter means and outputs zero-run, entry decode data, an EOB signal, and code length data.

The block counting means outputs an address indicating which DCT block of which macro block is being decoded. The area counting means outputs an address indicating which area of which unit is being decoded. Further, the flag memory means stores an EOB flag for each block indicating that decoding has been completed, or a flag for each area indicating whether or not decoding of the area ends with EOB.

The area end detecting means decodes all the code data stored in the DCT area, and generates a no code signal indicating that there is no more code data to be decoded in the area. The code address storage means adds the code length received from the decode circuit to the area address received from the area count means, remembers how far the decoding has progressed in the area, and outputs byte and bit information.

By using the above means, the depacking circuit according to the present invention does not have a buffer memory other than the code memory for storing the packed code as it is, and only needs to control the address to the code memory. The depacking process can be performed by accessing the code.

[0021]

FIG. 1 is a block diagram showing a first embodiment in which ACL data of a depacking circuit in a decoding circuit of a compressed moving picture reproducing apparatus according to the present invention is processed.

The code input terminal 1 supplies Huffman code data to a buffer memory 2, and the buffer memory 2 supplies data to a barrel shifter 3. Further, the barrel shifter 3 supplies code data to be decoded to the decoding circuit 4. The data decoded by the decoding circuit 4 is output to a decoded data output terminal 5, and when an EOB signal is detected, an EOB signal output terminal 6, a block count circuit 7, a flag memory 8, an area count circuit 9, and a flag memory 10 to provide an output signal. Further, the decoding circuit 4 outputs the code length data to the barrel shifter 3, the area end detection circuit 13, and the code address storage circuit 12.

The block count circuit 7 is connected to the flag memory 8, and the block address output from the block count circuit 7 is output to the block address output terminal 11 and the flag memory 8.

The area count circuit 9 includes a flag memory 1
The area address which is connected to 0 and output from the area count circuit 9 is output to the code address storage circuit 12 and the flag memory 10.

The code address storage circuit outputs the byte information and the bit information to the area end detection circuit 13, and supplies the byte information to the buffer memory 2 and the bit information to the barrel shifter 3.

The basic operation of the depacking circuit according to the present invention is as follows. First, buffer memory 2
Stores Huffman code data for one video segment supplied from the code input terminal 1. Decoding circuit 4
Decodes the code data supplied from the barrel shifter 3, outputs the decoded data and the EOB signal, and supplies the code length to the barrel shifter 3. The barrel shifter 3 subtracts from the previously decoded bit number by the supplied code length, shifts the remaining bits, and prepares them for the next decoded data. The empty barrel shifter 3 newly supplies 1-byte code data from the buffer memory 2, and adds it to the bits remaining in the barrel shifter 3 before supplying it to the decoding circuit 4.

The block count circuit 7 outputs a signal output from the decode circuit 4 when an EOB indicating the end of each DCT block is found and an output from the area end detection circuit 13 when the data of each DCT area is used up. The no-code signal to be input is input. When either of these signals is input, the block count circuit 7
Counts up. The flag memory 8 receives an address from the block count circuit 7 and advances the address each time the block count circuit 7 advances the count. At this time, in the flag memory 8, when EOB is detected and the block count circuit 7 counts up, the address is advanced by setting the flag (1) as shown in FIG. Is counted up, the (0) address is advanced without setting a flag. Here, the advance of the address of the flag memory 8 means that the block count circuit 7 counts up.

The block address output from the block count circuit 7 is supplied to a block address output terminal 1
1 is also output.

On the other hand, each DC is also applied to the area count circuit 9.
The signal output from the decoding circuit 4 when the EOB indicating the end of the T block is found and the no-code signal output from the area end detection circuit 13 when the data of each DCT area is used up are input. When one of these signals is input, the area count circuit 9 counts up. The flag memory 10 receives an address from the area count circuit 9 and advances the address each time the area count circuit 9 advances the count. At that time, when the EOB is detected and the area count circuit 9 counts up in the flag memory 10, the address is advanced by setting the flag (1) as shown in FIG.
Is counted up, the (0) address is advanced without setting a flag. Here, the advance of the address of the flag memory 10 means that the area count circuit 9 counts up.

On the other hand, the area count circuit 9 also supplies the area address to the code address storage circuit 12, and the code address storage circuit 12 decodes the bits decoded for each area based on the code length supplied from the decode circuit 4. Are added, and the position in the area to which decoding has been completed is stored.

The area end detection circuit 13 receives, from the code address storage circuit 12, byte information and bit information indicating to which position in the area decoding has been completed.
The vacant bits in the area determined from the information are compared with the code length supplied from the decoding circuit 4. Here, if the supplied code length is larger than the vacant bits in the area, it indicates that no code that can be decoded remains in the area, and the area end detection circuit 13
Supplies a no-code signal to the block count circuit 7 and the area count circuit 9.

The byte information output from the code address storage circuit 12 is also supplied to the buffer memory 2, and the buffer memory 2 controls supply of the code data to the barrel shifter 3 based on the information. Further, the bit information output from the code address storage circuit 12 is
The data is supplied to the barrel shifter 3, and the barrel shifter 3 performs a bit shift based on the bit information.

The decoding of one unit of the ACL is completed by performing the decoding of one macroblock by the above operations.

According to the present embodiment, the necessary code can be accessed only by controlling the address to the code memory without having a buffer memory other than the code memory for storing the packed code as it is, and one video segment can be accessed. The ACL depacking and decoding processing can be realized with only one buffer memory that stores the code data.

FIG. 2 is a block diagram of a second embodiment in which the processing of ACM data is performed after the processing of ACL data of the depacking circuit in the decoding circuit of the compressed moving picture reproducing apparatus according to the present invention.

The code input terminal 1 supplies Huffman code data to a buffer memory 2, and the buffer memory 2 supplies data to a barrel shifter 3. Further, the barrel shifter 3 supplies code data to be decoded to the decoding circuit 4. The data decoded by the decoding circuit 4 is output to a decoded data output terminal 5, and when an EOB signal is detected, an EOB signal output terminal 6, a block count circuit 7, a flag memory 8, an area count circuit 9, and a flag memory 10 to provide an output signal. Further, the decoding circuit 4 outputs the code length data to the barrel shifter 3, the area end detection circuit 13, and the code address storage circuit 12.

The block count circuit 7 is connected to the flag memory 8, and outputs a block address output from the block count circuit 7 to a block address output terminal 11,
It is output to the flag memory 8 and the area storage circuit 14.
Further, the block count circuit 7 supplies a select signal to the switch 15.

The area count circuit 9 includes a flag memory 1
The area address that is connected to 0 and output from the area count circuit 9 is output to the switch 15, the flag memory 10, and the area storage circuit 14.

The code address storage circuit outputs the byte information and the bit information to the area end detection circuit 13, and supplies the byte information to the buffer memory 2 and the bit information to the barrel shifter 3.

The area storage circuit 14 is supplied with the block address from the block count circuit 7 and the area address from the area count circuit as data. The output is supplied to the switch 15.

The area address of the output of the area count circuit 9 and the output of the area storage circuit 14 are input to the switch 15, and an address to be output to the code address storage circuit 12 is selected by a select signal from the block count circuit 7.

The basic operation of the depacking circuit according to the present invention is as follows. First, buffer memory 2
Stores Huffman code data for one video segment supplied from the code input terminal 1. Decoding circuit 4
Decodes the code data supplied from the barrel shifter 3, outputs the decoded data and the EOB signal, and supplies the code length to the barrel shifter 3. The barrel shifter 3 subtracts from the previously decoded bit number by the supplied code length, shifts the remaining bits, and prepares them for the next decoded data. The empty barrel shifter 3 newly supplies 1-byte code data from the buffer memory 2, and adds it to the bits remaining in the barrel shifter 3 before supplying it to the decoding circuit 4.

The block count circuit 7 outputs a signal output from the decode circuit 4 when an EOB indicating the end of each DCT block is found and an output from the area end detection circuit 13 when the data of each DCT area is used up. The no-code signal to be input is input. When either of these signals is input, the block count circuit 7
Counts up. The flag memory 8 receives an address from the block count circuit 7 and advances the address each time the block count circuit 7 advances the count. At this time, in the flag memory 8, when EOB is detected and the block count circuit 7 counts up, the address is advanced by setting the flag (1) as shown in FIG. Is counted up, the (0) address is advanced without setting a flag.

Here, it should be noted that according to the first embodiment of the present invention, when the decoding of the ACL data is completed, the address (1) where the flag is set is set in the address area of the flag memory 8. There is a non-existent (0) address. As in Embodiment 2 according to the present invention, AC
When decoding the ACM data following the decoding of the L data, if the block count circuit 7 counts up and the flag memory 8 advances the address and the flag is set at that address, the flag memory 8 8
Advances the address to where no flag is set.
Here, the advance of the address of the flag memory 8 means that the block count circuit 7 counts up.

The block address output from the block count circuit 7 is applied to the block address output terminal 1
1 and the area storage circuit 14.

On the other hand, the area count circuit 9 also has
The signal output from the decoding circuit 4 when the EOB indicating the end of the T block is found and the no-code signal output from the area end detection circuit 13 when the data of each DCT area is used up are input. When one of these signals is input, the area count circuit 9 counts up. The flag memory 10 receives an address from the area count circuit 9 and advances the address each time the area count circuit 9 advances the count. At that time, when the EOB is detected and the area count circuit 9 counts up in the flag memory 10, the address is advanced by setting the flag (1) as shown in FIG.
Is counted up, the (0) address is advanced without setting a flag.

When the area count circuit 9 counts up and the flag memory 10 advances the address, if the flag is not set at that address, the flag memory 10 stores the address up to the point where the flag is set. Proceed. Here, the advance of the address of the flag memory 10 means that the area count circuit 9 counts up.

The area count circuit 9 also supplies an area address to the area storage circuit 14 and the switch 15, and supplies an area address as data to the area storage circuit 14.

When the decoding of the ACL data is completed, the flag in the flag memory 8 and the flag in the flag memory 10 match, and each flag is set in the block count circuit 7.
Indicates that decoding of the block has been completed, and for the area count circuit 9,
This indicates that an empty area exists.

When decoding the ACM data, the block count circuit 7 searches for an undecoded block while looking at this flag, and the area count circuit 9 searches for an empty area to perform decoding.

When the decoding is interrupted by using up the data in each area, an uncompleted code of several bits that has not been decoded remains at the end of the area.
In order to continue decoding the ACM data, the incomplete code must be read, and then the code data in the empty area must be continued.

When the decoding of the ACL data is completed, the area in which the incomplete code exists matches the address indicated by the block count circuit 7, but moves when the decoding of the ACM data is advanced. Therefore, in order to store the moved area of the uncompleted code, in the second embodiment of the present invention, an area storage circuit 14 is added to the circuit configuration of the first embodiment.

The area storage circuit 14 stores an area count circuit 9 in a block address output from the block count circuit 7, that is, an address conceptually indicating which macro block and which DCT block is being decoded.
, Ie, an address indicating which area of which unit is being decoded.

In the switch 15, the data indicating the address output from the area storage circuit 14, that is, the address indicating the position where the incomplete code actually exists, and the area address output from the area count circuit 9 are stored in the block count circuit. Switching by the control signal output from 7,
Output to the code address storage circuit 12. That is, the switch 15 first outputs the address where the incomplete code exists, and subsequently outputs the address indicating the next area to be decoded.

The code address storage circuit 12 adds the bits decoded for each area based on the code length supplied from the decode circuit 4, and stores the position of the area to which the decoding has been completed.

The area end detection circuit 13 receives, from the code address storage circuit 12, byte information and bit information indicating up to which position in the area decoding has been completed.
The vacant bits in the area determined from the information are compared with the code length supplied from the decoding circuit 4. Here, if the supplied code length is larger than the vacant bits in the area, it indicates that no code that can be decoded remains in the area, and the area end detection circuit 13
Supplies a no-code signal to the block count circuit 7 and the area count circuit 9.

The byte information output from the code address storage circuit 12 is also supplied to the buffer memory 2, and the buffer memory 2 controls supply of the code data to the barrel shifter 3 based on the information. Further, the bit information output from the code address storage circuit 12 is
The data is supplied to the barrel shifter 3, and the barrel shifter 3 performs a bit shift based on the bit information.

By performing decoding for one macroblock by the above operations, decoding of ACM subsequent to decoding of one unit of ACL is completed.

According to the present embodiment, the necessary code can be accessed only by controlling the address to the code memory without having a buffer memory other than the code memory for storing the packed code as it is, so that one video segment can be accessed. The depacking and decoding of ACL and ACM can be realized with only one buffer memory storing the code data of.

FIG. 3 shows ACL and AC of the depacking circuit in the decoding circuit of the compressed moving picture reproducing apparatus according to the present invention.
FIG. 13 is a block diagram of a third embodiment in the case of performing ACH data processing subsequent to M data processing.

The code input terminal 1 supplies Huffman code data to a buffer memory 2, and the buffer memory 2 supplies data to a barrel shifter 3. Further, the barrel shifter 3 supplies code data to be decoded to the decoding circuit 4. The data decoded by the decode circuit 4 is output to a decode data output terminal 5, and when an EOB signal is detected, the EOB signal output terminal 6, block count circuit 7, flag memory 8, area count circuit 9, flag memory 10 , Connected area counting circuit 1
7 and an output signal to the flag memory 18. Further, the decoding circuit 4 converts the code length data into the barrel shifter 3,
It outputs to the area end detection circuit 13 and the code address storage circuit 12.

The block count circuit 7 is connected to the flag memory 8 and outputs a block address output from the block count circuit 7 to a block address output terminal 11.
It is output to the flag memory 8 and the area storage circuit 14.
Further, the block count circuit 7 supplies a select signal to the switch 16.

The area count circuit 9 stores the flag memory 1
The area address which is connected to 0 and output from the area count circuit 9 is output to the switch 16, the flag memory 10, and the area storage circuit 14.

The connection area count circuit 17 is connected to the flag memory 18, and the connection area address output from the connection area count circuit 17 is output to the switch 16 and the flag memory 18.

The code address storage circuit outputs the byte information and the bit information to the area end detection circuit 13, and supplies the byte information to the buffer memory 2 and the bit information to the barrel shifter 3.

The area storage circuit 14 is supplied with the block address from the block count circuit 7 and the area address from the area count circuit as data. The output is supplied to the switch 16.

The switch 16 receives the area address of the output of the area count circuit 9, the output of the connected area count circuit 17 and the output of the area storage circuit 14, and outputs the code address according to the select signal from the block count circuit 7 and the connected area count circuit 17. An address to be output to the storage circuit 12 is selected.

The basic operation of the depacking circuit according to the present invention is as follows. First, buffer memory 2
Stores Huffman code data for one video segment supplied from the code input terminal 1. Decoding circuit 4
Decodes the code data supplied from the barrel shifter 3, outputs the decoded data and the EOB signal, and supplies the code length to the barrel shifter 3. The barrel shifter 3 subtracts from the previously decoded bit number by the supplied code length, shifts the remaining bits, and prepares them for the next decoded data. The empty barrel shifter 3 newly supplies 1-byte code data from the buffer memory 2, and adds it to the bits remaining in the barrel shifter 3 before supplying it to the decoding circuit 4.

The block count circuit 7 outputs a signal output from the decode circuit 4 when an EOB indicating the end of each DCT block is found and an output from the area end detection circuit 13 when the data of each DCT area is used up. The no-code signal to be input is input. When either of these signals is input, the block count circuit 7
Counts up. The flag memory 8 receives an address from the block count circuit 7 and advances the address each time the block count circuit 7 advances the count. At this time, in the flag memory 8, when EOB is detected and the block count circuit 7 counts up, the address is advanced by setting the flag (1) as shown in FIG. Is counted up, the (0) address is advanced without setting a flag.

It should be noted that, in the first embodiment of the present invention, when the decoding of the ACL data has been completed, the flag area is set to the address (1) where the flag is set in the address area of the flag memory 8. There is a non-existent (0) address. As in Embodiment 2 according to the present invention, AC
When decoding the ACM data following the decoding of the L data, if the block count circuit 7 counts up and the flag memory 8 advances the address and the flag is set at that address, the flag memory 8 8
Advances the address to where no flag is set.
Here, the advance of the address of the flag memory 8 means that the block count circuit 7 counts up.

The block address output from the block count circuit 7 is applied to the block address output terminal 1
1 and the area storage circuit 14.

On the other hand, the area count circuit 9 also has
The signal output from the decoding circuit 4 when the EOB indicating the end of the T block is found and the no-code signal output from the area end detection circuit 13 when the data of each DCT area is used up are input. When one of these signals is input, the area count circuit 9 counts up. The flag memory 10 receives an address from the area count circuit 9 and advances the address each time the area count circuit 9 advances the count. At that time, when the EOB is detected and the area count circuit 9 counts up in the flag memory 10, the address is advanced by setting the flag (1) as shown in FIG.
Is counted up, the (0) address is advanced without setting a flag.

Here, when the area count circuit 9 counts up and the flag memory 10 advances the address, if the flag is not set at that address, the flag memory 10 stores the address up to the point where the flag is set. Proceed. Here, the advance of the address of the flag memory 10 means that the area count circuit 9 counts up.

The area count circuit 9 also supplies an area address to the area storage circuit 14 and the switch 16, and supplies an area address as data to the area storage circuit 14.

When the free area is small, even when the code of the free area is connected to the uncompleted code at the time of decoding the ACM data, the processing may end without being completed. In decoding ACH data, such an area needs to be read following an incomplete code. Therefore,
A counter for searching for such an area, that is, a connected area counting circuit 17 is provided, and after reading an uncompleted code, a code of an area indicated by the counting circuit is read, and then reading of an empty area is started.

The connection area count circuit 17 also has a DC
The signal output from the decoding circuit 4 when the EOB indicating the end of the T block is found and the no-code signal output from the area end detection circuit 13 when the data of each DCT area is used up are input. When one of these signals is input, the connected area counting circuit 17 counts up. The flag memory 18 receives an address from the linked area count circuit 17 and advances the address each time the linked area count circuit 17 counts. At this time, when EOB is detected in the flag memory 18 and the connected area count circuit 17 counts up, the address is advanced by setting a flag (1) as shown in FIG. When the circuit 17 counts up, the (0) address is advanced without setting a flag.

Here, when the connected area counting circuit 17 counts up and the flag memory 18 advances the address, if the flag is not set at that address,
The flag memory 18 advances the address to the point where the flag is set. Here, the advance of the address of the flag memory 18 means that the connected area count circuit 17 counts up. The address indicated by the connection area count circuit 17 is a free area in the same block as the macroblock indicated by the block count circuit 7.

The connection area count circuit 17 supplies the area address to the switch 16 and
Is supplied with a select signal.

The area storage circuit 14 stores the block address output from the block count circuit 7, that is, the address indicating which DCT block of which macro block is conceptually being decoded, in the area count circuit 9.
, Ie, an address indicating which area of which unit is being decoded.

In the switch 16, the data indicating the address output from the area storage circuit 14, that is, the address indicating the position where the uncompleted code actually exists, and the output of the connected area count circuit 17, that is, the uncompleted code when decoding the ACM, The address indicating the area that could not be decoded even when connected to the code, and the area address output from the area count circuit 9 are output from the select signal output from the block count circuit 7 and output from the connected area count circuit 17. It is switched by the select signal and output to the code address storage circuit 12.

That is, the switch 16 first outputs to the code address storage circuit 12 the address where the uncompleted code exists, and then decodes the area where decoding was not possible even when the ACM was connected to the uncompleted code. , Followed by an address indicating the next area to be decoded.

The code address storage circuit 12 adds the bits decoded for each area based on the code length supplied from the decode circuit 4 and stores the position of the area to which decoding has been completed.

The area end detection circuit 13 receives byte information and bit information from the code address storage circuit 12 indicating the position in the area to which decoding has been completed.
The vacant bits in the area determined from the information are compared with the code length supplied from the decoding circuit 4. Here, if the supplied code length is larger than the vacant bits in the area, it indicates that no code that can be decoded remains in the area, and the area end detection circuit 13
Supplies a no-code signal to the block count circuit 7 and the area count circuit 9.

The byte information output from the code address storage circuit 12 is also supplied to the buffer memory 2, and the buffer memory 2 controls supply of the code data to the barrel shifter 3 based on the information. Further, the bit information output from the code address storage circuit 12 is
The data is supplied to the barrel shifter 3, and the barrel shifter 3 performs a bit shift based on the bit information.

By performing decoding for one macroblock by the above operations, one unit of ACL and A
The decoding of the ACH following the decoding of the CM ends.

According to the present embodiment, the necessary code can be accessed only by controlling the address to the code memory without having a buffer memory other than the code memory for storing the packed code as it is, and one video segment can be accessed. The ACL, ACM, and ACH depacking and decoding processes can be realized with only one buffer memory that stores the code data.

[0087]

According to the present invention, there is provided a depacking circuit in a decoding circuit of a compressed moving picture reproducing apparatus, wherein an address to a code memory is controlled without having a buffer memory other than a code memory for storing packed codes as they are. The required code can be accessed only by using only one buffer memory for storing the code data for one video segment, and the ACL, ACM and ACH data depacking processing can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment when ACL data is depacked in a depacking circuit of the present invention.

FIG. 2 shows ACL, A in the depacking circuit of the present invention.
FIG. 7 is a block diagram of a second embodiment when depacking CM data.

FIG. 3 shows ACL, A in the depacking circuit of the present invention.
FIG. 10 is a block diagram of a third embodiment when depacking CM and ACH data.

FIG. 4 is an explanatory diagram of a video segment which is a target of depacking processing and is a unit having a fixed data amount in the depacking circuit of the present invention.

FIG. 5 is an explanatory diagram of a flag set to an address in a flag memory in the depacking circuit of the present invention.

[Explanation of symbols]

2 buffer memory, 3 barrel shifter, 4 decode circuit, 7 block count circuit, 8 flag memory,
9 area count circuit, 10 flag memory, 12
Code address storage circuit, 13 ... Area end detection circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^7/ 24-7/68 H04N 5/91-5/95

Claims (4)

(57) [Claims] 1. A compressed image data divided into a predetermined number of blocks, encoded a predetermined number of blocks of data have been found pressure <br/> reduced moving image being packed in a predetermined number of codes in the area A decoding circuit for decoding data, a buffer memory means for storing code data of a predetermined number of blocks, a barrel shifter means for bit-shifting the code data output from the buffer memory means according to code length information and latching the result, Decoding means for decoding code data output by the barrel shifter means and returning a code length; as a first step, for each of the predetermined number of code areas,
The data from the head until the code indicating the end of the block of the image data appears is read from the buffer memory means. The data from the continuation of the end code to the appearance of the code indicating the end of the block of the image data is read out from the buffer memory means. Memory control means for reading , and a block being decoded in the first to third steps
Block address that generates a block address that identifies
And a block address generated by the block address generating means.
And the memory control means can control the first, second, and
And a third step . 2. The decoding circuit according to claim 1, further comprising area storage means for storing, for each block, the progress of an area in which the end of the decoded code of the block is located. 3. A flag memory means for indicating that a code to be linked to a code of another area exists in an area, and a linked area count means for indicating a position of an area of a code to be linked. A decoding circuit, comprising: 4. A decoding circuit for decoding compressed moving image data reproduced from a recording medium using the decoding circuit according to claim 1.