JP3302886B2 - Image synthesis device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing apparatus for converting two image signals into a synthesized image signal for displaying them in parallel on a single screen, and more particularly to reducing the capacity of a line buffer. Regarding improvement.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional image synthesizing apparatus as a background of the present invention. The image synthesizing device 151 converts a thinned image from two input image signals, a main image signal (main screen image signal) S1 and a sub image signal (sub screen image signal) S2, onto a single screen. This is a device that combines so-called double window images displayed in parallel and outputs the combined image signal S3.

The input image signals S1 and S2 include (horizontal and vertical) synchronization signals Sync1 and Sync2, respectively.
Each is accompanied. The image signals S1 and S2 are, for example, television reception signals of two channels, and generally need not be synchronized with each other. That is, the synchronization signal S
The pulses of sync1 and Sync2 do not always need to be input at the same time, and the time shift does not need to be always constant.

[0004] The image signals S1 and S2 are, for example, image signals of the YUV color system and have already been digitized. The main image signal S1 among these passes through the horizontal filter / thinning unit 1 so that the pixels along the horizontal direction (scanning line direction) are halved (that is, the thinning rate 1 /
2) is decimated. In addition, the signal of the pixel discarded in the process of thinning is mixed to a certain degree with the signal of the pixel after thinning by filtering. The image signal that has passed through the horizontal filter / thinning unit 1 is appropriately distributed to two line buffers A and D by the demultiplexer 11.

[0005] The other sub-image signal S2 passes through the horizontal filter / thinning section 2, whereby pixels along the horizontal direction are thinned out at a thinning rate of 1/2, and at the same time, are filtered. The image signal that has passed through the horizontal filter / thinning unit 2 is appropriately distributed to two line buffers B and C by the demultiplexer 12.

Alternatively, as shown in FIG. 7 , by further passing through the vertical filter / thinning section 4, thinning and filtering are also performed in the vertical direction (the direction orthogonal to the scanning lines). Vertical filter / thinning section 4
Allows a plurality of sub-image signals S2 to be displayed in parallel by performing thinning in the vertical direction.

Each of the four line buffers A to D has a storage capacity of 1/2 line. That is, each of the line buffers A to D can store one line of the image signal after being thinned out at a thinning rate of 1/2. The line buffers A and D are distributed by the demultiplexer 11 so that the thinned main image signal is
It is stored alternately for each line. Similarly, the line buffers B and C are alternately stored by the demultiplexer 12 so that the sub-image signals after thinning are alternately stored for each line.

[0008] The multiplexer 13 appropriately selects a line buffer in which writing is not in progress from the four line buffers A to D, and reads out the stored contents. The read image signal is written to the external DRAM 10 through the DRAM interface 7.

The DRAM 10 is, for example, a single port RAM of an EDO (Extended Data Out) type, and an image signal S input to the device 151.
Writing and reading can be performed at least twice as fast as the input speed of the pixel values of 1 and S2. Reading from each of the line buffers A to D is performed at the speed of writing to the DRAM 10. In other words, reading from each of the line buffers A to D is performed at twice or more the speed of writing to them.

The DRAM 10 has a storage capacity capable of storing image signals corresponding to two fields of main or sub image signals S1 and S2 before thinning. The DRAM interface 7 further reads out the thinned image signals S1 and S2 stored in the DRAM 10 for each line in an order in which they can be displayed in parallel on the same screen, and writes them to the line buffer 8. . The line buffer 8 outputs the written signal as a composite image signal S3 to the outside at the same speed as the image signals S1 and S2 input to the device 151.

The synchronizing signal Sync is included in the composite image signal S3.
3 is attached. As the synchronization signal Sync3, for example,
The synchronization signal Sync1 is output as it is. Then, the line buffer 8 outputs the synthesized image signal S3 to the synchronization signal Syn.
The timing of reading the composite image signal S3 is set so as to synchronize with c3.

The device 151 operates as described above, and thereby, the main image signal S1 and the sub image signal S2
On a single screen in the form of a double window. In particular, four line buffers A to D are provided between the horizontal filters / thinning units 1 and 2 and the DRAM 10, and the line buffers A to D are operated by the demultiplexers 11 and 12 and the multiplexer 13.
Since the image signals to be written and read are appropriately allocated between the two, the composite image signal S3 can always be obtained correctly even if the image signals S1 and S2 are not synchronized with each other.

In the above description, for the sake of simplicity, an example is described in which the thinning rate of each of the image signals S1 and S2 is 1/2, but the apparatus 151 sets the thinning rate to a value other than 1/2. Is also available. For example, the image signals S1, S
Even if the thinning rates of 2 are 3/4 and 1/4 respectively,
By appropriately allocating the image signals to the four line buffers A to D after the thinning, it is possible to obtain the composite image signal S3 corresponding to the double window.

[0014]

By the way, as described above, the conventional device 151 has four line buffers for writing to the DRAM 10, so that the area of the device becomes large and the manufacturing cost increases. There was a problem that the cost also increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional apparatus, and has as its object to provide a small and inexpensive image synthesizing apparatus in which the capacity of a line buffer is reduced.

[0016]

According to a first aspect of the present invention, a main image signal and a sub image signal input from the outside are thinned out at respective thinning rates, so that the main image signal after thinning and the thinned main image signal are thinned out. A first and a second thinning unit for outputting a sub-image signal after the thinning, respectively;
And a first selector which either selects and outputs the second thinning section the thinning-out after the main and thinned after sub image signals output from the selectively output from the first selector The main and sub-image signals after thinning can be sequentially written to an external storage medium, and the main and sub-image signals after thinning can be displayed in parallel on the same screen in an order that allows them to be displayed in parallel. The present invention relates to an image synthesizing apparatus capable of reading out main and sub image signals after thinning out from the storage medium, and sending out the synthesized image signals to the outside.

The first selecting section selects and outputs any one of first to third inputs, and the image synthesizing device operates between the first thinning section and the first input. A first buffer interposed, the second thinning unit, and the second buffer;
A second buffer which is interposed between the input, from among the two inputs connected respectively to the front SL outputs of the first and second thinning section, a second selector for selecting and outputting either the And a third buffer interposed between the output of the second selector and the third input. Further, the first
Each of the third to third buffers has a storage capacity corresponding to a half line of the main or sub image signal before thinning.

According to a second aspect of the present invention, in the image synthesizing apparatus according to the first aspect, the second buffer has two memory areas capable of simultaneously reading from one side and writing to the other side. And

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

<1. Outline of Apparatus> FIG. 1 is a block diagram showing a configuration of an image synthesizing apparatus according to an embodiment. In the following drawings, the same components as those of the conventional device 151 shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. The image synthesizing apparatus 101 synthesizes a double window image from the input main and sub image signals S1 and S2 and outputs the synthesized image signal S3 as in the conventional apparatus 151. The image signals S1 and S2 are, like the device 151,
Generally, they need not be synchronized with each other. That is, the timings at which the pulses of the synchronization signals Sync1 and Sync2 are input need not coincide with each other, and the timing shift does not need to be always constant.

The main image signal S1 is thinned in the horizontal direction at a predetermined thinning rate by passing through the horizontal filter / thinning section 1, and is converted into a filtered main image signal P1 after thinning. . Also,
The sub-image signal S2 passes through the horizontal filter / decimation unit 2 and the vertical filter / decimation unit 4 to be discarded in both the horizontal direction and the vertical direction at a predetermined decimation rate, and the filtering is performed on each of them. As a result, the image data is converted into the sub-image signal P2 after thinning.

The thinning rates of the two horizontal filters / thinning units 1 and 2 are calculated as the composite image signal S3 as the image signal S3.
Both S1 and S2 are set so that they can be displayed in parallel on a single screen. For example, if the thinning rate of the main image signal S1 is 3/4, the thinning rate of the sub image signal S2 is 1 /.
It is set to 4 or a smaller value.

The vertical filter / decimation unit 4 includes a device 151
Similarly to the above, this is a device portion installed for the purpose of also supporting a plurality of sub-image signals S2. That is, for the purpose of displaying a single sub-image signal S2 in parallel with the main image signal S1 as exemplified below, installation is not necessarily required.

The device 101 is provided with three line buffers A, B, and C as line buffers for writing to the DRAM 10. That is, the number is one less than the device 151. Line buffers A, B, C
All have a storage capacity of 1/2 line, like the device 151.

The device 101 further includes a line buffer control unit 3. This line buffer controller 3
Are supplied with synchronization signals Sync1 and Sync2.
The line buffer control unit 3 outputs these synchronization signals Sync
By transmitting control signals to the three line buffers A, B, and C, and the multiplexers 5 and 6 while measuring the time by 1, Sync2, the operation of these device parts is controlled.

The main image signal P1 after thinning is input to one input of the multiplexer 5 and the line buffer A, and the sub image signal P2 after thinning is input to the other input of the multiplexer 5 and the line buffer B. The multiplexer 5 selects one of the two input image signals P1 and P2 based on a control signal from the line buffer control unit 3, and inputs the selected image signal to the line buffer C as an image signal P3.

That is, the thinned main image signal P1, the thinned sub image signal P2, and the image signal P3 are written in the line buffers A, B, and C, respectively. The image signal P3 is the image signal P1 or the image signal P2
Therefore, the three line buffers A, B, and C store the image signal P1 and the image signal P2 in an appropriate manner.

The multiplexer 6 appropriately selects a line buffer for which writing is not in progress from the three line buffers A, B, and C based on a control signal from the line buffer control unit 3 and stores the stored contents. read out. The image signals P4, P5, and P6 read from the line buffers A, B, and C are respectively supplied to the multiplexer 6 and the DRA.
The image signal P7 is written to the external DRAM 10 through the M interface 7. As a result, DRAM
10 stores the thinned main image signal P1 and the thinned sub image signal P2.

The conditions relating to the reading and writing speeds of the DRAM 10 are as follows.
Same as 10. Therefore, the line buffers A,
Reading from each of B and C is performed at twice or more the speed of writing to each.

The DRAM interface 7 further includes a D
The main image signal P after thinning stored in the RAM 10
1 and the thinned-out sub-image signal P2 are read out for each line in an order in which they can be displayed in parallel on the same screen, and written to the line buffer 8 as the image signal P8. The line buffer 8 stores the written image signal P8.
At the same speed as the image signals S1 and S2. As the synchronization signal Sync3 accompanying the composite image signal S3, for example, the synchronization signal Sy
nc1 is output as it is.

The composite image signal S3 thus obtained
By inputting the synchronization signal Sync3 to an external display device, the main image signal S1 and the sub image signal S2 can be displayed in parallel on the same screen.

<2. Example 1 of Operation> FIG. 2 is an explanatory diagram showing an example of the operation of the apparatus 101. In the operation example of FIG. 2, both the image signals S1 and S2 are decimated by 1/2 (decimation rate 1 /
2). Then, a composite image signal S3 that displays these in parallel as a main screen 91 and a sub-screen 92 on a single screen 90 at a division ratio of 1: 1 is output. Hereinafter, the operation of each unit of the apparatus 101 will be described in detail based on the operation example of FIG.

FIG. 3 is a timing chart corresponding to the operation example of FIG. FIG. 3 shows a period T ₀ during which image signals on four lines from the Nth line (the Nth scanning line) to the N + 3 line are input as the main image signal S1.
Image signals of each unit of the apparatus 101 in the through T ₃ are shown.

In FIG. 3, the input image signals S1, S2
In order to clarify the correspondence between the image signals S1 and S2, the same line numbers as those given to the image signals S1 and S2 are used.
It is also attached to the corresponding image signal. The line numbers assigned to the image signal P8 and the composite image signal S3 drawn at the bottom are the line numbers one field before the line numbers assigned to the other image signals.

In the example shown in FIG. 3, the synchronization signal Sync3 output together with the composite image signal S3 is the synchronization signal Sync.
It is consistent with c1. Also, as shown in FIG. 3, the synchronization signal Sync1 and the synchronization signal Sync2 generally do not match. The image signals S1 and S2 for one line are input following the pulses of the (horizontal) synchronization signals Sync1 and Sync2. Also, the (horizontal) synchronization signal Sync3 (= Sy
Following the pulse of nc1), a combined image signal S3 for one line is output.

Following the pulse of the synchronization signal Sync1,
One line of the image signal P8 is read from the DRAM 10 and written into the line buffer 8. The speed of the image signal P8 input to the line buffer 8 is extended, and is output as a composite image signal S3. Period T _0-
Each T _3, i.e., in one cycle of the synchronizing signal Sync1 pulses until the next pulse, the period after the reading of the image signal P8 is completed, the period can be written to the DRAM 10.

The reading of the image signal P8 is performed by the image signal S8.
Since it is performed at a speed more than twice the input speed of 1, S2,
The time required to read the image signal P8 for one line is:
It is sufficient that the period is not more than half the period during which the image signal S1 or S2 is input. Therefore, in one cycle, a period in which a blank period after the main image signal S1 is input is added to a period that is equal to or more than 期間 the period during which the main image signal S1 is input, and the period in which the DRAM 10 can be written Period is secured.

In one cycle of the synchronization signal Sync1, one line of the main image signal S1 is sequentially converted by the horizontal filter / thinning section 1 into a main image signal P1 after thinning at a thinning rate of 1/2. At the same time, the data is written to the line buffer A. Then, in one cycle, the image signal P4 is read from the line buffer A using a blank period after the input of the main image signal S1 is completed.

This reading is performed at twice or more the speed of writing, and the image signal P4 is thinned out by half. Therefore, the period required for reading is the same as the period during which the main image signal S1 is input. A length of 1/4 or less is sufficient.
The image signal P4 is read out from the line buffer A and simultaneously written into the DRAM 10 as an image signal P7. That is, the image signal P7 is written using the blank period included in the period in which writing to the DRAM 10 is possible.

In one cycle from one pulse to the next pulse of the synchronization signal Sync2, the sub-image signal S2 for one line is divided by the horizontal filter / decimation unit 2 at a decimation rate of 1/2, and It is sequentially converted to an image signal P2. The multiplexed sub-image signal P2 is supplied to the line buffer B (P in FIG.
2) and the line buffer C (P3 in FIG. 3) are written alternately.

The reading of the image signals P5 and P6 from the line buffers B and C is performed at twice or more the speed of the writing, and the image signals P5 and P6 are divided by 1 /.
Since the two sub-pixels are thinned out, the period required for reading is sufficient to be not more than １ ／ of the period during which the sub-image signal S2 is input.

The read image signals P5 and P6 are simultaneously written to the DRAM 10 as an image signal P7.
Therefore, the image signals P5 and P6 are read out from the DRAM 1
This is performed by selecting a period excluding the period in which the image signal P4 is read from the period in which writing to 0 is possible. The length of the limited period is large enough to read the image signals P5 and P6.

Since the sub-picture signal P2 after thinning is alternately written to the two line buffers B and C every one cycle, the sub-picture signal P2 after thinning from these line buffers B and C is converted into the image signals P5 and P5. By alternately reading as 6, the write period and the read period can be prevented from overlapping in the same line buffer, and the read period can be appropriately selected from the limited periods. .

This means that the two synchronization signals Sync1,
It does not change regardless of the timing of the Sync2 pulse. In the example of FIG. 3, the image signal P8
Are completed, the image signals P5 and P6 are read using the period until the reading of the image signal P4 from the line buffer A is started.

<3. Second Operation Example> FIG. 4 is an explanatory diagram showing another operation example of the apparatus 101. In the operation example of FIG. 4, the main image signal S1 is thinned out by 3/4, and the sub image signal S2 is thinned out by 1/4. And
Put them on a single screen 90, main screen 91,
As the sub-screen 92, a composite image signal S3 to be displayed in parallel at a division ratio of 3: 1 is output. Hereinafter, the operation of each unit of the device 101 will be described in detail based on the operation example of FIG.

FIG. 5 is a schematic diagram showing a configuration example of the line buffer B for realizing the operation of FIG. As shown in FIG. 5, the memory space of the line buffer B is divided into two memory areas called banks. Accordingly, each of the banks Ma and Mb is １ ／
It has a capacity to store image signals for lines.

While data is being written to one bank, the other bank is in a readable state. Therefore, writing of the sub-image signal P2 after thinning is performed alternately for each of the two banks Ma and Mb every period, and reading is performed to the bank to which writing has not been performed. The configuration of such a memory space and the write / read operation in the line buffer B are determined by the control of the line buffer control unit 3.

FIG. 6 is a timing chart corresponding to the operation example of FIG. In one cycle of the (horizontal) synchronization signal Sync1, one line of the main image signal S1 is sequentially converted by the horizontal filter / thinning section 1 into the thinned main image signal P1 at a thinning rate of 3/4, At the same time, the line buffer A (P1 in FIG. 6) and the line buffer C (FIG.
And P3).

In one cycle, when the writing of the main image signal P1 to the line buffer A after the thinning is completed, the reading of the image signal P8 from the DRAM 10 is completed, and the writing to the DRAM 10 is possible. It has become. Then, at the same time as the writing target shifts from the line buffer A to the line buffer C, reading of the image signal P4 from the line buffer A is started.

When the reading from the line buffer A is completed, the writing of the main image signal P1 to the line buffer C after the thinning is completed. Therefore, as soon as the reading of the image signal P4 from the line buffer A is completed, the reading of the image signal P6 from the line buffer C is performed. In this way, in the example of FIG. 6, the thinned main image signal P1 distributed and written to the line buffers A and C is continuously read from the line buffers A and C and simultaneously written to the DRAM 10.

In one cycle from one pulse of the (horizontal) synchronization signal Sync2 to the next pulse, the sub-image signal S2 for one line is divided by the horizontal filter / decimation unit 2 at a decimation rate of 1/4. Subsequent conversion to the sub-image signal P2 is performed. The thinned-out sub-image signals P2 are alternately written to the two banks Ma and Mb in the line buffer B every one cycle as image signals P2a and P2b.

From these banks Ma and Mb, the sub-image signals P2 after thinning are converted into image signals P5a and P5b, respectively.
Is read as Further, the read image signal P5
a and P5b are written into the DRAM 10 at the same time.
In one cycle, the time required for reading out the image signals P5a and P5b is 1/1 of the period during which the sub-image signal S2 is input.
A length of eight times or less is sufficient.

The reading of the image signals P5a and P5b is performed by D
From the period in which writing to the RAM 10 is possible, the image signal P
4 and P6 are performed by selecting a period excluding the period during which they are read. The length of this limited period is determined by the image signal P
5a and P5b are large enough to read.

Since the sub-image signal P2 after thinning is alternately written to the two banks Ma and Mb every period, the sub-image signal P2 after thinning is alternately read from these banks Ma and Mb. These reading periods can be appropriately selected from the limited periods. This means that the two synchronization signals Sync
It does not change regardless of the relationship between the timing of the pulse of Sync1 and that of Sync2.

In the example of FIG. 6, the image signal P8 in one cycle
Is completed, the period from when the reading of the image signal P4 from the line buffer A is started is selected.
Image signals P5a and P5b are read.

In the above description, as shown in FIG. 4, the division ratio between the main screen 91 and the sub-screen 92 displayed in parallel in a single screen 90, that is, the ratio of the thinning rate of the image signals S1 and S2 is The example of 3: 1 has been described. However,
In the device 101 configured as shown in FIG. 1, the line buffer B is equally divided into two banks as shown in FIG. 5, thereby making the line buffer B more than 3: 1 (for example, 7: 2, 4: 1, 5:
, Etc.) are generally possible.

[0056]

In the device of the first invention, the main and sub-image signals after thinning are distributed and written into three buffers by the operation of the second selecting section. Then, the main and sub-image signals after thinning out are selectively read from the three buffers by the operation of the first selection unit. Therefore, even if the main and sub image signals are not synchronized with each other, it is possible to obtain a composite image signal in which the main and sub image signals are displayed in parallel on the same screen with a division ratio of at least 1: 1. In addition, the number of line buffers is reduced by one as compared with the conventional device, so that the device can be downsized and the manufacturing cost can be reduced.

In the device according to the second aspect, the second buffer comprises:
Since there are two memory areas where reading from one side and writing to the other side can be performed at the same time, even if the main and sub image signals are not synchronized with each other, the main and sub image signals can be divided at an arbitrary division ratio of 3: 1 or more. A composite image signal that displays the image signals in parallel on the same screen can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image synthesizing apparatus according to an embodiment.

FIG. 2 is an explanatory diagram showing an operation example of the device of FIG. 1;

FIG. 3 is a timing chart corresponding to the operation example of FIG. 2;

FIG. 4 is an explanatory diagram showing another operation example of the device of FIG. 1;

FIG. 5 is a block diagram showing a configuration of a line buffer B of the device of FIG.

FIG. 6 is a timing chart corresponding to the operation example of FIG. 4;

FIG. 7 is a block diagram of a conventional image synthesizing apparatus.

[Explanation of symbols]

 Reference Signs List 1 horizontal filter / thinning section (first thinning section) 2 horizontal filter / thinning section (second thinning section) 5 multiplexer (second selecting section) 6 multiplexer (first selecting section) 10 DRAM (storage medium) A, B, C line buffer (first to third buffers) S1 main image signal S2 sub image signal S3 composite image signal P1 main image signal after thinning P2 sub image signal after thinning

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI G09G 5/397 G06F 15/66 450 5/399 G09G 5/00 555W H04N 5/265 5/36 520C 5/45

Claims (2)

(57) [Claims] A first and a second sub-image signal output from the external device, wherein the main image signal and the sub-image signal are externally input and each of which outputs a main image signal and a sub-image signal after the thinning. comprising a second thinning section, and a first selection unit for one selects and outputs of the first and after the decimation respectively output from the second thinning section main and thinned after the sub-image signals, the first selection It is possible to sequentially write the post-thinning-out main and sub-thinned image signals selectively output from the unit to an external storage medium, and further, that the thinned-out main and sub-thin image signals are arranged in parallel on the same screen. An image synthesizing apparatus which can read out the main and sub image signals after thinning out from the storage medium in the order in which display is possible, and send the read out main and sub image signals to the outside as a synthesized image signal . The first selection unit selects and outputs one of first to third inputs, and the image synthesizing device includes a first buffer inserted between the first thinning unit and the first input; a second buffer which is interposed between said second input and said second thinning section, from among the two inputs connected respectively to the front SL outputs of the first and second thinning section selects one And a third buffer interposed between the output of the second selector and the third input, wherein each of the first to third buffers has a An image synthesizing apparatus having a storage capacity corresponding to a half line of the main or sub image signal. 2. The image synthesizing apparatus according to claim 1, wherein said second buffer has two memory areas capable of simultaneously reading from one side and writing to the other side. .