JP3303022B2 - Controller integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit (hereinafter referred to as "CPU") and a controller integrated circuit used as an input / output interface of peripheral equipment such as a copying machine, a facsimile, a vending machine, and the like. .

[0002]

2. Description of the Related Art Conventional types of controller integrated circuits include, for example, address decoders, control logic circuits,
It has a data bus buffer, a control word register, and an input / output (IO) port. Any one of the input / output directions of each port address is programmably written to the control word register in advance based on a software command from the CPU. The O port can be set to either input or output.

Therefore, when outputting data written to a CPU using a conventional controller integrated circuit,
When a data signal is input to the data bus buffer of the controller integrated circuit in response to an output request from the CPU, a data signal is output from each I / O port which is previously set as an output in the control word register by software, and is output to the terminal of each port. The connected peripheral device is driven. Conversely, when a data signal is input from the peripheral device to the CPU and written, the data signal of the peripheral device is input from a terminal of each I / O port set in advance by software in response to an input request from the CPU. The data signal of the I / O port is read. When a conventional controller integrated circuit is incorporated, for example, a controller integrated circuit connected to an 86-series CPU and a controller integrated circuit connected to a 68-series CPU are selectively used.

[0004]

However, in the case of a conventional controller integrated circuit, a predetermined control word register is selected on the basis of an address signal from the CPU, and the I / O is controlled with respect to the port address of the control word register. Since any of the input / output directions of the O port is written in software, for example, if the CPU is reset for any reason, a reset signal is input to the controller integrated circuit, and the control word register and the like are initialized. Returns to the input state of
When the I / O port is returned to the original I / O state, there is a problem that the I / O direction of each I / O port must be set again in the control word register.

Further, in the case of a conventional controller integrated circuit, since it can be used only for a specific CPU, each of the Cs is set according to the type of CPU.
There has been a problem that a controller integrated circuit suitable for the PU has to be selected, which lacks versatility as an input / output interface element.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and provides a controller integrated circuit capable of holding an input / output port in an initially set state even when a CPU is reset. For example, 86 series C
It is an object of the present invention to provide a versatile controller integrated circuit applicable to both a PU and a 68-series CPU.

[0007]

According to a first aspect of the present invention, there is provided a controller integrated circuit having a plurality of input / output terminals for inputting / outputting data signals between a central processing unit and peripheral devices. A controller integrated circuit for controlling the input / output direction holding register which holds an external signal which is independent of a reset signal of the central processing unit and which sets an input / output direction of each terminal in a hardware manner; An internal register that holds an input / output direction setting signal that sets the output direction in a software programmable manner based on a signal from the central processing unit, and an external signal that sets the input / output direction of the input / output holding register are input. And a mode selection signal for selecting whether to set the input / output direction in software or hardware in cooperation with the external signal. Have a mode selection terminal, the de
Data signal and the internal register
Signal line for setting input / output direction setting signal by software is common
Is what you are doing .

According to a second aspect of the present invention, there is provided a controller integrated circuit having a plurality of input / output terminals for controlling input / output of data signals between a central processing unit and peripheral devices. In the circuit, an input / output direction holding register that holds an external signal that is independent of a reset signal of the central processing unit and sets the input / output direction of each terminal in a hardware manner, Software-based programming based on signals from the central processing unit
An internal register for holding an input / output direction setting signal to be set to be programmable, a plurality of external signal terminals to which external signals for setting the input / output direction of the input / output holding register are input,
A first mode selection terminal to which a mode selection signal for selecting whether to set the input / output direction by software or hardware in cooperation with the external signal is input; And a mode for selecting the type of central processing unit and changing the function of each of the input / output request terminals according to the selected central processing unit. have a second mode selection terminal for selecting signal is input, the signal lines passing the data signal
And input / output direction setting signal to the internal register.
Signal lines to be set in common are common .

[0009]

According to the first aspect of the present invention, when a mode selection signal for selecting a soft mode is input to the mode selection terminal, the central processing unit inputs and outputs a data signal to an internal register. When a direction setting signal is input, the signal is held in a pre-designated internal register, and the input / output directions of a plurality of terminals are set to the internal register by software.
Can be set programmable . When a mode selection signal for selecting a hard mode is input to the mode selection terminal, an external signal is input to a plurality of external signal terminals and input to an input / output holding register designated by these external signals. The output direction can be set by hardware. When the input / output direction is set by hardware, the input / output holding register is independent of the reset signal of the central processing unit. Therefore, even if the controller integrated circuit enters the input state by the reset signal, the input / output holding register is used. Can maintain a state set by hardware by an external signal before reset.

According to the second aspect of the present invention, after the controller integrated circuit is mounted, the second mode selection signal is input from the second mode selection terminal and the center of the 86 series or 68 series is input. When a processor is selected and a mode suitable for the central processor is selected, the functions of the pair of input / output request terminals are changed according to the selected central processor. When a mode selection signal for selecting the soft mode is input to the first mode selection terminal, when the input / output direction setting signal is input as a data signal from the central processing unit to the internal register, the signal is designated in advance. Retained in the internal register, and the input / output direction of multiple terminals can be software programmed for the internal register
It can be set to have. Further, when a mode selection signal for selecting a hard mode is input to the first mode selection terminal, an external signal is input to a plurality of external signal terminals, and an input / output holding register designated by these external signals is input. The input / output direction can be set by hardware. When the input / output direction is set by hardware, the input / output holding register is independent of the reset signal of the central processing unit. Therefore, even if the controller integrated circuit enters the input state by the reset signal, the input / output holding register is used. Can maintain a state set by hardware by an external signal before reset.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the embodiments shown in FIGS. The controller integrated circuit of the present embodiment is a microprocessor unit (MPU) not shown.
It is configured as an 8-bit input / output interface element connected between the MPU and the peripheral device for transmitting and receiving 8-bit data signals D0 to D7 between the MPU and the peripheral device. That is, as shown in FIG. 1, the controller integrated circuit includes a data bus buffer 1 and an address decoder 2 connected to a CPU constituting an MPU, and a controller logic circuit configured as a negative logic circuit connected to the address decoder 2. 3 and the controller logic circuit 3
A control word register (CWR) 4 as an internal register and an input / output (I / O) port 5 as an input / output holding register to which a control signal is input from the CPU, and data between a CPU and peripheral devices constituting an MPU. Signals D0 to D7
And an 8-bit data bus 6 serving as a path for transferring the data.

The control word register 4 is composed of four registers CWR (0) to CWR (3) as described above, and the I / O port 5 is an I / O port.
It consists of nine registers of ports (1) to (9). Each of the I / O ports (1) to (9) has eight input / output terminals (not shown) so as to input and output 8-bit signals. Driving devices such as motors and lamps of peripheral devices are connected to the input / output terminals of (9), and these driving devices are driven by bit signals.
The output current of each I / O port (1) to (8) is 3.2 m
A, but the output current of the I / O port (9) is 12.0 mA
To allow peripheral devices to be driven with a higher current than the other ports.

Further, the data bus buffer 1 includes a CP
The address decoder 2 adjusts the input / output timing of the data signals D0 to D7 between the U and the peripheral device. The address decoder 2 controls the address signals A0, A1, A
2. Decode A3 and decode the decoded address signals A0, A1, A
2, one of four CWRs (0) to (3) is selected in cooperation with A3 and a signal (control word) for setting a mode and the like described later, and nine I / O ports ( Any one of 1) to (9) is selected.

The controller logic circuit 3 is configured as a negative logic circuit.
A reset signal input terminal 7 for receiving a reset signal for initial setting from the CPU, and a CS input terminal 8 for receiving a chip select (CS) signal for opening and closing the data bus 6.
And reading of data signals D0 to D7 of peripheral devices (input)
Is connected to a RD input terminal 9 to which a read (RD) signal for requesting the data is input and a WR input terminal 10 to which a write (WR) signal for requesting the writing (output) of the CPU data signals D0 to D7 are input. . These signals are used as active low control signals by the controller logic circuit 3.
To control the data bus buffer 1, control word register 4 and I / O port 5 via the controller logic circuit 3 and the address bus 11. The control word register 4 is connected to an I / O port 5 via an address bus 11 and controls the I / O port 5 assigned to each via the control word register 4.

Each of the above-mentioned signals has the following functions. The combination of the above-mentioned signals with the above-mentioned address signals A0, A1, A2, and A3 causes the control word register 4 and the IOs
Port 5 is controlled. For example, when the reset signal is an L level signal, the controller integrated circuit is set to an initial state, and when the CS signal is an L level signal, the data bus 6 is opened to transfer data signals D0 to D7 with the MPU. is there. When the RD signal is an L level signal and the WR signal is an H level signal, predetermined data signals D0 to D7 input to each port 5 are read from the peripheral device, and the WR signal is an L level signal and the RD signal is an H level. In the case of a signal, the data of the CPU is transmitted via the data bus 6 to each control word register 4 and each I / O port 5.
, Predetermined data signals D0 to D7 are written to the I / O port 5, and the data signals D0 to D7 are output to peripheral devices. These signals are combined as shown in FIGS. 5A and 5B to select each of the I / O ports (1) to (9), and to control the CPU based on the input / output setting signal from the CPU. The input operation or the output operation can be controlled.

The controller logic circuit 3
Are three external signal terminals 12, 1 as shown in FIG.
3 and 14 and an IOS0 signal, I
The OS1 signal and the IOS2 signal are input from the external signal terminals 12, 13, and 14 as external signals. The input / output directions of the I / O ports (1) to (9) can be set by hardware using the IOS0, IOS1, and IOS2 signals. Furthermore, a mode selector 15 is connected to the controller logic circuit 3, and an MS signal is input to a mode selection (MS) terminal 16 of the mode selector 15. As shown in FIG. 2, a soft mode in which the input / output direction is set in a software manner and a hard mode in which the input / output direction is set in a hardware manner can be appropriately selected by the MS signal of the mode selector 15, as shown in FIG. When the MS signal is an L level signal and all the external signals are L level signals, the soft mode is selected, and in other cases, the hard mode is selected. Also,
There are two hard modes, and the hard mode and the hard mode can be selected according to the difference between the L level signal or the H level signal of the MS signal.

The CWR (0) to CWR (3) constituting the control word register 4 are the address signals A
Each is selected according to 0, A1, A2, and A3. Port addresses are formed in these CWR (0) to CWR (3) as shown in FIG. 4, and the input / output setting signal of the CPU is set to the L level signal (output direction) or the H level signal ( Input direction) as each CW
The input / output direction of the I / O port (see FIGS. 1 and 3) assigned to each of the port addresses R (0) to (3) is set by software from the CPU.

As shown in FIGS. 2A and 4, the above CW
R (0) is a register for setting the input / output direction of the I / O port (8) so that the input / output direction can be set in units of bits or nibbles (4 bits). The CWR (1) is a register for setting the input / output direction of the I / O ports (1) to (3). The input / output direction of the I / O port (2) can be set in nibble units or 8-bit units. The other I / O ports (1) and (3) can be set only in 8-bit units. The above CWR (2) is I / O port (4) ~
This register sets the input / output direction of (6).
For (5), the input / output direction can be set in nibble units or 8-bit units, and other I / O ports (4) and (6) can be set only in 8-bit units. Further, the CWR (3) is a register for setting the input / output direction of the I / O ports (7) and (9). Each of the I / O ports (7) and (9) is input / output only in 8-bit units. The direction cannot be set.

Next, a method of setting the input / output of the I / O port 5 will be described. When selecting the soft mode, as shown in FIG.
The signal is set to the L level signal, and the IOS0 signal, the IOS1 signal, and the IOS2 signal are set to the L level signals. This places the controller integrated circuit in soft mode. Next, as shown in FIG. 5B, the CS signal is L, the RD signal is H,
The WR signal is set to L so that the CPU can write data signals D0 to D7. Thereafter, address signals A0, A1, A2, and A3 are sent from the CPU to L and H corresponding to FIG.
Are output to the address decoder 2 by the combination of the above, the combination is decoded by the address decoder 2, and each I / O port (1) to (9) and each of the CWR (0) to (3) are The designation is made as shown in FIG. Further, the CS signal and the WR signal are set to L, and an 8-bit input / output setting signal is output from the CPU as a control word of an L level signal and an H level signal via a data bus, and each CWR (CWR) shown in FIG. 0) to CWR
Write to (3) and corresponding I / O ports (1)-
Set the input / output direction of (9). When the CS signal is set to L, the RD signal is set to L, and the WR signal is set to H, the data of the peripheral device is changed from the input I / O port via the data bus to the data signals D0 to D7 in response to an input request from the CPU.
Input to U, set the CS signal to L, the RD signal to H, and the WR signal to L. If there is an output request from the CPU, output the CPU data from the output I / O port as data signals D0 to D7 to peripheral devices. I do.

When the hard mode is selected, as shown in FIG.
If the S signal is an H level signal, the IOS0 signal, IOS1 signal
The signal and the IOS2 signal may be set to either an L level signal or an H level signal. The input / output direction of the I / O ports (1) to (7) can be set directly as shown in FIG. 6B by a combination of these external signals. Each of the I / O ports (1) to (7) is collectively set to either the input direction or the output direction as shown in FIGS. 6 (a) and 6 (b). Each of these I / O
The input / output directions of the ports (1) to (7) can be set as shown in FIG. 6B by combining H and L of the IOS0 signal, the IOS1 signal, and the IOS2 signal. However, I /
As described above, the input / output direction of the O port (8) is set by software by the CWR (0), and the I / O port (9) is always set to the output. When the controller integrated circuit is set to the hard mode, an external signal independent of the CPU, I
Each I / O by OS0 signal, IOS1 signal and IOS2 signal
Since the input / output direction of the ports (1) to (7) is set, the CPU is reset, and even if the reset signal is input to the controller integrated circuit, unlike the case of the soft mode, each I / O Ports (1) to (7) can maintain the initial settings.

When the hard mode is selected, if the MS signal of the mode selector 15 is set to the L level signal as shown in FIG. 2, the IOS0 signal, the IOS1 signal and the IOS2 signal will be in a state other than the soft mode. In other words, any state other than when all the external signals are L level signals may be used. In this case, the input / output direction of each I / O port is the same as in the hard mode except that the I / O port (1) is always set to the input state as shown in FIGS. 7 (a) and 7 (b). Is set. Also in this case, the initial setting state can be maintained as it is after the reset without being affected by the reset signal as in the hard mode.

As described above, according to this embodiment, C
An external signal (IOS0) that is independent of the PU reset signal and that sets the input / output directions of a plurality of input / output terminals in hardware.
Signal, IOS1 signal, and IOS2 signal), external signal terminals 12, 13, and 14 are provided, and a mode selector 15 for selecting between a hard mode and a soft mode is provided. The I / O ports (1) to (7) and (9) of the integrated circuit can be maintained in the initial setting state without being reset, and it is necessary to reset the input / output direction every reset. Absent.

As shown in FIGS. 8 and 2B, a controller integrated circuit according to another embodiment of the present invention has an external signal (IOS0) independent of the reset signal as in the above embodiment. Signals, IOS1 signal, IOS2 signal), and MS for selecting one of the soft mode and the hard mode in cooperation with the external signals.
Although a first mode selection terminal 16 to which a 0 signal is input is provided, this embodiment is different from the above embodiment in that the hard mode has only one mode. Furthermore, a major difference from the above-described embodiment is that the controller integrated circuit of the present embodiment can support a plurality of (two in this embodiment) CPUs and is configured as a highly versatile input / output interface. is there.

That is, the mode selector 15 of the controller integrated circuit of the present embodiment is connected to the second mode selection terminal 17 to which the MS1 for selecting the CPU is inputted as shown in FIG. And when it is 86 system CPU, MS1
Signal is an L level signal.
The signal is changed to an H level signal. And 8
When a 6-system CPU is selected, an RD signal is input to the RD input terminal 9 as shown in FIGS.
The WR signal is input to the input terminal 10 so as to perform the same function as in the above embodiment. Further, FIG.
As shown in (b), a data signal is read from each of the I / O ports (1) to (9) specified by the address signals A0, A1, A2, and A3, and each of the CWRs (0) to (3) or each IWR is read. Data signals are written to the / O ports (1) to (9).

However, when the MS1 signal is set to H and a 68-system CPU is selected, the function of the RD input terminal is changed to the RW input terminal as shown in FIGS. 10 (a) and 10 (b). It has a function of inputting both the RD signal and the WR signal, and the function of the WR input terminal has a function of inputting an enable (MEN) signal for permitting the input of the RD signal or the RW signal. When the RW signal is H and the MEN signal is L, a data signal is read from each of the I / O ports (1) to (9). When the RW signal is L and the MEN signal is L, each of the CWR (0) to (3) is read. ) Or each I / O port (1) ~
The data signal is written in (9).

As described above, according to this embodiment, M
If the S0 signal is used, either the soft mode or the hard mode is selected in the same manner as in the above embodiment, and in the case of the hard mode, the operation and effect according to the above embodiment can be expected.
Further, in the present embodiment, if the second MS signal is used, the 86 system C
The present invention can be applied to a PU and a 68-series CPU, so that the versatility as an input interface can be enhanced.

It goes without saying that the present invention is not limited to the above embodiments.

[0028]

As described above, according to the first aspect of the present invention, a plurality of input / output terminals are provided.
Input and output data signals between the central processing unit and peripheral devices
In the controller integrated circuit to be controlled, the central processing
Independent of the reset signal of the processor and the input of each terminal
I / O that holds external signals that set the output direction in hardware
Force input holding register and input / output direction of each terminal above
Software based on the signal from the central processing unit.
Holds the input / output direction setting signal to be set to be programmable
How to input / output the internal registers and the input / output holding registers
Multiple external signal terminals for inputting external signals to set the direction
And input / output directions can be set in software in cooperation with the external signal.
Mode selection signal to select whether to set
And a mode selection terminal for inputting a signal.
Signal line for passing the signal
Signal lines for setting direction setting signals by software are common.
Data from the central processing unit to internal registers.
I / O setting signal in soft mode using data signal
Even if the CPU is in the reset state, the input / output port can be kept in the initial setting state set in the hard mode, and the input / output direction can be changed every reset.
Between the central processing unit and peripheral devices without resetting
It is possible to provide a controller integrated circuit capable of transmitting and receiving data signals .

According to the second aspect of the present invention , the central processing unit has a plurality of input / output terminals.
To control the input and output of data signals between the
In the roller integrated circuit, the reset of the central processing unit is performed.
And the input / output direction of each terminal is independent of the
Input / output direction holding level for holding external signals
The central processing of the register and the input / output direction of each terminal
Software programmable based on the signal from the device
Internal register that holds the input / output direction setting signal to be set
And set the input / output direction of the input / output holding register
A plurality of external signal terminals for inputting external signals
Set the input / output direction by software in cooperation with the signal
Mode selection signal for selecting whether to set
Any of the first mode selection terminal and the input / output of each of the above terminals
Input / output request terminals
And the type of the central processing unit is selected and the selected
Function of each input / output request terminal according to the central processing unit
Mode selection terminal to which a mode signal for changing the mode is input
And a signal line for passing the data signal.
Set the above input / output direction setting signal in the software register
Signal lines are common, so the central processing unit
Input / output settings for internal registers using data signals
Signal can be set in software mode, CPU can also be kept input and output ports of the initial setting state set by the hard mode in the reset state, Li
Central processing without resetting the input / output direction for each set
Transfer of data signals between the
Can be performed, and for example, the CPU of the 86 series and the 68
It is possible to provide a versatile controller integrated circuit that can be applied to both system CPUs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a controller integrated circuit of the present invention.

FIG. 2 is a table showing states of an MS signal and an external signal when a soft mode and a hard mode are selected in the controller integrated circuit shown in FIG. 1; FIG. FIG. 2B shows the second embodiment.

FIG. 3 is a list showing functions of a control word register of the controller integrated circuit shown in FIG. 1;

FIG. 4 is a conceptual diagram showing a register of a control word register of the controller integrated circuit shown in FIG. 1;

5 is a table showing input / output directions of I / O ports set in a soft mode by a control word register of the controller integrated circuit shown in FIG. 1;

6 (a) is a list showing functions of external signals of the controller integrated circuit shown in FIG. 1, and FIG. 6 (b) is an I / O set by a hard mode based on external signals.
4 is a list showing input / output directions of ports.

7A is a list showing functions of external signals of the controller integrated circuit shown in FIG. 1, and FIG. 7B is a table showing I / Os set in a hard mode by external signals;
4 is a list showing input / output directions of ports.

FIG. 8 is a block diagram showing another embodiment of the controller integrated circuit of the present invention.

FIG. 9 is a block diagram showing the controller integrated circuit shown in FIG.
6 is a table showing input / output directions of I / O ports set in a soft mode by a control word register when applied to a PU.

10 is a table showing input / output directions of I / O ports set in a soft mode by a control word register when the controller integrated circuit shown in FIG. 8 is applied to a 68-series CPU.

[Explanation of symbols]

4 Control word register (internal register) 5 I / O port (input / output direction holding register) 7 Reset signal input terminal 8 RD signal input terminal (input / output request terminal) 9 WR signal input terminal (input / output request) 12 External signal terminal 13 External signal terminal 14 External signal terminal 16 MS terminal (mode selection terminal, first mode selection terminal) 17 2nd MS terminal (second mode selection terminal)

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Koichi Yomiya 5-3-1-16 Akasaka, Minato-ku, Tokyo Inside Tokyo Electron Co., Ltd. (56) References JP-A-63-155354 (JP, A) JP-A-63-155354 Hei 6-243086 (JP, A) JP-A-60-218140 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13/10-13/14

Claims (2)

(57) [Claims] 1. A controller integrated circuit having a plurality of input / output terminals and controlling input / output of data signals between a central processing unit and peripheral devices, wherein the controller integrated circuit is independent of a reset signal of the central processing unit. And an input / output direction holding register for holding an external signal for setting the input / output direction of each terminal in a hardware manner, and a software programmable input / output direction of each terminal based on a signal from the central processing unit. set to an internal register for holding the output direction setting signal, and a plurality of external signal terminal to which an external signal is input to set the input and output direction of the output holding register, the external signal in cooperation with the input It has a mode selection terminal a mode selection signal for selecting whether to set the output direction or by hardware by software to set inputs, and a signal line passing the data signal The internal register
Signal line for setting the above input / output direction setting signal by software
Controller integrated circuit, characterized in that There are common. 2. A controller integrated circuit having a plurality of input / output terminals and controlling input / output of data signals between a central processing unit and peripheral devices, wherein the controller integrated circuit is independent of a reset signal of the central processing unit. And an input / output direction holding register for holding an external signal for setting the input / output direction of each terminal in a hardware manner, and a software programmable input / output direction of each terminal based on a signal from the central processing unit. set to an internal register for holding the output direction setting signal, and a plurality of external signal terminal to which an external signal is input to set the input and output direction of the output holding register, the external signal in cooperation with the input Requests a first mode selection terminal to which a mode selection signal for selecting whether to set the output direction by software or hardware, and one of input / output of each terminal And a mode signal for selecting the type of the central processing unit and changing the function of each of the input / output request terminals according to the selected central processing unit. It has a second mode selection terminal for inputting a signal line passing the data signal, the internal registers
Signal line for setting the above input / output direction setting signal by software
Controller integrated circuit, characterized in that There are common.