JP3306901B2 - Cache memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory for performing high-speed memory access in a microprocessor.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a dirty bit of a conventional write-back type cache memory. Here, for the sake of simplicity, a direct map cache memory is used. The clock is a two-phase clock. The dirty bit holds information indicating that data has been updated by a write operation to the cache, and thus has the effect of preventing data from being written to an external memory and reducing bus traffic. Reference numeral 100 denotes a precharge circuit using a P-channel transistor for precharging a bit line, and 101 denotes a clock xph2 obtained by inverting ph2 of a two-phase clock for controlling precharge. Therefore, when ph2 is HIGH, xph2 becomes LOW, turning on the P-channel transistor. 104 is a word line WL0 corresponding to the 0th cache line of the cache memory.
And a storage circuit for storing information indicating the update of data connected to the bit line B and its inverted bit line XB, that is, dirty bits. Here, for simplicity, the storage circuits 104, 10 corresponding to the first and last two lines
Only 9 is shown. 102 and 103 are bit lines, respectively
N and N-channel transistor 105 connected to bit line XB,
The memory cells are accessed via the memory cells 2 and 103.
Reference numeral 106 denotes a driver for reading data from or writing data to the bit lines B and XB. Reference numeral 107 denotes write data related to dirty bits, and reference numeral 108 denotes read data related to dirty bits.

The operation of the cache memory configured as described above will be described below. Clock 1
Bit lines B and X when xph2 of 01 is LOW, that is, ph2 is HIGH
B is precharged to HIGH. When ph2 is HIGH, decode the row address given to the cache and ph2
Is low, only one of the plurality of word lines is valid, and a dirty bit entry of one cache line is selected. Here, it is assumed that WL0 is selected. When the dirty bit information is read out, the dirty bit information held in the memory cell 105 is read out to the bit lines B and XB via the N-channel transistors 102 and 103, and the read out driver 106 detects and amplifies and reads out the dirty bit information. It is taken out as data 108 to the outside. According to the dirty bit information, if the dirty bit is 1 at the time of a cache miss, the data has been updated and the cache line must be written back to the external memory.

When writing information to a dirty bit, the write data 107 is amplified by a write driver 106 and applied to the bit lines B and XB.
The data is written to the memory cell 105 via the steps 2 and 103. Information is written to the dirty bit when the cache is set to 1 when a write hit occurs and when a cache miss occurs. There are a read miss and a write miss in the cache miss, but 0 and 1 are respectively written in the dirty bits, indicating that the data is clean in the read operation and that the data has been updated in the write operation.

FIG. 5 is an explanatory diagram of a pipeline operation of a store instruction in a cache memory. A case in which two store instructions for writing data to the cache memory successively cause a cache hit will be described. Here store A
The operation of a write hit is indicated as store B. ph1,
ph2 indicates a two-phase clock. TAG (R) reads the tag, D
(R) indicates reading of a dirty bit, Data (W) indicates writing of store data, and D (W) indicates writing of a dirty bit. In stage (1), tags and dirty bits related to store A are read. The tag is compared with the address given to the cache to obtain a write hit signal. In stage (2), the bit line is precharged before writing the store data to the data portion of the cache. In the stage (3), writing of store data and writing of a dirty bit are performed by a write enable signal generated from a write hit signal. In the stage (4), the bit line is precharged before reading the tag and dirty bit relating to the next store instruction, that is, store B. The subsequent operation of store B is the stage (1) of store A,
This is the same as the cases (2), (3) and (4).

[0006]

However, in the above configuration, the dirty bit cannot be read and the dirty bit cannot be written at the same time. Therefore, when a continuous store instruction is pipelined, one stop cycle is required. However, since the store operation can be performed only in two clock cycles, the processing efficiency is reduced.

The present invention has been made in view of the above problems, and provides a cache memory capable of performing a store operation in one clock cycle without a stop cycle when a continuous store instruction is operated in a pipeline.

[0008]

In order to solve the above problem, a cache memory according to the present invention comprises at least a tag address, a first dirty bit, a second dirty bit, and a selected entry in one entry. Means for setting the second dirty bit, and means for transferring the information of the second dirty bit to the first dirty bit in the next cycle when a write operation hits in a write cycle. It is characterized by having.

[0009]

According to the present invention, by performing the reading of the dirty bit and the writing of the dirty bit at different stages by the above-described configuration, when a continuous store instruction is pipeline-operated, a stop cycle is not inserted and one clock cycle is performed. Thus, the store operation can be performed, thereby improving the performance of the cache memory.

[0010]

FIG. 1 is a circuit diagram showing a dirty bit of a write-back type cache memory according to an embodiment of the present invention. Here, for the sake of simplicity, a direct map cache memory is used. The clock is a two-phase clock. In FIG. 1, reference numeral 10 denotes a precharge circuit using a P-channel transistor for precharging a bit line;
Reference numeral 27 denotes a clock obtained by inverting the second phase clock ph2 of the two-phase clock for controlling precharge, and is abbreviated as xph2.
Therefore, when ph2 is HIGH, xph2 becomes LOW, turning on the P-channel transistor. 11 is a word line WL0 corresponding to the 0th cache line of the cache memory.
And a storage circuit for storing information indicating the update of data connected to the bit line B and its inverted bit line XB, that is, dirty bits. Numeral 30 denotes a tag memory cell for storing a tag address. Here, for simplicity, there are shown storage circuits 11 and 20 and tag memory cells 30 and 31 corresponding to the first and last two lines. 14, 1
5 is a bit line B and its inverted bit line X, respectively.
An N-channel transistor, 16 connected to B, is a first transistor accessed through N-channel transistors 14,15.
Memory cell. 26 is a first phase clock ph1 of a two-phase clock, 12 is a second memory cell in the storage circuit 11,
29 denotes an inverter constituting the second memory cell 12, 1
Reference numeral 3 denotes an N-channel transistor controlled by a clock ph1 for transmitting a signal from the word line WL0 to the second memory cell. Reference numeral 25 denotes a two-phase clock ph2, and reference numeral 24 denotes a write hit signal indicating that a cache hit has occurred by a store instruction. An AND gate 21 receives the signals 24 and 25 as inputs, and generates an enable signal by a write hit signal. Reference numeral 18 denotes a NAND gate which receives the output of the second memory cell 12 and the output of the AND gate 21 as inputs. 17,
Reference numeral 28 denotes a NAND gate and an inverter which constitute the first memory cell, respectively. Reference numeral 19 denotes a driver for reading data from or writing data to the bit lines B and XB. 22 is write data related to a dirty bit, 2
Reference numeral 3 denotes read data relating to a dirty bit.

The operation of the cache memory configured as described above will be described below. Clock 2
Bits B and XB when xph2 of 7 is LOW, that is, ph2 is HIGH
Is precharged to HIGH. When ph2 is HIGH, decode the row address given to the cache and ph2
Is low, only one of the plurality of word lines is valid, and a dirty bit entry of one cache line is selected. Here, it is assumed that WL0 is selected. When reading information from the dirty bit, the information of the dirty bit held in the first memory cell 16 is read out to the bit lines B and XB via the N-channel transistors 14 and 15, and is detected and read by the read driver 19. It is amplified and taken out as read data 23. According to the dirty bit information, if the dirty bit is 1 at the time of a cache miss, since the data has been updated, the cache line needs to be written back to the external memory.

On the other hand, there are two types of methods for writing information to dirty bits. The first method is a case where, when a cache miss occurs in a store operation to a cache, when data transferred from an external memory is replaced with a cache line, information is written to a dirty bit at the same time as updating the store data. This operation is the same as that of the conventional method.
, And is applied to the bit lines B and XB, and is written to the first memory cell 16 via the N-channel transistors 14 and 15.

The second method is to set a dirty bit when a cache hit occurs for a store operation to the cache. When ph1 of the clock 26 is HIGH, a HIGH signal of the selected word line WL0 is sent through the N-channel transistor 13 and the second memory cell 12
To hold HIGH. Cache write hit signal 2
4 high and clock ph2 25 high AND gate 21
To generate HIGH. The HIGH held in the second memory cell 12 and the output HIGH of the AND gate 21 are input to the NAND gate 18 to obtain LOW. The output LOW of the NAND gate 18 is input to the NAND gate 17, and its output is set to HIGH.
To hold this information via the inverter 28. Therefore, the dirty bit information of the first memory cell 16 is set to 1 indicating data update.

FIG. 2 is an explanatory diagram of a pipeline operation of a store instruction in a cache memory. A case where two store instructions for writing data to the cache memory successively cause a cache hit will be described. Here is the store
The write hit operation is shown as A and store B. ph1,
ph2 indicates a two-phase clock. TAG (R) reads tags,
D (R) indicates reading of a dirty bit, Data (W) indicates writing of store data, and D (W) indicates writing of a dirty bit. In stage (1), tags and dirty bits related to store A are read. The tag is compared with the address given to the cache to obtain a write hit signal. In stage (2), the bit line is precharged and the dirty bit is written at the same time before the store data is written to the data portion of the cache. In the stage (3), the store data is written and the tag and dirty bit relating to the store B, which is the next access, are read by the write enable signal generated from the write hit signal. In stage (4), the bit line is precharged and the dirty bit is written at the same time before the store data is written to the data portion of the cache. The subsequent operation of the store B is the same as in the case of the stages (3) and (4) of the store A. As described above, successive write operations to the caches of the store A and the store B are processed every clock cycle.

FIG. 3 is a timing chart showing a process of setting a dirty bit when a write hit occurs in the cache memory. ph1, ph2 are two-phase clocks, A,
B is an access related to successive time-series store instructions, and corresponds to the store A and the store B. The operation of the word line WL0 is shown here for the word line. First, the operation for access A will be described. The address is input at the timing of ph2, and is decoded to select each entry of the cache by the lower index address of this address. Next, during the period when ph2 is LOW, the word line WL0 becomes valid and transmits HIGH. Here, the second memory cell 12 is connected via the N-channel transistor 13.
Latch HIGH. The upper address of the address A is compared with the tag A read from the cache, and a write hit signal 24 is obtained. The output of the AND gate 21 generates the write enable by the clock ph2. The output of the NAND gate 18 becomes LOW due to the output of the second memory cell 12 and the output of the AND gate 21, and the NAND gate 17
Will hold HIGH. Therefore, the output of the NAND gate 17 sets the first memory cell 16 holding the information of the dirty bit to the dirty state.

Next, it is assumed that a word line other than word line WL0 is selected in access B. Therefore, word line WL0 is L
It becomes OW, LOW is latched in the second memory cell 12, and the state of the first memory cell 16 does not change. on the other hand,
The dirty bit of the storage circuit 20 for holding the dirty bit corresponding to another word line decoded at the address B, for example, WLn, is set to 1. In such a continuous store operation, a dirty bit is set for each clock cycle via a word line corresponding to each cache line.

Although a direct-mapped cache memory is used here for simplicity, a write-assist signal can be provided independently for each way to realize a set-associative cache similarly.

As described above, according to this embodiment, the storage state of the dirty bit of the first memory cell 16 is changed by the output of the second memory cell 12 holding the information of the word line and the write hit signal 24. , Dirty bits are written for each cycle, and successive store instructions can be pipelined in one clock cycle. Also,
Since the tag address and the dirty bit are read at the same time, there is no delay in writing back the cache line with the dirty bit set to the external memory when the cache misses.

[0019]

As described above, according to the present invention, at least a tag address, a first dirty bit, a second dirty bit, and the second dirty bit for a selected entry are stored in one entry. Means for setting,
Means for transferring information of the second dirty bit to the first dirty bit in a next cycle when a write operation hits in a write cycle,
By setting the dirty bit information in each clock cycle, successive store instructions can be pipelined. Also, by reading the tag address and the dirty bit at the same time, if a cache miss occurs, there is no delay in writing back the cache line with the dirty bit set to the external memory. Performance can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a cache memory according to an embodiment of the present invention.

FIG. 2 is a pipeline operation diagram for explaining the operation in the embodiment.

FIG. 3 is a timing chart for explaining the operation in the embodiment.

FIG. 4 is a circuit diagram of a dirty bit of a conventional cache memory.

FIG. 5 is a pipeline operation diagram for explaining the operation of a conventional cache memory.

[Explanation of symbols]

 Reference Signs List 10 precharge circuit 11, 20 storage circuit 16 first memory cell 12 second memory cell 13, 14, 15 N-channel transistor 17, 18 NAND gate 19 read / write driver 21 AND gate 22 write data 23 read data 24 write Hit signal 25, 26, 27 Clock 28, 29 Inverter 30, 31 Tag memory cell

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-75850 (JP, A) JP-A-3-62243 (JP, A) JP-A-5-109286 (JP, A) JP-A-2- 259866 (JP, A) JP-A-1-243297 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08 G11C 11/401, 15/04

Claims (5)

(57) [Claims] At least a tag address, a first dirty bit, a second dirty bit, and a first phase clock for a selected entry are assigned to one entry.
The first dirty bit at the expected timing
To the second dirty bit.
The setting means to set and the time during which the hit signal indicating that the write operation hit in the write cycle is valid
A second phase clock which is a reverse phase clock of the first phase clock.
Transfer means for transferring the information of the second dirty bit to the first dirty bit at a timing synchronized with the first dirty bit.
Cache memory; and a stage. 2. The cache memory according to claim 1, wherein said first dirty bit receives an output of said first inverter and an output of said transfer means as an input of a first NAND gate, and outputs an output of said first NAND gate. A cache memory comprising a first memory cell as an input of the first inverter. 3. The cache memory according to claim 1, wherein said second dirty bit comprises a second memory cell connected in a closed loop using two second inverters, and outputs the output of said setting means to said second dirty bit. A cache memory as an input of a second memory cell. 4. The cache memory according to claim 1, wherein said transfer means is stored in said second memory cell.
Hit signal indicating that the write operation has hit
Signal is in a valid period and the reverse phase clock of the first phase clock
Occurs at a timing synchronized with the second phase clock
Cache memory, comprising the second NAND gate which receives that signal. 5. The cache memory according to claim 1, wherein said setting means connects said first phase clock to a gate of an N-channel transistor, a word line to a source, and an input of said second memory cell to a drain. Characteristic cache memory.