JP3307145B2 - Power chip carrier and power semiconductor device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS-controlled power semiconductor, in particular, a transistor (IGBT or the like) or a composite semiconductor (IGCT) of a transistor and a thyristor.
Etc.) and a unit power chip carrier on which a diode is mounted, and a large-capacity semiconductor device in which these are sandwiched and pressed between the same metal substrates to enable parallel operation.

[0002]

2. Description of the Related Art There is a strong demand for the development of high-speed, low-loss switching elements in order to cope with high performance and low noise of power converters such as inverter devices. As this semiconductor element, IGBT (Insulated Gate Bipolar
Transistor) and IGCT (Insulated Gate Control)
led Thyristor). The IGBT is described in, for example, Electronics Technology, August 1991, pp. 139-143. As shown in 17-71, voltage drive is used, and high-speed operation is possible. Furthermore, because of voltage control, the conventional current control element GTO
Since the on-state voltage can be reduced as compared with the thyristor, the element can have low loss. Further, the IGCT can further reduce the ON voltage and increase the current as compared with the IGBT. However, MOS-controlled semiconductors such as IGBTs and IGCTs have difficulty in increasing the area of the chip from the viewpoint of process yield. Therefore, parallel switching of the chips is indispensable when performing high-power switching. It is essential.

FIGS. 1A and 1B show a conventional single-sided cooling type IG.
It is the figure which showed the plane and sectional structure of the BT module.
In the figure, 101 is an IGBT chip, 102 is a collector (anode) side support electrode plate, 103 is a bonding wire, 104 is an AlN substrate, 105 is a solder layer, 106 is an emitter electrode terminal, 107 is an Al electrode, and 108 is a gate electrode terminal. , 109 are collector (anode) electrode terminals and 1
Reference numeral 10 denotes a diode chip. The heat generated inside the IGBT chip 101 is dissipated to the outside through the collector-side electrode terminal 109, which is a copper circuit board, the AlN substrate 104, and the collector-side electrode support plate 102, which is a metal substrate such as Mo or copper. As an example of such a single-sided cooling type IGBT module, for example, Mitsubishi Electric Technical Report vol 67, No. 9, 1993,
PP. 90-93.

[0004] On the other hand, materials of the National Institute of Electrical Engineers of Japan in 1994 (N
FIG. 2 shows an IGBT having a pressure contact type package structure disclosed in O.507). This structure is IGBT chip 2
The collector or anode side of No. 01 is bonded to the lower collector-side electrode plate 203 by a bonding layer 202, and the pressing electrode 205 provided on the emitter is pressed and pressed by the emitter electrode plate 204 having a convex portion. . The gate electrode 206 is connected to a gate terminal 208 by a wire 207. Because it can be cooled from both sides, it has low thermal resistance and high reliability.

[0005]

In the conventional single-sided cooling type structure, when the IGBT is mounted on the substrate at a high density due to low cooling efficiency, the chip temperature rises, and the solder joint and the wire bonding part are likely to deteriorate. . In addition, the gate electrode (1
(Corresponding to the chip-side electrode of No. 08) Since there is a brittle and thin gate oxide film immediately below, chip damage easily occurs at the time of wire bonding, which causes a problem in the reliability of the joint. Further, in the case of the above structure, it is necessary to design a module structure each time to cope with the series.

In the pressure contact type package structure, since the emitter side has a pressure contact structure, the chip temperature rises when current is applied in a pressurized state. As a result, the pressurized electrode is longer than the IGBT chip, so that the load is apt to be biased, and the contact resistance is likely to fluctuate. In addition, problems such as handling of dust and misalignment are likely to occur. Further, since the pressure electrode is provided on the chip, the ratio of the MOS control unit closed to the chip area is reduced, and the current capacity per area is reduced.

An object of the present invention is to provide a power chip carrier which is excellent in reliability, handling, manufacturability and cooling efficiency.

Another object of the present invention is to provide a power semiconductor device which is easy to increase in capacity and series based on the power chip carrier.

[0009]

According to the chip carrier of the present invention, the cathode electrode and the anode electrode of the MOS control type power semiconductor element are metallurgically joined to the cathode internal electrode and the anode internal electrode. .

According to an embodiment, the cathode electrode and the anode electrode are made of Al as the first layer, are joined and the uppermost layer is made of Ag or Au, and the intermediate layer has an adhesive layer made of Cr, Ti or Ni. . The cathode-side internal electrode and the anode-side internal electrode have Ni as a first layer, and the uppermost layer to be joined has an adhesive layer made of Ag or Au. Furthermore, the junction between the cathode electrode and the cathode-side internal electrode and the junction between the anode electrode and the anode-side internal electrode are metallurgically bonded by mutual diffusion of Ag and Ag or Ag and Au. preferable. This Ag and Ag,
Alternatively, metallurgical bonding by interdiffusion between Ag and Au is 2
It is desirable that the heating be performed at 50 ° C. or lower.

According to the power semiconductor device of the present invention, a plurality of the above-mentioned power chip carriers are used, and a plurality of insulating substrates metallurgically bonded to the respective cathode-side internal electrodes and anode-side internal electrodes of these power chip carriers. And an insulating substrate bonded to the cathode side internal electrode, and
A first pressurizing connection to a plurality of power chip carriers connected in parallel to an insulating substrate bonded to the anode-side internal electrode.
And a second external electrode.

A semiconductor device characterized in that it is desirable to have a sea-surface metal layer or a superelastic alloy layer between an insulating substrate joined to a cathode side internal electrode and a first external electrode.

[0013]

In the structure of the present invention, since the electrodes on both the anode and cathode main surfaces of the semiconductor element substrate and the internal electrodes are metallurgically bonded, the structure of the present invention is more advantageous on both sides than in the pressure welding structure in which an air layer is interposed at the interface. Can be sufficiently cooled and has low thermal resistance. Furthermore, the unbalanced load phenomenon peculiar to the pressure contact structure hardly occurs, and the handling property such as dust and displacement does not deteriorate. For example, in the case of an IGBT module to which the present invention is applied, the pressure dependency of VCE (saturation voltage) is extremely small. That is, the pressing force can be reduced. From the above, the structure of the present invention is advantageous for miniaturization and high reliability. Furthermore, since it is sealed with a resin, it can be used in a state where an insulating plate is not connected, that is, as a unit module depending on the use.

The metallurgical bonding of the present invention is preferably performed at a temperature of 250 ° C. or less, but if the connection is made at a temperature of about 120 to 150 ° C., the internal electrode is formed of W, Mo or Cu—Al.
Not only materials having a low coefficient of thermal expansion such as N, Cu-SiC, Cu-W, and Cu-Mo, but also materials having a relatively large coefficient of thermal expansion such as Cu and Al can be used. The reason for this is that, since the temperature is low, even if the mismatch of the thermal expansion coefficient is large, the thermal stress generated at the joint can be reduced.

In the power semiconductor device according to the present invention, the power chip carrier described above can be achieved in a considerably smaller size than the conventional module by connecting the power chip carriers in units of modules in parallel.

That is, since it is difficult to make a chip 3 cm square or more from the viewpoint of chip yield in a MOS control type semiconductor, the chip capacity is at most about 100 amperes, and this is increased to several thousand amperes. Therefore, it is necessary to operate many chips simultaneously. Therefore,
The conventional one-side cooling type module is considerably large in size in consideration of cooling efficiency. In addition, it is necessary to design the position of the chip, the position of the terminal, and the like according to the capacity, evaluate the reliability of the manufactured module, and the like.

According to the power semiconductor device of the present invention, the above-mentioned small power chip carrier having high cooling efficiency and high reliability is used, and each power chip carrier is provided with the first and second external power chips. They are connected in parallel by electrodes. Accordingly, a large-capacity power semiconductor device which can be easily formed into a series and is small and highly reliable can be realized.

Further, since a sea surface metal layer or a superelastic alloy layer is provided between the insulating substrate bonded to the cathode side internal electrode and the first external electrode, each power chip carrier is uniformly pressed. Therefore, the reliability is further increased.

[0019]

The present invention will be described below in more detail with reference to examples.

FIGS. 3A and 3B show an example of a sectional structure of the power chip carrier of the present invention. FIG. 4 is a sectional view of an IGBT used for a power chip carrier. In FIG. 3, reference numeral 301 denotes a Si base, 302 denotes a gate, 30
3 is a cathode electrode, 304 is a collector (anode) side electrode, 305 is a cathode side adhesive layer, 306 is a collector (anode) side adhesive layer, 307 is a cathode side internal electrode, 30
8 is a collector (anode) side internal electrode, 309 is a gate electrode, 310 is a bonding wire, 311 is a gate terminal, 312 is an insulating support substrate, 313 is a resin, 314 is an adhesive layer with a cathode side insulating substrate, and 315 is a collector ( An adhesive layer with the (anode) side insulating plate, and 316 and 317 indicate insulating substrates. The feature of FIG. 3A is that the cathode electrode 303 and the collector (anode) electrode 304 of the Si base 301 and the internal electrodes 307 and 308 are firmly metallurgically adhered.
A gate electrode 309 arranged around the GBT is connected to a gate terminal 311 by a wire and is sealed with a resin 313. The gate electrode 309 is connected to the gate electrode 302 located between the emitter electrodes 405 in FIG. Incidentally, reference numeral 406 in FIG. 4 denotes an insulating film for insulating the cathode electrode 303 and the gate 302.

In this structure, the capacity of the IGBT depends on the performance and size of the Si substrate,
00V, about 50 to 300 A, and within this capacity, it can be used in this state. Further, since the cathode and collector electrodes of the IGBT are bonded to the internal electrodes 307 and 308, heat can be released from both sides (both sides are cooled), which is extremely advantageous in terms of thermal resistance and reliability as compared with the prior art. . Therefore, the wire bonding portion is not easily deteriorated.

The cathode electrode 303 and the collector electrode 304
The electrode structure of Al / Cr / Ni / Ag, Al / N
i / Ti / Ni / Au or Al / Cr / Ag, Al
/ Ni / Au, Al / Cr / Ag, etc. as the first layer,
The uppermost layer is made of Ag or Au.
It suffices if it is composed of r and Ti layers and a Ni layer as a barrier. On the other hand, the adhesive layer of the internal electrodes 307 and 308 is Ni /
Ag. The metal bonding at a temperature of 250 ° C. or less is completed by the interdiffusion of Ag and Ag or Au.

On the other hand, in the single-sided cooling type shown in FIG. 1, in the case of the solder connection indicated by 105, the back surface of the IGBT chip is subjected to the Al / Cr / Ni / Ag treatment. Is plated with Ni and Pb-S
n or Sn-Sb solder. In this case, Ag diffuses into the solder, and a compound of Ni and Sn is generated at the interface on both sides, whereby the bonding is completed. The compound of Ni and Sn does not grow sufficiently unless the temperature reaches 250 ° C. or higher.
The solder connection between the AlN substrate 102 and the substrate 104 is also N
A compound of i and Sn is generated, and the joining is completed. The formation of the compound of Ni and Sn is considerably affected not only by the bonding temperature but also by the oxide film (NiO, Ni ₂ O ₃ ) on the surface of the Ni plating film, dirt, and gas in the solder, and large voids are generated at the interface and in the solder. Etc., etc., and variations in bonding are large.

In this embodiment, the internal electrodes and the Ag on the insulating substrate are used.
Alternatively, low-temperature diffusion bonding with Au and Ag films on the cathode and anode electrodes is possible only by reducing the carbon concentration in the Au film to 30 at% or less. Carbon inhibits diffusion bonding. When Ag fine particles are used to reduce the carbon concentration to 30 at% or less, an internal electrode or an insulating substrate coated with Ag particles is used to remove carbon from the organic solvent.
What is necessary is just to heat in air | atmosphere to the temperature of 50 degreeC. When an Au or Ag film is formed by vapor deposition or sputtering, heat treatment is not required to eliminate carbon.

In the structure shown in FIG. 3B, in order to further increase the capacity, the insulating substrates 316 and 317 are connected to the internal electrodes 307 in order to connect the chip carriers shown in FIG. , 308 and a connection layer 314 made of Ag,
315 also provides low temperature bonding. Note that the gate electrode 309 is arranged around the IGBT substrate 301, and has a structure in which the oxide film of the gate 302 is hardly damaged during wire bonding. The gate electrode and the external terminal may be connected by a thin plate other than the wire. In this case, it is preferable to bond the anode and the cathode in the same manner as the low-temperature bonding.

FIG. 3C shows that an Ag film is formed on the Mo internal electrode via a Ni plating film by powder or sputtering, and is overlapped with the Mo internal electrode provided with the Ag film by the same method.
The relationship between the bonding strength ratio of the sample bonded by heating at 00 ° C. in the air and the carbon concentration in the Ag film is shown. Ag is 30a
It can be seen that when the content exceeds t%, the joining strength is significantly reduced.

FIG. 5 shows the structure of an IGBT in which a high melting point metal such as TIW or TiN or a nitride layer 506 is provided between the gate 502 and the cathode electrode 503 in FIG. In the figure, reference numeral 505 denotes an emitter electrode, and 507 denotes a gate oxide. Using the IGBT substrate having the structure shown in FIG.
The power chip carrier shown in (a) and (b) can be manufactured in the same manner. The presence of the high-melting metal compound layer 506 having high strength above the gate 502 causes the gate oxide 507 to be subjected to external stress. , And reliability is improved.

FIG. 6 is a sectional view of a unit module using the IGBT chips shown in FIGS. 4 and 5, ie, a power chip carrier. The feature of this structure is that the emitter electrode 614 and the cathode-side internal electrode 6 as shown in FIG.
07 is solid-phase bonded to the convex portion of the gate electrode 605 by the adhesive layer 605, and the internal electrode is not bonded to the cathode electrode 603 on the gate 602. Since the internal electrode 607 is directly connected to the emitter electrode 614 serving as a heat sink,
The cooling efficiency of heat is improved as compared with the case where the electrode is connected on the cathode electrode 603 on the gate 602. Others are the same as the structure shown in FIG.

FIG. 6B shows an insulating substrate 617 for connecting a large number of FIG. 6A in parallel with a view to further increasing the capacity.
618 and the internal electrodes 607 and 608 are connected to the connection layers 615 and 6
Reference numeral 16 denotes a structure formed by low-temperature metal bonding.

In the above embodiments, the adhesive layer is formed of an Ag layer, and its density is preferably in the range of 60 to 100%, as described later, from the viewpoint of electrical conductivity and stress relaxation.
This density varies depending on the size of the Ag particles used and the bonding temperature. Further, as the internal electrodes 607 and 608,
When a material having a low coefficient of thermal expansion such as Mo or W is used, the material is heated to a temperature of 200 ° C. or more, and the density of the bonding layer is reduced to 1
It may be close to 00%. On the other hand, the internal electrodes 607 and 60
8 as Cu, Al and W, Mo, AlN, S
When using a composite material with a material having a low coefficient of thermal expansion such as iC, it is desirable to join at a low temperature of 200 ° C. or less from the viewpoint of securing reliability.

Although the embodiments of the power chip carrier using the IGBT substrate have been described above, the present invention can be applied to MOS controlled thyristors in addition to MOS controlled transistors.

FIG. 7 shows a sectional structure of a MOS-controlled thyristor (IGCT) used for the power chip carrier of the present invention.
In the figure, 701 is an IGCT, 702 is a gate oxide film, 703 is a poly-Si gate, 704 is an insulating film on a thyristor, 705 is a cathode, 706 is an anode side Al /
A Cr / Ni / Ag film and 707 are emitter electrodes. The insulating film 704 on the thyristor is made of, for example, PSG (Ph
ospo-Silicate-Glass) or SiO ₂ is used.

In the IGBT shown in FIG.
A smaller ratio of the length of the cathode electrode 403 on the gate to the length of the gate electrode 05 is more effective in increasing the breakdown voltage and reducing the ON voltage, whereas the IGCT has a smaller length of the emitter electrode 707 in FIG. Are effective for increasing the breakdown voltage and reducing the ON voltage. That is, since the bonding area with the cathode-side internal electrode can be increased, it can be said that the element is suitable for the power chip carrier in terms of the reliability of the bonding portion and the cooling efficiency.

FIG. 8 is a sectional view of a power chip carrier manufactured by using the IGCT shown in FIG. FIG. 8 (a)
Is a case where the capacitor is used in a capacity range up to several hundred A. In the figure, 801 is an IGCT base, 802 is a gate insulating film, 803 is a gate, 804 is an insulating film, 805 is a cathode electrode, 806 is an emitter electrode, 806 is a collector side electrode, 807 is a cathode side adhesive layer, and 809 is a collector side. An adhesive layer, 810 is a cathode side internal electrode, 811 is a collector side internal electrode, 812 is a gate electrode, 813 is a bonding wire, 814 is a resin, and 815 is an insulating support substrate. The cathode electrode 805 and the collector electrode 807 are made of Al
/ Cr / Ni / Ag, Al / Cr / Ag and Al / Cr
/ Ag. The bonding layers 808 and 809 on the cathode-side internal electrode 810 and the collector-side internal electrode 811 are made of Ag. By the diffusion of Ag, the cathode electrode film 805 and the cathode-side internal electrode 810 and the collector-side electrode 807 and the collector-side internal electrode 811 are joined at low temperature, respectively. IGCT base 801 itself is ON
Since the area of the cathode electrode 805 is large in addition to the low voltage, a power chip carrier having particularly excellent cooling efficiency and reliability can be obtained. The gate electrode 812 is connected to the gate terminal 816 by wire bonding 813. FIG. 8B further shows that the internal electrodes 810 and 811 and the insulating plates 819 and 820 are joined.

In FIG. 9, two chip carriers 901 are arranged, the cathode internal electrodes 902 are connected 903, the collector electrodes 904 are connected 905, the gate electrodes 906 are connected 907, and the cooling fins 9 are arranged from above and below the insulating plate 908.
10 shows a structure for increasing the capacity by sandwiching between external electrodes 909, tightening with screws 911, applying pressure, and operating in parallel. In the figure, between the cathode-side insulator plate 908 and the external electrode 909 with cooling fins, in order to uniformly press the two chip carriers,
A spongy metal or superelastic alloy plate 912 is provided. The present embodiment is a case of two power chip carriers. However, by increasing the number of carriers, a semiconductor device capable of coping with high power is made possible, so that a series can be easily formed according to the application.

Next, a method for manufacturing a power chip carrier will be described. Plating on the internal electrodes shown in FIGS.
A Ni layer is provided by a method such as sputtering or vapor deposition, and, for example, Ag ultrafine particles (100
(Less than 0 °). Next, in the atmosphere
Heat to a temperature of at least 00 degrees to remove C. In the next step, similarly, heating is performed in a vacuum to remove the oxide film on the Ag surface. Next, the Ag layer on the electrodes of the IGBT and IGCT and the Ag layer on the surface of the internal electrode are overlapped, and heated to a temperature range of 150 to 250 ° C. for bonding. Similarly, when joining to an insulating plate,
Using the g layer, wire bonding and resin sealing are completed. In the case where a sputtered Ag or Au film is used in addition to the above Ag fine particles, N on the internal electrode such as Mo is used.
An Ag film is formed on the i-film at a temperature in the range of room temperature to 100 ° C. by a sputtering method to a thickness of 2 to 20 μm. Subsequently, the anode and cathode electrodes of the MOS power semiconductor are overlapped with each other by heating at a temperature of 100 to 250 ° C. in the atmosphere under N ₂ .

[0037]

According to the present invention, it is possible to provide a power chip carrier having high reliability, low thermal resistance, large capacity, and a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a diagram showing the structure of a conventional single-sided cooling type semiconductor module.

FIG. 2 is a diagram showing a module structure of a conventional pressure contact type double-sided cooling system.

FIG. 3 is a diagram showing a power chip carrier of the present invention.

FIG. 4 is an IG used for the power chip carrier of the present invention.
It is a figure showing the section of BT.

FIG. 5 is an IG used for the power chip carrier of the present invention.
It is sectional drawing of BT.

FIG. 6 is a diagram showing a power chip carrier of the present invention.

FIG. 7 is an IG used for the power chip carrier of the present invention.
It is sectional drawing of CT.

FIG. 8 is a sectional view showing a power chip carrier of the present invention.

FIG. 9 is a diagram showing a cross-sectional structure of a large dose semiconductor of the present invention.

[Explanation of symbols]

301: Si base, 302: Gate, 303: Cathode electrode, 304: Collector (anode) side electrode, 305:
Cathode-side adhesive layer, 306: collector (anode) -side adhesive layer, 307: cathode-side internal electrode, 308: collector (anode) -side internal electrode, 309: gate electrode, 310
... bonding wire, 311 ... gate terminal, 312 ...
Insulating support substrate, 313: resin, 314: adhesive layer with cathode side insulating substrate, 315 ... adhesive layer with collector (anode) side insulating plate, 316, 317: insulating substrate.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Mitsuo Sato 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Ichiji Yamada 7-1-1 Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Hideo Kobayashi 7-1-1, Omikamachi, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Hiroshi Nagase Omikamachi, Hitachi City, Ibaraki Prefecture Hitachi 1-1, Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Masaki Suwa 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Research Laboratory (56) References JP-A-6-232303 ( JP, A) JP-A-54-17669 (JP, A) JP-A-52-122472 (JP, A) JP-A-6-310725 (JP, A) JP-A-1-228139 (JP, A) JP-A-1-228138 (JP, A) JP-A-5-206449 (JP, A) JP-A-8-167625 (JP, A) JP-A-53-124974 ( JP, A) JP-A-2-206125 (JP, A) JP-A-60-176244 (JP, A) JP-A-58-17626 (JP, A) JP-A-3-25258 (JP, U) Hei 1-501027 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/52

Claims (6)

(57) [Claims] An MO formed on one main surface of a semiconductor substrate.
An S-control type power semiconductor element, a cathode electrode of the semiconductor element formed on one main surface of the semiconductor substrate, and a cathode electrode formed on one main surface of the semiconductor substrate via an insulating layer. A gate electrode of the semiconductor element, an anode electrode of the semiconductor element formed on the other main surface of the semiconductor substrate, a cathode-side internal electrode metallurgically bonded to the cathode electrode, and the anode electrode and the metal an anode-side internal electrode joined to histological, and possess, the cathode
The internal electrode on the anode side and the internal electrode on the anode side are made of Ni in the first layer.
And the uppermost layer to be bonded is made of Ag or Au.
Having a deposition layer, the cathode electrode and the cathode-side internal electrode,
And the anode electrode and the anode-side internal electrode
Is the interdiffusion between Ag and Ag or between Ag and Au
Power characterized by being metallurgically joined by
Chip carrier. 2. The method according to claim 1, wherein the carbon concentration of the Ag is
Power chip key characterized by being 30 at% or less.
Jalia. 3. An MO formed on one main surface of a semiconductor substrate.
An S-control type power semiconductor element, a cathode electrode of the semiconductor element formed on one main surface of the semiconductor substrate, and a cathode electrode formed on one main surface of the semiconductor substrate via an insulating layer. A gate electrode of the semiconductor element, an anode electrode of the semiconductor element formed on the other main surface of the semiconductor substrate, and the cathode electrode and Ag and Ag, or
A cathode-side internal electrode that is metallurgically bonded by mutual diffusion of Ag and Au, the anode electrode, Ag and Ag,
Alternatively, a plurality of power chip carriers each having an anode-side internal electrode which is metallurgically bonded by interdiffusion of Ag and Au, and a metallurgy is applied to each of the cathode-side internal electrode and the anode-side internal electrode of the power chip carrier. A plurality of insulating substrates joined together, an insulating substrate joined to the cathode-side internal electrode, and an insulating substrate joined to the anode-side internal electrode. A power semiconductor device comprising: first and second external electrodes to be fixed. 4. The method according to claim 3, wherein the carbon concentration of the Ag is
Power semiconductor device characterized by being 30 at% or less.
Place. 5. The power semiconductor according to claim 3 , wherein a sea surface metal layer or a superelastic alloy layer is provided between the insulating substrate joined to the cathode side internal electrode and the first external electrode. apparatus. 6. The claim 3 5, between the cathode-side internal electrode and the insulating substrate, and the bonding layer mainly composed of Ag or Au is between the anode-side internal electrode and the insulating substrate A power semiconductor device comprising: