JP3307808B2 - DSV calculator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EFM (Eight to Fourteen Modulatio) used for a mini disc device or the like.
n) DSV (Digital Suspension) serving as an index for selecting merging bits connecting each frame signal in modulation
More specifically, the present invention relates to a DSV calculator having a function of improving the accuracy of DSV.

[0002]

2. Description of the Related Art EFM modulation is a modulation method used when audio data is recorded on an optical disk in a mini disk device or the like.

FIG. 7A shows a part of a conversion table in EFM modulation and a waveform shown by data subjected to EFM modulation. As shown in FIG. 7A, the EFM modulation is
It converts bit digital data into a 14-bit pattern. 2 ⁸ = 25 for the original 8-bit data
There are six types of patterns, and conversion tables corresponding to each pattern are prepared.

In EFM-modulated data, data “0” does not indicate a Low level but means that the polarity (High or Low) of the immediately preceding data is maintained, and data “1” indicates High. It means to invert the polarity instead of representing the level. Therefore, the polarity of the last bit of the immediately preceding data is High.
The waveform changes depending on h or Low.

The reason why EFM modulation is required for recording a mini-disc or the like is that the frequency band in the optical disc pickup mechanism is limited. Since the frequency band is limited, if the length of the pit recorded on the optical disk is too short, it becomes difficult to read data. Therefore, in order to prevent the length of the pit from becoming extremely short, the data is converted into data in which “two or more“ 0 ”s are between“ 1 ”and“ 1 ”” by EFM modulation.
Since 14-bit digital data has 2 to the 14th power, that is, 16384 kinds of patterns, one of the patterns suitable for the condition of “two or more“ 0 ”s between“ 1 ”and“ 1 ”” is selected. 256 are selected to form a conversion table for EFM modulation.

In actual EFM modulation, input serial data is divided into 8-bit data,
Each frame data is converted into 14-bit frame data according to the conversion table of the FM modulation, and a 24-bit frame synchronization signal is inserted for every fixed number of frame data. Further, merging bits are inserted between the frame data and between the frame data and the frame synchronization signal.

[0007] The merging bits will be described below.

Even if the data is converted into data in which “two or more“ 0 ”s are between“ 1 ”and“ 1 ”” by EFM modulation,
The connection between data may not satisfy the condition that “two or more“ 0 ”s exist between“ 1 ”and“ 1 ””.

For example, the last bit of certain data is "1"
And the bit of the next data is 1 at the beginning,
When two data are connected, "1" and "1" are continuous. Therefore, the condition of “two or more“ 0 ”s between“ 1 ”and“ 1 ”” is not satisfied. In order to prevent such a problem, 3-bit data is used in EFM modulation to connect data. This is the merging bit.

Since the merging bit data is 3 bits, there are 2 to the third power, ie, 8 types of bit patterns. However, due to the condition in EFM modulation that “two or more“ 0 ”s are between“ 1 ”and“ 1 ””, “11
The four patterns “1”, “110”, “101”, and “011” are inappropriate, and “000”, “100”, “010”, “00
Only four patterns "1" can be used. The best one of these four patterns is selected each time as a merging bit.

The selection of the merging bit is performed as follows. First, a merging bit pattern that satisfies the condition “two or more“ 0 ”s between“ 1 ”and“ 1 ”” by the last bit pattern of the previous data and the first bit pattern of the next data Select

For example, if the last three bits of the previous data are "
001 ”and the first three bits of the next data are“ 10 ”.
If it is "0", only "000" can be used as a merging bit. If the last three bits of the previous data are “100” and the first three bits of the next data are “001”, “000” “100”
All four patterns “010” and “001” can be used as merging bits.

If a plurality of patterns can be used as merging bits, an optimum pattern is selected based on the value of DSV.

Here, DSV (Digital Sum Variation)
) Will be described below.

The DSV represents a deviation of the balance of the DC component of the modulated data, and can be calculated very simply in practice. In the EFM-modulated data waveform, if the per bit is at the High level, +
1, if it is at the low level, it is set to -1, and these values may be added.

FIG. 7B is a diagram for explaining a method of selecting a merging bit based on the value of DSV. In FIG. 7B, since the last bit pattern of the previous data is “010” and the first bit pattern of the next data is “001”, “000”, “010”, and “000” can be used as merging bits. 001 ”
There are two patterns. Therefore, the DSV value when each pattern is selected is calculated. here,
It is assumed that the DSV in the last bit of the immediately preceding data (hereinafter, referred to as cumulative DSV) is “−3”. Also, it is assumed that the polarity of the last bit of the immediately preceding data (hereinafter referred to as the accumulated polarity) is High.

When "000" is selected, the DSV of the merging bit is "3", and the polarity of the last bit of the merging bit is high. Therefore, the DSV of the next data becomes “+2”, and the DSV of the last bit of the next data (hereinafter, referred to as a new accumulated DSV)
Becomes “+2”. When “010” is selected,
The DSV of the merging bit is “−1”, and the polarity of the last bit of the merging bit is Low. Therefore, the DSV of the next data is “−2”, and the new accumulated DSV is “−6”. When “001” is selected, the DSV of the merging bit is “+1”, and the polarity of the last bit of the merging bit is Low. Therefore, the DSV of the next data is "-2", and the new accumulated DSV is "-4".

It is considered that a value of DSV closer to 0 is desirable in terms of sound quality and the like. Therefore, here, “000” is selected as the merging bit so that the new cumulative DSV is closest to zero.

There are two methods for calculating the cumulative DSV: a serial method and a parallel method.

The serial method is a method of calculating DSV one bit at a time from the beginning of data for EFM-modulated data.

On the other hand, the parallel method is a method in which the DSV of the frame synchronization signal, the frame data and the merging bit is calculated in advance, and the DSV is calculated by adding the value of each DSV to the value of the accumulated DSV.

As examples of the conventional DSV calculator using the parallel method, a polarity estimator for the DSV of the frame synchronization signal and the frame data signal, a cumulative DSV, a DSV of the merging bit, and a DSV of the frame synchronization signal and the frame data signal are provided. By using the addition means for adding the three types of data, it is possible to reduce the circuit scale and determine whether or not the addition result by the addition means has an overflow or underflow. Some include an overflow / underflow processor that performs exception processing.

[0023]

However, the conventional DSV calculator has the following problems.

The upper limit value and the lower limit value of the accumulated DSV data are determined by the number of bits representing the accumulated DSV data. For example, assuming that the accumulated DSV data is represented by 8 bits, only decimal numbers from “−128” to “127” can be expressed. However, in practice, the accumulated DSV data may exceed the upper limit value or fall below the lower limit value, so that a so-called overflow or underflow occurs.

In the conventional DSV calculator, when the accumulated DSV data overflows, the upper limit value is output as new accumulated DSV data, and when the accumulated DSV data underflows, it is output as new accumulated DSV data. The lower limit was output. At this time, an error occurs between the true accumulated DSV data and the new accumulated DSV data. Moreover, this error is not corrected forever. Therefore, there is a problem that an error may remain when calculating the cumulative DSV.

FIG. 8 is a graph showing changes in the accumulated DSV data in the conventional DSV calculator. In the figure,
(A) is a graph when no overflow occurs,
(B) is a graph when an overflow has occurred. In addition, ○ is the accumulated DSV data obtained by the adding means of the DSV calculation device, and □ is the accumulated DSV data corrected by the occurrence of the overflow. Here, since the accumulated DSV data is represented by 8 bits, the upper limit value is “127” and the accumulated DSV data is
When the data exceeds “127”, an overflow occurs.

As shown in FIG. 8 (a), when no overflow occurs, the accumulated DS obtained by the adding means is obtained.
Since the V data is not modified, the true cumulative DSV
No error occurs with the data. However, as shown in FIG. 8B, when an overflow occurs, the cumulative DSV data is corrected to the upper limit value "127", and thereafter, the cumulative DSV data obtained by the adding means and the true cumulative D
An error will occur with the SV data. This error will not be corrected thereafter and will increase with each overflow.

In view of the above problems, it is an object of the present invention to provide a DSV calculator that does not decrease the accuracy even when the accumulated DSV data overflows or underflows.

[0029]

In order to achieve the above-mentioned object, the present invention relates to a method of calculating the cumulative DSV data, which is performed when an overflow or an underflow occurs in the calculation of the cumulative DSV data. Is stored, and this difference data is later accumulated DSV
An overflow / underflow processor having a function of adding to data is provided.

Specifically, a solution taken by the first aspect of the present invention is a DSV (Digital-to-Fourteen Modulation) which serves as an index for selecting merging bits for connecting modulated frame signals in EFM (Eight to Fourteen Modulation) modulation.
Sum Variation) is intended for a DSV calculation apparatus that calculates each time one frame signal is input, the cumulative DSV data representing the DSV value up to the frame signal immediately before the one frame signal, the one frame Adding frame signal DSV data representing the value of the DSV of the signal and merging bit DSV data representing the value of the DSV of the merging bit connecting the one frame signal and the frame signal immediately before the one frame signal; Adding means for outputting the addition result; and determining whether or not the addition result output from the addition means has caused an overflow or underflow. When the overflow or underflow has occurred, exception processing is performed on the addition result. And an overflow / underflow processor that outputs as new accumulated DSV data The overflow / underflow processor holds the difference between the addition result and the upper limit value of the accumulated DSV data when the addition result output from the addition means has caused an overflow, and The difference held when the output result does not cause an overflow is added to the addition result. On the other hand, when the addition result output from the adding means underflows, the addition result and the accumulation are added. A structure having a function of holding a difference from the lower limit value of the DSV data and adding the held difference to the addition result when the addition result output from the adding means does not cause an underflow. It is.

According to the first aspect of the present invention, when the addition result output from the addition means overflows, the difference between the addition result and the upper limit value of the accumulated DSV data is held by the overflow / underflow processor. In addition, the held difference is added to the addition result when the addition result output from the adding means does not overflow. Therefore, even if an overflow occurs, an error with respect to the true accumulated DSV data will be corrected later. When the addition result output from the addition means underflows, the difference between the addition result and the lower limit value of the accumulated DSV data is held, and the held difference is added to the addition result output from the addition means. When the result does not cause underflow, it is added to the addition result. Therefore, even if an underflow occurs, an error with respect to the true accumulated DSV data will be corrected later.

According to a second aspect of the present invention, in the configuration of the first aspect, the adding means adds a merging bit DSV data and the frame signal DSV data, and outputs a result of the addition, This configuration adds a configuration having a second adder that adds the addition result of the first adder and the accumulated DSV data and outputs the addition result.

According to a third aspect of the present invention, in the configuration of the second aspect, the overflow / underflow processor determines whether or not the addition result of the second adder has caused an overflow or an underflow. When an overflow has occurred, the upper limit value of the accumulated DSV data is output. When an underflow has occurred, the lower limit value of the accumulated DSV data is output. On the other hand, when neither an overflow nor an underflow has occurred, the addition result is obtained. When the first determiner determines that the addition result of the first determiner to be output and the addition result of the second adder have caused an overflow, the addition result and the upper limit value of the accumulated DSV data are determined. While calculating the difference, the first determiner determines that the addition result of the second adder is underflowing. Is the difference between the lower limit value of the cumulative DSV data and the addition result calculated when the a first difference calculator for outputting the calculation result as a first difference data,
A difference data holding unit, a difference adder that adds data output from the first determination unit and data held in the difference data holding unit, and outputs a result of the addition; It is determined whether or not the result has caused an overflow or an underflow. If an overflow has occurred, the upper limit value of the accumulated DSV data is output as new accumulated DSV data. Outputting the lower limit value of the data as the new accumulated DSV data, and outputting the addition result as the new accumulated DSV data when neither overflow nor underflow has occurred;
And the difference between the addition result and the upper limit of the cumulative DSV data when the addition result of the difference adder is determined by the second determination device to be overflowing, When the second determiner determines that the addition result of the difference adder is underflowing, the addition result and the accumulated DSV
A second difference calculator that calculates a difference between the lower limit value of the data and outputs the calculation result as second difference data, and adds the first difference data and the second difference data, And a holding data adder for holding the addition result in the difference data holding device.

According to the third aspect of the invention, when the first determiner determines that the addition result of the second adder has caused an overflow, the addition result and the accumulated DSV are compared.
The difference between the data and the upper limit value is output from the first difference calculator as first difference data. After the first difference data is added to second difference data described later, the first difference data is held in a difference data holding unit, and is added by a difference adder at the next calculation. Also, when the second determiner determines that the addition result of the difference adder has caused an overflow, the difference between the addition result and the upper limit value of the accumulated DSV data is calculated by the second difference calculator from the second difference calculator. Output as difference data. After the second difference data is added to the first difference data, the second difference data is held in the difference data holding unit, and is added by the difference adder at the next calculation. For this reason, even if an overflow occurs, an error with respect to the true accumulated DSV data will be corrected later, and even if an overflow occurs when the error is corrected, the true accumulated DV data will be corrected.
The error with respect to the SV data will be corrected later.

When the first determiner determines that the addition result of the second adder is underflowing, the difference between the addition result and the lower limit of the accumulated DSV data is equal to the first difference. It is output as first difference data from the calculator. After the first difference data is added to second difference data described later, the first difference data is held in a difference data holding unit, and is added by a difference adder at the next calculation. Further, when the second determiner determines that the addition result of the difference adder is underflowing, the difference between the addition result and the upper limit value of the accumulated DSV data is calculated by the second difference calculator from the second difference calculator. Is output as the differential data of. After the second difference data is added to the first difference data, the second difference data is held in the difference data holding unit, and is added by the difference adder at the next calculation. Therefore, even if an underflow occurs, an error with respect to the true accumulated DSV data will be corrected later. Even if an underflow occurs when the error is corrected, an error with respect to the true accumulated DSV data will be corrected later. It will be corrected.

According to a fourth aspect of the present invention, in the configuration of the third aspect, the first determiner includes a most significant bit of the accumulated DSV data, a most significant bit of an addition result of the first adder, Based on the most significant bit of the addition result of the second adder, it is determined whether or not the addition result of the second adder has caused an overflow or an underflow. And an upper limit / lower limit recognizer that outputs an underflow signal when an underflow occurs, and an overflow signal from the upper limit / lower limit recognizer outputs the first difference. A calculator is provided with an upper limit value of the cumulative DSV data as upper limit value / lower limit value data and the second limit value.
And outputs an upper limit value of the accumulated DSV data to the difference adder, while outputting an upper limit value of the accumulated DSV data to the difference adder, and outputs an underflow from the upper limit value / lower limit value recognizer. When the signal is input, the first difference calculator is informed that the lower limit value of the accumulated DSV data as the upper limit value / lower limit value data and the addition result of the second adder are underflowing. And a data selector that outputs a lower limit value of the accumulated DSV data to the difference adder.

According to a fifth aspect of the present invention, in the configuration of the fourth aspect, the first difference calculator accumulates the upper limit value / lower limit value data output from the data selector of the first decision unit.
A subtractor that subtracts the V data from the V data, and outputs a result of the subtraction; an adder that adds the subtraction result of the subtractor to the addition result of the first adder and outputs the addition result; A data selector that outputs the addition result of the adder as first difference data when the addition result of the adder is transmitted by a determination signal output from the data selector that an overflow or underflow has occurred. Is added.

According to a sixth aspect of the present invention, in the configuration of the third aspect, the second determiner holds the most significant bit of the output data of the first determiner and the difference data holder. Based on the most significant bit of the data and the most significant bit of the result of addition of the difference adder, it is determined whether the addition result of the difference adder has caused an overflow or an underflow. When an overflow signal is output, an underflow signal is output when an underflow occurs, and an upper limit / lower limit value recognizer that outputs an underflow signal. That the upper limit value of the accumulated DSV data as the upper limit value / lower limit value data and the addition result of the difference adder cause an overflow in the difference calculator. While outputting a judgment signal to be transmitted and outputting an upper limit value of the accumulated DSV data as a new accumulated DSV, when an underflow signal is input from the upper limit / lower limit value recognizer, the second difference calculator And outputs a lower limit value of the accumulated DSV data as upper limit value / lower limit value data and a determination signal for notifying that the addition result of the difference adder is underflowing, and outputs the accumulated DSV data as new accumulated DSV data. And a data selector for outputting a lower limit value of data.

According to a seventh aspect of the present invention, in the configuration of the sixth aspect, the second difference calculator includes an upper limit value / lower limit value data output from a data selector included in the second determiner. A subtractor that subtracts from the output data of the determiner and outputs a result of the subtraction, and an adder that adds the result of the subtraction and the data held in the difference data holder and outputs the addition result. When the determination result output from the data selector indicates that the addition result of the difference adder has caused an overflow or an underflow, data that outputs the addition result of the adder as second difference data A configuration having a selector is added.

[0040]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a DSV calculator according to one embodiment of the present invention. In FIG.
12 is a merging bit DSV calculator, 14 is a frame signal DSV / polarity estimator, 16 is an adding means, and 20 is an overflow / underflow processor. Addition means 1
6 includes a first bit converter 16a, a second bit converter 16b, a first adder 16c, and a second adder 16d.

Here, it is assumed that the accumulated DSV data is represented by 8 bits. That is, the upper limit value of the accumulated DSV data is “127” and the lower limit value is “−128”.

When the merging bit output from the merging bit generator is input, the merging bit DSV calculator 12 calculates the DSV value of the merging bit in consideration of the accumulated polarity up to the immediately preceding frame signal. Then, the calculation result is output to the first bit converter 16a as merging bit DSV data. Further, the accumulated polarity signal obtained when the merging bit is connected to the immediately preceding frame signal is used as a temporary accumulated polarity signal as the frame signal DS.
Output to V / polarity evaluator 14.

The frame signal DSV / polarity evaluator 14
The frame signal DSV data and the frame signal polarity signal for the frame signal input to the merging bit generator are input while the temporary accumulated polarity signal is input, and the frame after the polarity evaluation is performed in consideration of the temporary accumulated polarity signal. The signal DSV data is output. Further, it outputs the accumulated polarity signal up to the input frame signal as a new accumulated polarity signal.

The adding means 16 adds the accumulated DSV data up to the immediately preceding frame signal, the merging bit DSV data, and the frame signal DSV data after the polarity evaluation, and outputs an addition result.

In the adding means 16, the first bit converter 16a adjusts the number of bits of the input merging bit DSV data to the number of bits of the accumulated DSV data.
Further, the second bit converter 16b accumulates the number of bits of the input polarity-evaluated frame signal DSV data into the accumulated DSV data.
Match the number of data bits. The first adder 16c is
The output data of the first bit converter 16a and the output data of the second bit converter 16b are added. The second adder 16d adds the accumulated DSV data and the output data of the first adder 16c. The output data of the second adder 16d is output to the overflow / underflow processor 20. Further, the accumulated DSV data and the first adder 1
The output data 6c is also output to the overflow / underflow processor 20.

Overflow / underflow processor 2
0 is the output data of the first adder 16c, the output data of the second adder 16d and the accumulated DS in the adding means 16.
With V data as input, overflow and underflow are determined, and new accumulated DSV data is output.

FIG. 2 is a block diagram showing the configuration of the overflow / underflow processor 20. In FIG. 2, reference numeral 21 denotes a first decision unit, 22 denotes a first difference calculator, 2
3 is a retained data adder, 24 is a differential data retainer, 25
Is a difference adder, 26 is a second determiner, and 27 is a second difference calculator. The first determiner 21 includes an upper / lower value recognizer 21a and a data selector 21b, and the second determiner 26 includes an upper / lower value recognizer 26a and a data selector 26b.

The first determiner 21 is provided with a second adder 16d.
It is determined whether the output data has overflowed or underflowed. First difference calculator 22
Calculates the difference from the upper limit value "127" when the output data of the second adder 16d overflows, and calculates the difference from the lower limit value "-128" when the output data of the second adder 16d underflows. Calculate and output the calculation result as first difference data.

The held data adder 23 adds the first difference data and the second difference data output from the second difference calculator 27, and adds the addition result at the time of calculating the next accumulated DSV data. For this purpose, the data is held in the difference data holding unit 24.

The difference adder 25 adds the output data of the first decision unit 21 and the difference data held in the difference data holding unit 24.

The second determiner 26 determines whether or not the output data of the difference adder 25 has caused an overflow or an underflow. The output data of the second determiner 26 is output as new accumulated DSV data. The second difference calculator 27 calculates the difference from the upper limit value “127” when the output data of the difference adder 25 has overflowed, and calculates the lower limit value “−128” when it has underflowed. ”And calculate the difference to the second
Is output to the held data adder 23 as differential data of

The operation of the overflow / underflow processor 20 shown in FIG. 2 will be described by taking as an example a case where the accumulated DSV data overflows.

First, a first operation example will be described. Table 1 is a table showing a change in each data in the first operation example.

[0055]

[Table 1]

First, it is assumed that "130" is obtained as output data of the second adder 16d (column A). It is also assumed that the difference data holding unit 24 holds data “0”. At this time, the first determiner 21 outputs the second adder 16d.
It is determined that the output data has overflown, and the first difference calculator 22 outputs “1” as the upper limit value / lower limit value data.
27 "is output, and the fact that the output data of the second adder 16d has caused an overflow is transmitted by a determination signal, and the data" 127 "is sent to the difference adder 25.
Is output.

The first difference calculator 22 recognizes from the judgment signal that the output data of the second adder 16d has overflowed, and outputs the upper limit value / lower limit value data and the accumulated D value.
The first difference data “3” is calculated based on the SV data and the output data of the first adder 16 c and output to the held data adder 23.

The difference adder 25 adds the output data “127” of the first judging unit 21 and the difference data held in the difference data holding unit 24, and adds the difference data held in the difference data holding unit 24. Is "0" and outputs "127". The second determiner 26 does not output data to the second difference calculator 27 because the output data of the difference adder 25 does not cause an overflow, and the new accumulated DSV
"127" is output as data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs the data “3” to the difference data holder 24 and holds it.

Next, it is assumed that the output data of the first adder 16c has become "-7" (column B). At this time, the output data of the second adder 16d becomes “120”, and the first determiner 21 sends the output data of the second adder 16d to the first difference calculator 22 since the overflow has not occurred. Does not output data, and outputs data “12” to the difference adder 25.
The first difference data output from the first difference calculator 22 is "0".

The difference adder 25 adds the data “120” output from the first decision unit 21 and the data “3” held in the difference data holding unit 24, and adds the data “123”.
Is output to the second determiner 26. The second determiner 26 is
Since the output data of the difference adder 25 has not overflown, no data is output to the second difference calculator 27, and "123" is output as new accumulated DSV data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs the data “0” to the difference data holder 24 and holds it.

Next, it is assumed that the output data of the first adder 16c has become "+6" (column C). At this time, the output data of the second adder 16d becomes “129”, the first determiner 21 determines that the output data of the second adder 16d has overflowed, and the first difference calculator 22 "127" is output as the upper limit value / lower limit value data, and the determination signal indicates that the output data of the second adder 16d is overflowing. Further, data “127” is output to the difference adder 25.

The first difference calculator 22 recognizes from the judgment signal that the output data of the second adder 16d has overflown, and outputs the upper limit value / lower limit value data and the accumulated D value.
The first difference data “2” is calculated based on the SV data and the output data of the first adder 16 c and output to the held data adder 23.

The difference adder 25 adds the output data “127” of the first judging unit 21 and the difference data held in the difference data holding unit 24, and adds the difference data held in the difference data holding unit 24. Is "0", "127" is output. The second decision unit 26 does not output data to the second difference calculator 27 because the output data of the difference adder 25 does not cause an overflow, and the new accumulated DS
"127" is output as V data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs the data “2” to the difference data holder 24 and holds it.

Next, it is assumed that the output data of the first adder 16c becomes "-5" (column D). At this time, the output data of the second adder 16d becomes “122”, and the first determiner 21 sends the output data of the second adder 16d to the first difference calculator 22 since the overflow has not occurred. Does not output data, and outputs data “12” to the difference adder 25.
2 ". The first difference data output from the first difference calculator 22 is" 0 ".

The difference adder 25 adds the data “122” output from the first decision unit 21 and the data “2” held in the difference data holding unit 24, and obtains the data “124”.
Is output to the second determiner 26. The second determiner 26 is
Since the output data of the difference adder 25 has not overflown, no data is output to the second difference calculator 27, and "124" is output as new accumulated DSV data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs data “0” to the difference data holder 24.

FIG. 3 is a graph showing a change in data in the first operation example. In FIG. 3, ○ indicates output data of the second adder 16d, and □ indicates output data of the second determiner 26, that is, new accumulated DSV data. When the output data of the second adder 16d overflows beyond the upper limit value "127", it can be seen that the difference data is added when calculating the accumulated DSV data in the next frame signal.

As described above, even if the output data of the second adder 16d overflows, the overflowed data is held in the difference data holding unit 24,
Is added again when the output data of the adder 16d falls below the upper limit value, so that accurate accumulated DSV data is obtained.

Next, a second operation example will be described. Table 2 is a table showing changes in each data in the second operation example.

[0069]

[Table 2]

First, it is assumed that "132" is obtained as output data of the second adder 16d (column A). It is also assumed that the difference data holding unit 24 holds data “0”. At this time, the first determiner 21 outputs the second adder 16d.
It is determined that the output data has overflown, and the first difference calculator 22 outputs “1” as the upper limit value / lower limit value data.
27 "is output, and the fact that the output data of the second adder 16d has caused an overflow is transmitted by a determination signal, and the data" 127 "is sent to the difference adder 25.
Is output.

The first difference calculator 22 recognizes from the judgment signal that the output data of the second adder 16d has overflowed, and outputs the upper limit value / lower limit value data and the accumulated D value.
The first difference data “5” is calculated based on the SV data and the output data of the first adder 16 c and output to the held data adder 23.

The difference adder 25 adds the output data “127” of the first judging unit 21 and the difference data held in the difference data holding unit 24, and adds the difference data held in the difference data holding unit 24. Is "0", "127" is output. The second decision unit 26 does not output data to the second difference calculator 27 because the output data of the difference adder 25 does not cause an overflow, and the new accumulated DS
"127" is output as V data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs data “5” to the difference data holder 24.

Next, it is assumed that the output data of the first adder 16c has become "-2" (column B). At this time, the output data of the second adder 16d is “125”, and the first determiner 21 sends the output data of the second adder 16d to the first difference calculator 22 because the overflow of the output data has not occurred. Does not output data, and outputs data “12” to the difference adder 25.
5 ". The first difference data output from the first difference calculator 22 is" 0 ".

The difference adder 25 adds the data “125” output from the first decision unit 21 and the data “5” held in the difference data holding unit 24 to obtain data “130”.
Is output to the second determiner 26. The second determiner 26 is
It is determined that the output data of the difference adder 25 has overflowed, and “127” is output to the second difference calculator 27 as upper limit value / lower limit value data.
That the output data has overflown is transmitted by a determination signal. Also, “127” is output as new accumulated DSV data.

The second difference calculator 27 recognizes that the output data of the difference adder 25 has caused the overflow by the judgment signal, and outputs the output data of the first judgment unit 21 and the data held by the difference data holding unit 24. The second difference data “3” is calculated based on the output data of the difference adder 25 and output to the held data adder 23. The held data adder 23 outputs the data “3” to the difference data holder 24.

Next, it is assumed that the output data of the first adder 16c has become "-2" (column C). At this time, the output data of the second adder 16d is “125”, and the first determiner 21 sends the output data of the second adder 16d to the first difference calculator 22 because the overflow of the output data has not occurred. Does not output data, and outputs data “12” to the difference adder 25.
5 ". The first difference data output from the first difference calculator 22 is" 0 ".

The difference adder 25 adds the data “125” output from the first decision unit 21 and the data “3” held in the difference data holding unit 24 to obtain data “128”.
Is output to the second determiner 26. The second determiner 26 is
It is determined that the output data of the difference adder 25 has overflowed, and “127” is output to the second difference calculator 27 as upper limit value / lower limit value data.
That the output data has overflown is transmitted by a determination signal. Also, “127” is output as new accumulated DSV data.

The second difference calculator 27 recognizes that the output data of the difference adder 25 has caused an overflow by the judgment signal, and outputs the output data of the first judgment unit 21 and the data held by the difference data holding unit 24. The second difference data “1” is calculated based on the output data of the difference adder 25 and output to the held data adder 23. The held data adder 23 outputs the data “1” to the difference data holder 24.

Next, assume that the output data of the first adder 16c becomes "-5" (column D). At this time, the output data of the second adder 16d becomes “122”, and the first determiner 21 sends the output data of the second adder 16d to the first difference calculator 22 since the overflow has not occurred. Does not output data, and outputs data “12” to the difference adder 25.
2 ". The first difference data output from the first difference calculator 22 is" 0 ".

The difference adder 25 adds the data “122” output from the first decision unit 21 and the data “1” held in the difference data holding unit 24 to obtain the data “123”.
Is output to the second determiner 26. The second determiner 26 is
Since the output data of the difference adder 25 has not overflown, no data is output to the second difference calculator 27, and "123" is output as new accumulated DSV data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs data “0” to the difference data holder 24.

FIG. 4 is a graph showing a change in data in the second operation example. In FIG. 4, ○ indicates output data of the second adder 16d, and □ indicates output data of the second determiner 26, that is, new accumulated DSV data. When the output data of the second adder 16d overflows beyond the upper limit value "127", the difference data is stored in the next accumulated DS.
It can be seen that it is added when calculating the V data. Also,
It can be seen that even when overflow occurs when the difference data is added, the difference data is added at the time of calculating the next accumulated DSV data.

As described above, even if the output data of the second adder 16d overflows, the data corresponding to the overflow is held in the difference data holding unit 24,
Is added again when the output data of the adder 16d falls below the upper limit value "127", and even if the added data overflows, the overflowed data is held in the difference data holding unit 24. , Second
Is added again when the output data of the adder 16d falls below the upper limit "127", so that accurate accumulated DSV data is obtained.

Next, a third operation example will be described. Table 3 is a table showing changes in each data in the third operation example.

[0084]

[Table 3]

First, it is assumed that "130" is obtained as output data of the second adder 16d (column A). It is also assumed that the difference data holding unit 24 holds data “0”. At this time, the first determiner 21 outputs the second adder 16d.
It is determined that the output data has overflown, the determination result is transmitted to the first difference calculator 22 by the determination signal, and "127" is output as the upper limit value / lower limit value data. Further, data “127” is output to the difference adder 25.

The first difference calculator 22 recognizes that the output data of the second adder 16d has overflown based on the judgment signal, and outputs the upper limit value / lower limit value data and the accumulated D value.
The first difference data “3” is calculated based on the SV data and the output data of the first adder 16 c and output to the held data adder 23.

The difference adder 25 adds the output data “127” of the first judging unit 21 and the difference data held in the difference data holding unit 24, and adds the difference data held in the difference data holding unit 24. Is "0", "127" is output. The second decision unit 26 does not output data to the second difference calculator 27 because the output data of the difference adder 25 does not cause an overflow, and the new accumulated DS
"127" is output as V data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs data “3” to the difference data holder 24.

Next, it is assumed that the output data of the first adder 16c has become "+3" (column B). At this time, the output data of the second adder 16d becomes “130”, the first determiner 21 determines that the output data of the second adder 16d has overflowed, and the first difference calculator 22 This determination result is transmitted by a determination signal and "127" is output as upper limit value / lower limit value data. Further, data “127” is output to the difference adder 25.

The first difference calculator 22 recognizes that the output data of the second adder 16d has overflown by the judgment signal, and outputs the upper limit value / lower limit value data and the accumulated D value.
The first difference data “3” is calculated based on the SV data and the output data of the first adder 16 c and output to the held data adder 23.

The difference adder 25 adds the data “127” output from the first decision unit 21 and the data “3” held in the difference data holding unit 24 to obtain data “130”.
Is output to the second determiner 26. The second determiner 26 is
It is determined that the output data of the difference adder 25 has overflowed, the determination result is transmitted to the second difference calculator 27 by a determination signal, and “127” is output as the upper limit value / lower limit value data. Also, “127” is output as new accumulated DSV data.

The second difference calculator 27 recognizes that the output data of the difference adder 25 has caused an overflow by the judgment signal, and outputs the output data of the first judgment unit 21 and the data held in the difference data holding unit 24. The second difference data “3” is calculated based on the output data of the difference adder 25 and output to the held data adder 23. The held data adder 23 adds the first difference data “3” and the second difference data “3”, and outputs the addition result “6” to the difference data holder 24.

Next, it is assumed that the output data of the first adder 16c has become "+3" (column C). At this time, the output data of the second adder 16d becomes “130”, the first determiner 21 determines that the output data of the second adder 16d has overflowed, and the first difference calculator 22 This determination result is transmitted by a determination signal and "127" is output as upper limit value / lower limit value data. Further, data “127” is output to the difference adder 25.

The first difference calculator 22 recognizes from the judgment signal that the output data of the second adder 16d has overflowed, and outputs the upper limit value / lower limit value data and the accumulated D value.
The first difference data “3” is calculated based on the SV data and the output data of the first adder 16 c and output to the held data adder 23.

The difference adder 25 adds the data “127” output from the first decision unit 21 and the data “6” held in the difference data holding unit 24 to obtain data “133”.
Is output to the second determiner 26. The second determiner 26 is
It is determined that the output data of the difference adder 25 has overflowed, the determination result is transmitted to the second difference calculator 27 by a determination signal, and “127” is output as the upper limit value / lower limit value data. Also, “127” is output as new accumulated DSV data.

The second difference calculator 27 recognizes that the output data of the difference adder 25 has overflown by the judgment signal, and outputs the output data of the first judgment unit 21 and the data held by the difference data holding unit 24. The second difference data “6” is calculated based on the output data of the difference adder 25 and output to the held data adder 23. The held data adder 23 adds the first difference data “3” and the second difference data “6”, and outputs the added result “9” to the difference data holder 24.

Next, it is assumed that the output data of the first adder 16c has become "+3" (column D). At this time, the output data of the second adder 16d becomes “130”, the first determiner 21 determines that the output data of the second adder 16d has overflowed, and the first difference calculator 22 This determination result is transmitted by a determination signal and "127" is output as upper limit value / lower limit value data. Further, data “127” is output to the difference adder 25.

The first difference calculator 22 recognizes from the judgment signal that the output data of the second adder 16d has overflowed, and outputs the upper limit value / lower limit value data and the accumulated D value.
The first difference data “3” is calculated based on the SV data and the output data of the first adder 16 c and output to the held data adder 23.

The difference adder 25 adds the data “127” output from the first decision unit 21 and the data “9” held in the difference data holding unit 24 to obtain the data “136”.
Is output to the second determiner 26. The second determiner 26 is
It is determined that the output data of the difference adder 25 has overflowed, the determination result is transmitted to the second difference calculator 27 by a determination signal, and “127” is output as the upper limit value / lower limit value data. Also, “127” is output as new accumulated DSV data.

The second difference calculator 27 recognizes that the output data of the difference adder 25 has overflown by the judgment signal, and outputs the output data of the first judgment unit 21 and the data held in the difference data holding unit 24. The second difference data “9” is calculated based on the output data of the difference adder 25 and output to the held data adder 23. The held data adder 23 adds the first difference data “3” and the second difference data “9”, and outputs the added result “12” to the difference data holder 24.

Next, it is assumed that "-15" is obtained as the output data of the first adder 16c (column E). At this time,
The output data of the second adder 16d is "112",
The first determiner 21 does not output the data to the first difference calculator 22 because the output data of the second adder 16 d does not overflow, and the data “112” is directly output to the difference adder 25. Output. First difference adder 22
Is "0".

The difference adder 25 adds the data “112” output from the first decision unit 21 and the data “12” held in the difference data holding unit 24, and adds the data “12”.
4 "is output to the second determiner 26. The second determiner 26
Outputs no data to the second difference calculator 27 because the output data of the difference adder 25 does not overflow, and outputs "124" as new accumulated DSV data. Since the second difference data output from the second difference calculator 27 is “0”, the held data adder 23 outputs data “0” to the difference data holder 24.

FIG. 5 is a graph showing a change in data in the third operation example. In FIG. 5, ○ indicates output data of the second adder 16d, and □ indicates output data of the second determiner 26, that is, new accumulated DSV data. Even when the output data of the second adder 16d continuously overflows beyond the upper limit value "127", it can be seen that the difference data is accumulated and added at the time of calculating the next accumulated DSV data.

As described above, even if the output data of the second adder 16d continuously overflows, the data corresponding to the overflow is accumulated and stored in the difference data holding unit 2d.
4 and is added again when the output data of the second adder 16d falls below the upper limit “127”.
Accurate accumulated DSV data is required.

The configurations of the first determiner 21 and the second determiner 26 will be described in more detail. First determiner 21
And the second determiner 26 are realized by a similar configuration, and therefore the first determiner 21 will be described here as an example.

The upper limit / lower limit recognizer 21a stores the cumulative D
SV data, the output data of the first adder 16c and the second
Of the most significant bit (M
SB) is input. The MSB of the accumulated DSV data and the MSB of the output data of the first adder 16c are “0”, and the MSB of the output data of the second adder 16d is “1”.
In this case, the upper limit / lower limit recognizer 21a recognizes that the accumulated DSV data has overflowed and outputs an overflow signal to the data selector 21b. When the MSB of the accumulated DSV data and the MSB of the output data of the first adder 16c are "1" and the MSB of the output data of the second adder 16d is "0", the upper limit value and the lower limit value are set. The recognizer 21a recognizes that the accumulated DSV data has underflowed, and outputs an underflow signal to the data selector 21b.

When neither the overflow signal nor the underflow signal is input, the data selector 21b outputs the output data of the second adder 16d to the difference adder 25 as it is. When the overflow signal is input, "127" is output to the difference adder 25, the overflow is notified to the first difference calculator 22 by the judgment signal, and "127" is output as the upper limit value / lower limit value data. . When the underflow signal is input, "-128" is output to the difference adder 25, the underflow is notified to the first difference calculator 22 by the judgment signal, and "-128" is output as the upper limit value / lower limit value data. 12
8 "is output.

The configurations of the first difference calculator 22 and the second difference calculator 27 will be described in more detail. Since the first difference calculator 22 and the second difference calculator 26 are realized by the same configuration, here, the first difference calculator 22 is used.
Will be described as an example.

FIG. 6 shows the first difference calculator 22 shown in FIG.
FIG. 3 is a block diagram showing the configuration of FIG. In FIG. 6, 22a
Is a subtractor, 22b is an adder, and 22c is a data selector.

When the output data of the second adder 16d is overflowing, the subtractor 22a outputs the accumulated DS.
The difference between the V data and the upper limit value data “127” is calculated and output as subtraction data. The adder 22b includes a subtractor 22
The sum of the subtraction data output from a and the output data of the first adder 16c is calculated and output as addition data.
When the output data of the second adder 16d is underflowing, the subtractor 22a calculates the difference between the accumulated DSV data and the lower limit data "-128" and outputs the result as subtraction data. The adder 22b calculates the sum of the subtraction data output from the subtractor 22a and the output data of the first adder 16c, and outputs the result as addition data.

When the data selector 22c recognizes that the output data of the second adder 16d has caused an overflow or an underflow by the judgment signal, the adder 2c
The added data output from 2b is output as it is as the first difference data. When neither overflow nor underflow occurs, “0” is output as the first difference data.

As described above, the first determiner 21 and the second determiner 26, and the first difference calculator 22 and the second difference calculator can be realized by a simple configuration. 20 can be realized by a configuration with a small circuit scale.

[0112]

According to the DSV calculation apparatus according to the first or second aspect of the present invention, even if an overflow or an underflow occurs in the accumulated DSV data obtained by calculation, an error with respect to the true accumulated DSV data is corrected later. , The accuracy of the accumulated DSV data is improved.

According to the DSV calculation apparatus of the third aspect, even if an overflow or an underflow occurs in the accumulated DSV data obtained by the calculation, the true accumulated D
Since the error with respect to the SV data is corrected later, and the error with respect to the true accumulated DSV data is corrected later even if an overflow or underflow occurs when the error is corrected, the accuracy of the accumulated DSV data is further improved.

According to the DSV calculator according to the fourth to seventh aspects of the present invention, the overflow / underflow processor can be realized with a small circuit scale, so that the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DSV calculation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an overflow / underflow processor in the DSV calculation device shown in FIG.

FIG. 3 is a graph showing a change in data in a first operation example of the overflow / underflow processor shown in FIG. 2;

FIG. 4 is a graph showing a change in data in a second operation example of the overflow / underflow processor shown in FIG. 2;

FIG. 5 is a graph showing a change in data in a third operation example of the overflow / underflow processor shown in FIG. 2;

FIG. 6 is a block diagram illustrating a configuration of a first difference calculator in the overflow / underflow processor illustrated in FIG. 2;

7A is a diagram illustrating a part of a conversion table in EFM modulation and a waveform of EFM-modulated data, and FIG. 7B is a diagram for explaining a DSV calculation method.

8A and 8B are graphs showing changes in accumulated DSV data in a conventional DSV calculation device, wherein FIG. 8A is a graph when no overflow occurs, and FIG. 8B is a graph when an overflow occurs.

[Explanation of symbols]

 Reference Signs List 12 Merging bit DSV calculator 14 Frame signal DSV polarity evaluator 16 Adder 16a First bit converter 16b Second bit converter 16c First adder 16d Second adder 20 Overflow underflow processor 21st 1 determiner 21a upper / lower value recognizer 21b data selector 22 first difference calculator 23 held data adder 24 difference data holder 25 difference adder 26 second determiner 26a upper / lower value recognition 26b Data selector 27 Second difference calculator 22a Subtractor 22b Adder 22c Data selector

Continuation of front page (56) References JP-A-59-57549 (JP, A) JP-A-61-230679 (JP, A) JP-A-62-281523 (JP, A) JP-A-63-298775 (JP) JP-A 1-252023 (JP, A) JP-A 63-18822 (JP, A) JP-A 62-283719 (JP, A) JP-A 2-114724 (JP, A) 4-339365 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 7/14 G11B 20/14 341 H04L 25/49

Claims (7)

(57) [Claims] 1. An EFM (Eight to Fourteen Modulatio)
n) In modulation, DS as an index for selecting merging bits for connecting modulated frame signals to each other
A DSV calculator for calculating V (Digital Sum Variation) every time one frame signal is input, wherein D is a value up to a frame signal immediately before the one frame signal.
Cumulative DSV data representing the value of the SV, frame signal DSV data representing the value of the DSV of the one frame signal, and merging bits for connecting the one frame signal and the frame signal immediately before the one frame signal. Adding means for adding merging bit DSV data representing the value of DSV and outputting the addition result; and determining whether the addition result output from the addition means has caused overflow or underflow, and determining whether the overflow or underflow has occurred. An overflow / underflow processor that performs exception processing on the addition result when the flow is occurring and outputs the result as new accumulated DSV data; and wherein the overflow / underflow processor outputs the addition result. When the addition result is overflowing, The holds the difference between the upper limit value of the cumulative DSV data, while output addition result from said adding means for adding the difference held when no overflows to the addition result and,
When the addition result output from the addition means underflows, the difference between the addition result and the lower limit value of the accumulated DSV data is held, and the addition result output from the addition means underflows. A DSV calculation device having a function of adding a difference held when the difference is not present to the addition result. 2. An adder for adding a merging bit DSV data and a frame signal DSV data and outputting a result of the addition, a first adder for adding the result of the addition and the accumulated DSV data to the first adder. 2. The DSV calculation apparatus according to claim 1, further comprising: a second adder for adding the sum and outputting the addition result. 3. An overflow / underflow processor determines whether or not the addition result of the second adder has caused an overflow or an underflow. If an overflow has occurred, the overflow / underflow processor determines an upper limit value of the accumulated DSV data. If the output is underflow, the accumulated DSV
While outputting the lower limit value of the data, when neither overflow nor underflow has occurred, a first determiner that outputs the addition result, and that the addition result of the second adder has caused an overflow. While the difference between the addition result and the upper limit value of the accumulated DSV data is calculated when determined by the first determiner, the first result indicates that the addition result of the second adder is underflowed. A first difference calculator that calculates a difference between the addition result and the lower limit value of the accumulated DSV data when the determination result is determined by the determination unit, and outputs the calculation result as first difference data; A difference adder that adds data output from the first determiner and data held in the difference data holding unit, and outputs a result of the addition; It is determined whether or not the result of addition has caused an overflow or an underflow. When an overflow has occurred, the upper limit value of the accumulated DSV data is output as new accumulated DSV data. A second determiner that outputs a lower limit value of the accumulated DSV data as the new accumulated DSV data, and outputs an addition result as the new accumulated DSV data when neither overflow nor underflow occurs; When it is determined by the second determiner that the addition result of the adder has caused an overflow, the difference between the addition result and the upper limit value of the accumulated DSV data is calculated, while the addition result of the difference adder is calculated. Before the second determiner determines that the underflow has occurred A second difference calculator that calculates a difference between the addition result and the lower limit value of the accumulated DSV data, and outputs the calculation result as second difference data; and a second difference calculator that calculates the difference between the first difference data and the second difference. 3. A holding data adder for adding data and holding the addition result in the difference data holding unit.
3. The DSV calculator according to 1. 4. The DSV calculation apparatus according to claim 3, wherein the first determiner includes a most significant bit of the accumulated DSV data, a most significant bit of an addition result of the first adder, and the second bit. It is determined whether or not the addition result of the second adder has caused an overflow or an underflow based on the most significant bit of the addition result of the adder. If an overflow has occurred, an overflow signal is output. On the other hand, when an underflow occurs, an upper limit / lower limit value recognizer that outputs an underflow signal, and when an overflow signal is input from the upper limit / lower limit value recognizer, the first difference calculator Determination that the upper limit value of the accumulated DSV data as the upper limit value / lower limit value data and the addition result of the second adder indicate that an overflow has occurred. While outputting a signal and outputting the upper limit value of the accumulated DSV data to the difference adder, when an underflow signal is input from the upper limit value / lower limit value recognizer, the upper limit value is supplied to the first difference calculator. The lower limit of the cumulative DSV data as the lower limit data and the second lower limit;
And a data selector for outputting a determination signal indicating that the addition result of the adder underflow has occurred and outputting a lower limit value of the accumulated DSV data to the difference adder. Computing device. 5. A first difference calculator for subtracting upper limit value / lower limit value data output from a data selector included in a first determiner from accumulated DSV data, and outputting a subtraction result. The adder that adds the subtraction result of the subtractor and the addition result of the first adder and outputs the addition result, and that the addition result of the second adder causes an overflow or an underflow. 5. The DSV calculation according to claim 4, further comprising: a data selector that outputs the addition result of the adder as first difference data when transmitted by a determination signal output from the data selector. 6. apparatus. 6. The DSV calculation device according to claim 3, wherein the second determiner includes a most significant bit of output data of the first determiner and a most significant bit of data stored in the difference data retainer. It is determined whether or not the addition result of the difference adder has caused an overflow or an underflow based on the most significant bit and the most significant bit of the addition result of the difference adder.If an overflow has occurred, an overflow signal is generated. An upper limit value / lower limit value recognizer that outputs an underflow signal when an underflow occurs, and an overflow signal input from the upper limit value / lower limit value recognizer, the second difference calculation. That the upper limit value of the accumulated DSV data as the upper limit value / lower limit value data and the addition result of the difference adder overflow. Is output and a new accumulated DS is output.
While the upper limit value of the accumulated DSV data is output as V, when an underflow signal is input from the upper limit value / lower limit value recognizer, the accumulated value as the upper limit value / lower limit value data is input to the second difference calculator. A data selector that outputs a lower limit value of the DSV data and a determination signal indicating that the addition result of the difference adder is underflowing, and outputs the lower limit value of the accumulated DSV data as new accumulated DSV data; DSV characterized by having
Computing device. 7. The second difference calculator subtracts upper limit value / lower limit value data output from a data selector included in the second determiner from output data of the first determiner, and calculates a result of the subtraction. A subtractor to output, an adder that adds the subtraction result of the subtractor and the data held in the difference data holding unit, and outputs the addition result, and an addition result of the difference adder causes overflow or underflow. And a data selector for outputting, as second difference data, an addition result of the adder when the determination is transmitted by a determination signal output from the data selector. The described DSV calculator.