JP3309186B2 - Channel control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo fault setting method for evaluating a channel control device, and more particularly to a high load state setting method.

[0002]

2. Description of the Related Art A conventional channel control device is connected to an external device 1 as shown in FIG. 2, and includes a channel control device 2, a plurality of channel devices 31 to 33, and channel devices 31 to 33.
A system is configured by a plurality of peripheral devices 41 to 43 connected to 33. In the design evaluation phase, various peripheral devices 41 to 43 are connected to the channel devices 31 to 3.
3, the input / output operation is executed by a test program or the like, and the result is compared with the correct answer value. Thus, the functions of the channel control device 2 and the channel devices 31 to 33 are confirmed.

When evaluating functions under a high load state such as the highest performance, peripheral devices 41 to 43 that operate at high speed, such as magnetic disks, are connected to all channel devices 31 to 33. Therefore, all the peripheral devices 41 to 43 are preferably at the same time,
In addition, an input / output operation by a test program is executed so as to operate for a long time.

[0004]

The problem to be solved is that in a high load evaluation, a special job in which all devices operate simultaneously under the condition that peripheral devices are connected to all channel devices, respectively. This is a point that needs to be developed and executed as a test program.

[0005]

SUMMARY OF THE INVENTION The present invention comprises an interrupt-inhibiting flip-flop, which allows the timing of an interrupt mask for a microprogram and the period thereof to be arbitrarily set, and connects peripheral devices to all channels. It is characterized in that evaluation under a high load state can be performed without the need.

[0006]

Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a channel control device according to the present invention. In FIG. 1, 1 is an external device, 20 is a channel control device, and 31 to 33 are channel devices. In the channel control device 20, 10 to
12 is a first to third register, 13 to 15 are first to third counters respectively, 16 is a display means for displaying a high load mode, 17 is an interrupt disable flip-flop (hereinafter referred to as an interrupt disable F / F). F.), 18
Is a priority circuit, and 19 is a microprogram control unit.

When operating in the high load mode, the external device 1 sets an appropriate count value in the first to third registers 10 to 12, and sets the display means 16 and the interrupt disable F / F 17 to "1". I do. The output of the interrupt disable F / F 17 is input to the priority circuit 18 and masks interrupt requests from the channels 31 to 33 until the interrupt disable F / F 17 is reset.

The first counter 13 has a function of the first register 10
And counts down according to the internal clock of the channel control device 20. Until all 0s are detected, the first counter 13 keeps the first register 1
Fetch a value of 0 and continue countdown. The second counter 14 takes in the value of the second register 11 and performs subtraction when the first counter 13 detects all 0s.

When the subtraction proceeds and the second counter 14 detects all 0s, the subtraction is interrupted and the interrupt disable F /
Reset F17. By resetting the interrupt disable F / F 17, the mask state for the priority circuit 18 is released, and it becomes possible to accept an interrupt request from the channel devices 31 to 33. The third counter 15 takes in the value of the third register 12 when the second counter detects all 0s, and performs subtraction when the first counter 13 detects all 0s.

When the subtraction proceeds and the third counter 15 detects all 0s, the subtraction is interrupted and the interrupt inhibition F / F1
7 is set, and the priority circuit 18 is again set to the mask state. Further, the second counter 11 stores the second register 11
Take the value of and restart the subtraction. Thereafter, the second and third counters 14 and 1 until the display unit 16 for displaying the high load mode is reset by the external device 1.
The subtraction by 5 is repeatedly performed, and all 0
Is detected, the interrupt disable F / F 17 is reset and set, and the interrupt request from the channel devices 31 to 33 is masked for a certain period.

When the third counter 15 detects all zeros, the cycle of the first counter 13 is changed by resetting the contents of the first register 10 with the microprogram address at that time. Can be.

[0012]

As described above, according to the present invention, three registers and counters are provided, respectively, so that the timing and the period of the interrupt mask from the channel device can be set freely. There is an advantage that evaluation can be performed in an effective high load state without connecting peripheral devices.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a channel control device according to the present invention.

FIG. 2 is a block diagram showing a connection example of a conventional channel control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 External device 2, 20 Channel control device 31-33 Channel device 41-43 Peripheral device 10-12 Register 13-15 Counter 16 Display means 17 Interrupt prohibition F / F 18 Priority circuit 19 Micro program control part

Claims (3)

(57) [Claims] A microprogram controller for controlling an operation sequence; a plurality of registers for setting respective count values provided by the microprogram controller; and a plurality of registers for counting the count value A counter, an interrupt prohibiting flip-flop for masking an interrupt by resetting when all 0s are detected by the counter, and controlling the interrupt request by the micro-flip-flop whenever the interrupt prohibiting flip-flop is reset. A channel control device comprising a priority circuit for sending the signal to the unit. 2. A first counter of the plurality of counters fetches a value set in a first register of the plurality of registers, performs subtraction according to an internal clock, and detects all zeros. And the interrupt prohibiting flip-flop is reset by the all 0s and accepts an interrupt, but is set again to cause the second counter of the plurality of counters to continue the same operation. 2. The channel control device according to claim 1, wherein: 3. The microprogram control unit sets the value of the first register and, if the last counter of the plurality of counters detects all 0s, sets the content of the first register. 2. The channel control device according to claim 1, wherein the period can be changed by resetting.