JP3310316B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit, and more specifically, for example, a supercomputer, a super EWS.
The present invention relates to an arithmetic device that performs vector processing at high speed and is suitable for use in fields such as (Engineering Work Station). In recent years, in scientific calculations and the like, for example, a DO loop in the FORTRAN language, that is, DO 10 I = 0,100 C (I) = A (I) * B (I) F (I) = D (I) + E ( I) In many cases, a large number of operations are concentrated in a specific loop processing, such as an iterative operation represented by 10 CONTINUE.

[0002] A process in which a certain operation is repeated for a plurality of data is called a vector process. For example, in an arithmetic device such as a vector processor that executes a large amount of scientific calculations, it is possible to execute the vector process at a high speed. Required.

[0003]

2. Description of the Related Art As a conventional arithmetic unit of this type, for example, there is a vector processor as shown in FIG. In the figure, 1 is a vector processor, 2 is an instruction control unit, 3 is an instruction register, 4 is a multiplier, 5 is an adder, 6 is a vector register, 7 is a mask register, 8 is an input / output control unit, and 9 is an input / output control unit. A CPU (Central Processing Unit) 10 is a main memory.

An outline of the operation of vector processing in the above configuration will be described. First, a predetermined instruction sequence and operation data on the main memory 10 are transferred to the vector processor 1 by the CPU 9, and the instruction sequence is stored in the instruction register 3 and the operation data is stored in the vector register 6. Next, when the CPU 9 activates the vector processor 1, the instruction control unit 2 in the vector processor 1 fetches instructions one by one from the instruction register 3 and outputs a control signal required for execution.

In each unit, data input / output and operation are executed in accordance with the control signals. For example, when multiplication is executed, operation data is read from the vector register 6 and transferred to the multiplier 4, and Performs multiplication on the operation data. The result of the multiplication by the multiplier 4 is transferred to the vector register 6, and the result of the multiplication is stored in the vector register 6. Note that the above-described control signals include read / write timings and the like necessary for these operations.

Finally, if the instruction fetched from the instruction register 3 is an end instruction, the operation is interrupted and the vector processor 1 enters a standby state. Here, consider an operation with a mask. The masked operation means that mask data is set for each element of the vector data, and no operation is performed on the masked data.

That is, A (I) is an operand, and B (I)
Is the number of operations, and M (I) is mask data. As shown in FIG. 6, when the value of A (I) × B (I) is stored in C (I), the value of M (I) is referred to. However, when "M (I) = 1", the masked operation is to prevent the result from being written to C (I). Normally, when an operation such as multiplication or addition is performed, operation data, operation target data, and mask data are transferred from the vector register 6 and the mask register 7 to the operation unit including the multiplier 4 and the adder 5 for each processing cycle. Pipeline processing is performed in which the result calculated by the device is transferred to the vector register 6 every processing cycle.

Here, since the data handled in the vector processing is an index, that is, related data distinguished by the value of I in the above equation, the maximum value or the minimum value is calculated. Can be considered. In such processing, similarly to the above-described vector processing, data for each processing cycle is transferred to an arithmetic unit that performs magnitude comparison, and this arithmetic unit receives two pieces of data at the same time, and performs a comparison between them. Big and small are judged.

FIG. 7 shows the concept of a calculation with a mask in the calculation of the maximum value or the minimum value. However, when all the data are masked, the minimum value is output as the result when the maximum value is detected, and the maximum value is output as the result when the minimum value is detected. FIG. 8 is a block diagram showing an arithmetic circuit for obtaining the maximum value or the minimum value of the vector data.

This arithmetic circuit includes input latches 11, 12,.
13, a fixed value generator 14, a magnitude comparator 15, a first selector 16, a second selector 17, a temporary latch 18, and an output latch 19. In the figure, D 'is the output signal of the input latch 11, M' is the output signal of the input latch 12, C2 'is the output signal of the input latch 13, K is the output signal of the fixed value generator 14, and S is the magnitude comparison. Output signal of the unit 15,
Q is the output signal of the first selector 16, R is the second selector 1
7, T indicates an output signal of the temporary latch 18, and O indicates an output signal of the output latch 19.

The input latch 11 is a latch circuit for temporarily holding vector data D to be operated on, and data of one element is transferred from the vector register 6 as vector data D in one cycle. The input latch 12 is a latch circuit for temporarily holding the mask information M for the vector data D. The mask information M is transferred from the mask register 7 in synchronization with the vector data D, and the mask is valid when the value is "1". And

The input latch 13 is a latch circuit for temporarily holding a signal C2 indicating that the transferred vector data D is the first element. The signal C2 is "1" in synchronization with the vector data D of the first element. Is transferred from the instruction control unit 2. The fixed value generator 14 receives the input vector data D
Is a circuit that generates the maximum value or the minimum value of the data used in the arithmetic circuit based on the signal C1 indicating which of the maximum value and the minimum value is detected when is masked.

FIG. 9A is a block diagram showing a main part of the fixed value generator 14.
The operation will be described as an integer in a two's complement representation of bits. That is, as shown in FIG. 9B, C1 = "0"
In the case of “1”, it is determined by the selector that “1”
000 "(minimum value) is selected. On the other hand, when C1 =" 1 ", it is determined by the selector that the minimum value is to be detected and" 01 "
11 ″ (maximum value) is selected and output as the signal K.

As shown in FIG. 10A, the magnitude comparator 15 is a circuit that compares the magnitudes of the two inputs A and B and outputs the result of the comparison. It will be described based on the following. When C2 ′ = “1”, that is, when the input data is the first element, the output of the signal S is “0” regardless of the value of the signal C1.

On the other hand, when C2 '= "0", that is, when the input data is the second and subsequent elements, the maximum value is detected (C1 =
"0"), when AB ≧ 0, S = “0”, A
When −B <0, S = “1”, and the minimum value is detected (C1 =
In the state of “1”), when AB ≧ 0, S = “1”, A
When -B <0, S = "0". First selector 16
As shown in FIG. 11A, the output signal S of the magnitude comparator 15, the output signal M 'of the input latch 12 (mask signal for the current data), and the output signal T of the temporary latch 18 (the previous data The output signal D 'of the input latch 11, the output signal O of the output latch 19, and the output signal K of the fixed value generator 14 are selected based on a mask signal for the input latch 11.

That is, as shown in FIG. 11B, when only the current input is masked, the previously selected maximum value or minimum value is selected, and only the previous data is masked. If so, the current input is selected. When both the current and previous data are selected, a fixed value is selected. When neither data is masked, the signal D ′ or the signal O is selected based on the output signal S of the magnitude comparator 15. Is done.

The second selector 17 is a circuit for selecting either the signal M 'or the signal T based on the output signal S of the magnitude comparator 15, as shown in FIG.
As shown in (b), when S = "0", R = M 'and S
If "1", R = T is selected. Temporary latch 18
Is a latch circuit for temporarily holding the output signal R from the second selector 17 for use as a mask signal for previous data.

The output latch 19 is a latch circuit for temporarily holding the output signal Q from the first selector 16 for use as previous data, and the output signal O
Is fed back to the magnitude comparator 15 and the first selector 16.

[0019]

However, in such a conventional arithmetic device, since the mask information for the previously input data is also latched, it is necessary to hold the mask information. There is a problem that two latch circuits are required. Further, since the first selector 16 and the second selector 17 are operated based on two types of mask information, there is a problem that the configuration of the selector becomes complicated.

[Purpose] Accordingly, an object of the present invention is to provide an arithmetic unit which simplifies a circuit configuration of a detection part of a maximum value and a minimum value of vector data with a mask.

[0021]

In order to achieve the above object, an arithmetic unit according to the present invention has a principle diagram as shown in FIG.
An arithmetic unit for calculating a maximum or minimum value in said plurality of input data based on the mask data for a plurality of input data and said plurality of input data based on said mask data, the maximum or minimum value Selection means 20 for selecting and outputting one of the fixed value data set according to which operation is to be performed and the input data ;
Output value of the plurality of input data from the selection means 20
The first input data when it is (first th element) outputs the output value as the input data the output value is other than outermost first input data from said selecting means 20 (No. 1 of the
(An element other than the eye) , the determining unit 21 that determines which of the output value and the previously output value is larger or smaller based on which of the maximum value and the minimum value is calculated. It is constituted so that it may be provided.

[0022]

According to the present invention, the number of latch circuits for holding the mask information is reduced by applying the mask data only to the currently input predetermined data.
The configuration of a selector or the like that operates based on the mask information is prevented from becoming complicated.

That is, the circuit configuration of the detection part of the maximum value and the minimum value of the masked vector data is simplified.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the arithmetic device according to the present invention,
FIG. 2 is a block diagram illustrating a schematic configuration of an arithmetic unit according to the present embodiment. First, the configuration will be described.

In FIG. 2, the same reference numerals as those given to the principle diagram shown in FIG. 1 and the conventional example shown in FIGS. 8 to 10 indicate the same parts. The arithmetic device according to the present embodiment includes input latches 11 and 12, a fixed value generator 14, a selection unit 20 including a third selector 22 and a selection unit 20 and a determination unit 21, an input latch 13, a size comparator 15, and a fourth It comprises a selector 23 and a determination means 21 comprising an output latch 19.

In the figure, P indicates an output signal of the third selector 22, and Q 'indicates an output signal of the fourth selector 23. Third
As shown in FIG. 3A, the selector 22 outputs the output signal D ′ of the input latch 11 and the output signal D ′ of the fixed value generator 14 based on the output signal M ′ of the input latch 12 (a mask signal for the current data). One of the output signals K is selected. Specifically, as shown in FIG.
“0”, that is, if the current input is not masked, the current input D ′ is selected and output as the output signal P as it is, while if it is masked (M ′ = “1”) The output K of the fixed value generator 14 is selected and output as the output signal P.

As shown in FIG. 4A, the fourth selector 23 outputs an output signal P (corresponding to the current data) of the third selector 22 and an output latch based on the output signal S of the magnitude comparator 15. This is a circuit for selecting any one of the 19 output signals O (corresponding to the previous data). As shown in FIG. 4B, when S = "0", Q = P and S = "1" Q for
= O is selected.

Next, the operation will be described. First, the instruction control unit 2
, The vector data is read from the vector register 6 and the mask data is read from the mask register 7 and transferred to the arithmetic circuit in this embodiment as signals D and M, respectively, and are latched by the input latches 11 and 12, respectively. .

The input data and the fixed value are selected by the third selector 22 based on the value of the output signal M ′ from the input latch 12. Here, when the maximum value is detected, if the vector data that is the input data is masked, the value is compared as the minimum value, so that even if the input value is large, it can be ignored.

Next, based on the output signal S of the magnitude comparator 15, the fourth selector 23 selects either input data (fixed value if masked) and the previous maximum value or minimum value. Thus, the maximum value or the minimum value of all the vector data input so far is selected. The output Q ′ of the fourth selector 23 is latched by the output latch 19 and the output O
5, and transferred to the outside.

As described above, in this embodiment, an unnecessary latch circuit for holding mask information can be omitted, and the amount of elements in the entire circuit can be reduced. Therefore, it is possible to reduce the circuit scale of the arithmetic circuit that calculates the maximum value or the minimum value of the masked vector data. In the above-described embodiment, the data used in the calculation is described as data represented by a 4-bit two's complement number. However, the present invention is not limited to this, and actual data may be, for example, floating point data. Needless to say, the bit length is also arbitrary.

[0032]

According to the present invention, it is possible to reduce the number of latch circuits for holding mask information by applying mask data only to predetermined data that is currently input, and to operate based on this mask information. It is possible to prevent the configuration of the selector or the like from becoming complicated. Therefore, the circuit configuration of the detection part of the maximum value and the minimum value of the masked vector data can be simplified.

[Brief description of the drawings]

FIG. 1 is a principle diagram of an arithmetic unit according to the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of an arithmetic device according to the present embodiment.

FIG. 3 is a diagram illustrating the configuration and operation of a third selector.

FIG. 4 is a diagram for explaining the configuration and operation of a fourth selector.

FIG. 5 is a schematic diagram of a vector processor.

FIG. 6 is a diagram illustrating a calculation with a mask.

FIG. 7 is a diagram for explaining a calculation with a mask for detecting a maximum value and a minimum value.

FIG. 8 is a block diagram illustrating a schematic configuration of a conventional arithmetic device.

FIG. 9 is a diagram illustrating the configuration and operation of a fixed value generator.

FIG. 10 is a diagram for explaining the configuration and operation of a magnitude comparator.

FIG. 11 is a diagram for explaining the configuration and operation of a first selector.

FIG. 12 is a diagram illustrating the configuration and operation of a second selector.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Vector processor 2 Instruction control part 3 Instruction register 4 Multiplier 5 Adder 6 Vector register 7 Mask register 8 Input / output control part 9 CPU 10 Main memory 11 Input latch 12 Input latch 13 Input latch 14 Fixed value generator 15 Large and small comparator 16 First selector 17 Second selector 18 Temporary latch 19 Output latch 20 Selection means 21 Judgment means 22 Third selector 23 Fourth selector

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/02 G06F 17/16

Claims (1)

(57) [Claims] 1. A computing device for computing a maximum or minimum value in said plurality of input data based on the mask data for a plurality of input data and said plurality of input data <br/>, the mask data Based on whether to calculate the maximum value or the minimum value, based on the fixed value data,
Selection means for selecting and outputting one of said input data, output values from said selection means of said plurality of input data
The first case is the input data and outputs the output value as the input data the output value of the outermost first from said selection means
When the input data is other than the input data , a determination unit that determines which of the output value and the previously output output value is larger or smaller based on which of the maximum value and the minimum value is calculated, An arithmetic device, comprising: