JP3314818B2 - Semiconductor nonvolatile memory device and erase / write method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device, and more particularly to a semiconductor nonvolatile memory device.
The required negative high voltage for erasing and writing
Circuit configuration and how to erase and write using this circuit configuration
About the law.

[0002]

2. Description of the Related Art Referring to FIG.
A method for erasing and writing will be described. In the following description, a method of erasing and writing when an N-channel nonvolatile memory element is used will be described.

When erasing a nonvolatile memory element, as shown in FIG. 3A, a negative high voltage (hereinafter referred to as -VPP) is applied to a gate 73 of a memory element 71, and a drain 75, This is performed by applying 0 V (reference voltage) to the source 77 and the bulk 79 and depleting the threshold voltage (hereinafter referred to as Vth) of the memory element 71.

When writing data to a nonvolatile memory device, as shown in FIG.
A reference voltage of 0 V is applied to the gate 83 of the
-VPP is applied to the source 87 and the bulk 89,
This is performed by enhancing Vth of the memory element 81.

[0005]

As described above, when erasing and writing to a semiconductor nonvolatile memory element,
A negative high voltage -VPP is required.

Conventionally, as shown in FIG. 4, one Zener diode 97 having one terminal connected to a power supply voltage line 95 is connected to -VPP which is the output of a negative high voltage generation circuit 91.
The line 93 is connected to control the -VPP voltage value for erasing and writing of the nonvolatile memory.

Therefore, the conventional Zener diode 9
Since there is only one 7, the -VPP voltage value at the time of erasing and
The -VPP voltage value at the time of writing is the same voltage value.

As described above, conventionally, the -VPP voltage value used for erasing and writing in a nonvolatile memory is the same at the time of erasing and at the time of writing, and therefore has the following problems. . This problem will be described with reference to the graph of FIG.

In the graph of FIG. 5, the horizontal axis indicates the number of times of rewriting, and the vertical axis indicates Vth. As shown in the graph of FIG.
As the number of times of rewriting of the memory element increases, a curve 103 indicating the value of the erase Vth and a curve 101 indicating the value of the write Vth
And the width 109 becomes narrow. As a result, the value of the erase Vth cannot be distinguished from the value of the write Vth, and the number of times of rewriting of the memory element is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to erase a semiconductor nonvolatile memory device having a large number of rewrites,
Circuit configuration for switching between different negative high voltages during writing
And an erase and write method .

[0011]

In order to achieve the above object, a semiconductor nonvolatile memory according to the present invention employs the following configuration.

The nonvolatile memory device according to the present invention comprises an erasing Zener diode, a writing Zener diode,
A zener diode switching circuit block for erasing, a zener diode switching circuit block for writing,
A semiconductor nonvolatile memory device having a negative high voltage generation circuit, wherein at the start of an erase operation, an erase program signal is used.
Of the erasing zener diode switching circuit block
After changing the input voltage, the negative high voltage
A negative high voltage is generated, and at the end of the erase operation,
After the generation of the negative high voltage from the
The erasing Zener diode according to the erase program signal
Return the input voltage of the switching circuit block to the original voltage, and
At the start of the write operation,
Zener diode switching circuit block for writing
After changing the input voltage of the negative high voltage generating circuit.
Generates a negative high voltage, and at the end of the write operation,
After the generation of negative high voltage from the high voltage generation circuit of
The write program signal is used to
The input potential of the
It is characterized by returning to voltage . Further, the erasing and writing method of the semiconductor non-volatile memory device according to the present invention comprises: an erasing zener diode; a writing zener diode; an erasing zener diode switching circuit block; a writing zener diode switching circuit block; An erasing and writing method for a semiconductor nonvolatile memory device having a circuit, wherein at the start of an erasing operation, an input voltage of said erasing Zener diode switching circuit block is changed by an erasing program signal, and then said negative high voltage is generated. A negative high voltage is generated from the circuit, and at the end of the erasing operation, the generation of the negative high voltage is terminated by the negative high voltage generating circuit, and then the erasing zener diode switching circuit block is generated by the erasing program signal. Input voltage is returned to the original voltage. A negative high voltage is generated from the negative high voltage generating circuit after changing the input voltage of the write zener diode switching circuit block with a program signal, and at the end of the writing operation, the negative high voltage generating circuit generates a negative high voltage. After the generation of the negative high voltage ends, the input potential of the write zener diode switching circuit block is returned to the original voltage by the write program signal.

(Operation) The number of times of rewriting of the nonvolatile memory element is -VPP at the time of erasing.
By setting the voltage value and the −VPP voltage value at the time of writing to different optimized −VPP voltage values, the number of times of rewriting of the memory can be increased as compared with the conventional case.

FIG. 5 is a graph showing the Vth value of the memory element when erasing and writing are performed while changing the -VPP voltage value during erasing and the -VPP voltage value during writing. As shown in the graph of FIG. 5, a curve 105 indicating the value of the write Vth and a curve 10 indicating the value of the erase Vth.
7 does not change the value of Vth even if the number of rewrites increases.

Compared with the conventional case where the −VPP voltage value at the time of erasing and the −VPP voltage value at the time of writing are the same value, the −VPP voltage value at the time of erasing and the −VPP voltage value at the time of writing according to the present invention are different from each other. Can be increased so that the number of times of rewriting of the memory element can be increased.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. The configuration of the -VPP voltage switching circuit in erasing and writing of the semiconductor non-volatile memory element of the present invention, and erasing using the -VPP voltage switching circuit,
The writing method will be described with reference to the circuit diagram of FIG.

The -VPP voltage switching circuit shown in FIG.
The erasing zener diode switching circuit block includes a circuit for switching the erasing zener diode and a circuit for switching the writing zener diode. The erasing zener diode switching circuit block is controlled by an erasing program signal PG1.
It is controlled by a write program signal G2.

First, the configuration of the switching circuit of the Zener diode will be described with reference to FIG.

As shown in FIG. 1, an erasing and writing voltage switching circuit includes an erasing zener diode 25 and an erasing zener diode switching circuit block 21.
It comprises a write zener diode 27, a write zener diode switching circuit block 23, and a -VPP voltage generation circuit 15.

The erasing zener diode switching circuit block 21 includes a first P-channel transistor 29,
It comprises a second P-channel transistor 31, a first N-channel transistor 33, a second N-channel transistor 35, and a third N-channel transistor 37.

An erase program signal PG1 is input to the drain 17 of the first P-channel transistor 29,
The gate of the first P-channel transistor 29 is connected to the reference potential line 43 of 0V, the bulk is connected to the power supply voltage line 11 of 5V, and the source is connected to the gate of the second P-channel transistor 31 and the first N-channel transistor. Transistor 3
3 and the drain of the second N-channel transistor 35.

The source of the first P-channel transistor 29, the gate of the second P-channel transistor 31,
The connection point between the gate of the first N-channel transistor 33 and the drain of the second N-channel transistor 35 is
Let it be the first node 39.

The source and bulk of the second P-channel transistor 31 are connected to the 5 V power supply voltage line 11,
The drain is connected to the drain of the first N-channel transistor 33, the gate of the third N-channel transistor 37, and the gate of the second N-channel transistor 35.

A connection point between the drain of the second P-channel transistor 31, the drain of the first N-channel transistor 33, the gate of the second N-channel transistor 35, and the gate of the third N-channel transistor 37 Is the second node 41.

Three first N-channel transistors 33
And the source and bulk of each of the second N-channel transistor 35 and the third N-channel transistor 37 are connected to the -VPP line 13, which is the output of the -VPP voltage generation circuit 15. .

The drain of the third N-channel transistor 37 is connected to the anode of the zener diode 25 for erasing.

The cathode of the erasing zener diode 25 is connected to the 5 V power supply voltage line 11.

Here, the second N-channel transistor 35
Are the other two first N-channel transistors 33,
The channel length and the channel width are smaller than those of the third N-channel transistor 37.

The write zener diode switching circuit block 23 includes a third P-channel transistor 45.
, A fourth P-channel transistor 47, a fourth N-channel transistor 49, a fifth N-channel transistor 51, and a sixth N-channel transistor 53.

The write program signal PG2 is input to the drain 19 of the third P-channel transistor 45, and the gate of the third P-channel transistor 45 is set to 0V.
, The bulk is connected to the 5 V power supply voltage line 11, the sources are the gate of the fourth P-channel transistor 47, the gate of the fourth N-channel transistor 49, and the fifth N-channel transistor. Transistor 51
Connected to the drain.

The source of the third P-channel transistor 45, the gate of the fourth P-channel transistor 47,
The connection point between the gate of the fourth N-channel transistor 49 and the drain of the fifth N-channel transistor 51 is
Let it be the third node 55.

The source and the bulk of the fourth P-channel transistor 47 are connected to the 5 V power supply voltage line 11,
The drain is connected to the drain of the fourth N-channel transistor 49, the gate of the sixth N-channel transistor 53, and the gate of the fifth N-channel transistor 51.

A connection point between the drain of the fourth P-channel transistor 47, the drain of the fourth N-channel transistor 49, the gate of the fifth N-channel transistor 51, and the gate of the sixth N-channel transistor 53 Is the fourth node 57.

Three fourth N-channel transistors 49
And the source and bulk of each of the fifth N-channel transistor 51 and the sixth N-channel transistor 53 are connected to the -VPP line 13, which is the output of the -VPP voltage generation circuit 15. .

The drain of the sixth N-channel transistor 53 is connected to the anode of the write Zener diode 27.

The cathode of the writing zener diode is connected to a 5 V power supply voltage line 11.

Here, the fifth N-channel transistor 51
Are the other two fourth N-channel transistors 49,
The channel length and channel width are smaller than those of the sixth N-channel transistor 53.

Next, the relationship between the erase program signal PG1, the write program signal PG2, and the negative high voltage -VPP when erasing and writing the memory element will be described with reference to FIG.

As shown in the waveform diagram showing the signal timing in FIG. 2, when erasing the memory element, first, the erasing program signal PG 161 is changed from the power supply voltage of 5 V to the reference potential of 0 V, and then is applied to -VPP. The line 65 is lowered from the reference potential of 0 V to the voltage of -VPP. -The VPP line is
The Zener potential of the erasing Zener diode 25 shown in FIG.

When the erasing is completed, the -VPP line 65 is returned to 0V, and then the erasing program signal PG161 is returned to 5V.

During the above-described erase cycle 67, the program signal PG263 for writing remains at the power supply potential of 5V.

When writing to a memory element, first, a write program signal PG 263 is set to a power supply voltage of 5.
V to the reference potential of 0 V, and then the -VPP line 65
From the reference potential of 0 V to the -VPP voltage. -VPP
The line 65 has a Zener potential of -4.0 V of the Zener diode 27 for writing shown in FIG.

When the writing is completed, the -VPP line 6
5 is returned to 0 V, and then the write program signal PG
263 is returned to 5V.

During the above-described write cycle 69, the erase program signal PG161 remains at the power supply potential of 5V.

Next, the operation of the circuit based on the above configuration will be described with reference to FIG.

When erasing the memory element, a reference potential level of 0 V is applied to the drain 17 of the first P-channel transistor 29 to which the erasing program signal PG1 is connected, and the third to which the writing program signal PG2 is connected. Drain 19 of P-channel transistor 45
Is applied with a power supply voltage of 5V. At this time, since the -VPP voltage generation circuit 15 has not been operated yet, the voltage of the -VPP line 13 is 0V.

In the erasing zener diode switching circuit block 21, a potential of 0 V is applied to the drain 17 of the first P-channel transistor 29 from the PG1 terminal, and 0 V of the reference potential line 43 is applied to the gate. , The first node 39 of the source of the first P-channel transistor 29 becomes 0V.

The second node connected to the first node 39
Of the P-channel transistor 31, the gate of the first N-channel transistor 33, and the drain of the second N-channel transistor 35 become 0V.
The channel transistor 31 is turned on, the first N-channel transistor 33 is turned off, and the drain of the second P-channel transistor 31 and the second node 41 of the drain of the first N-channel transistor 33 become 5V.

As a result, since the gate of the second N-channel transistor 35 is 5 V and the source potential is 0 V, the second N-channel transistor 35 is turned on, the first node 39 becomes 0 V, and the third N-channel transistor 35 becomes third. Since 5 V is applied to the gate and 0 V is applied to the source of the third N-channel transistor 37,
7 is turned on, and the -VPP line 13 and the erasing Zener diode 25 are connected.

The write zener diode switching circuit block 23 includes a third P-channel transistor 45.
A potential of 5 V from the PG2 terminal to the drain 19 of
0 V of the reference potential line 43 is applied to the gate. Therefore, the potential of the third node 55 of the source of the third P-channel transistor 45 becomes 5V.

The fourth node connected to the third node 55
Of the P-channel transistor 47, the gate of the fourth N-channel transistor 49, and the drain of the fifth N-channel transistor 51 become 5V,
The channel transistor 47 is turned off, the fourth N-channel transistor 49 is turned on, and the drain of the fourth P-channel transistor 47 and the fourth node 57 of the drain of the fourth N-channel transistor 49 become 0V.

As a result, the fifth N-channel transistor 51 has a gate potential of 0 V and a source potential of 0 V, so that the fifth N-channel transistor 51 is turned off, the fourth node 55 becomes 5 V, and the sixth Of the N-channel transistor 53 at the same potential as the source voltage
V is applied.

As a result, the sixth N-channel transistor 53 is turned off, and the -VPP line 13 and the write zener diode 27 are disconnected.

After the respective nodes of the erasing zener diode switching circuit block 21 and the writing zener diode switching circuit block 23 are stabilized, -VPP
The voltage generation circuit 15 is operated to set the -VPP line 13 to a negative high potential.

At this time, the operations of the erasing zener diode switching circuit block 21 and the writing zener diode switching circuit block 23 are as described below.

When the -VPP line 13 becomes a negative high potential, for example, -6 V, the source potential of the second N-channel transistor 35 connected to the -VPP line 13 is determined by the erasing Zener diode switching circuit block 21. Becomes −6 V, but since the second node 41 of the gate of the second N-channel transistor 35 is 5 V, the second N-channel transistor 35 keeps on and the first node 39 becomes It becomes -6V.

When the potential of the first node 39 becomes -6 V, the first P-channel transistor 29 is turned off, thereby preventing the negative high voltage -VPP and the drain 17 from being short-circuited.

Even if the first node 39 becomes -6V, the second P-channel transistor 31 remains on and the first N-channel transistor 33 remains off, so that the second The potential of the second node 41 maintains 5V.

The second N connected to the second node 41
Since the gate potential of the channel transistor 35 remains at 5 V and the source potential is −6 V, the second N-channel transistor 35 maintains the ON state and the second node 4
Since the potential of 1 also maintains 5 V, and the third N-channel transistor 37 maintains the ON state, the erasing Zener diode 25 remains connected to the -VPP line 13.

On the other hand, when the potential of the -VPP line 13 becomes -6 V, the write zener diode switching circuit block 23 outputs the source potential of the fifth N-channel transistor 51 connected to the -VPP line 13 and the sixth potential. Is the source potential of the N-channel transistor 53
It becomes -6V.

The fifth N-channel transistor 51 and the sixth
Of the N-channel transistor 53, the sixth N-channel transistor 53 has a larger channel length and channel width, so the fourth node 57 of the gate of the fifth N-channel transistor 51 has 0V, Before the fifth N-channel transistor 51 changes from the off-state to the on-state, the potential of the fourth node 57 at the drain of the fourth N-channel transistor 49 is changed from 0V to −6V.
Therefore, the sixth N connected to the fourth node 57
The gate potential of the channel transistor 53 becomes -6 V, and the sixth N-channel transistor 53 maintains the off state.

The potential of the fourth node 57 connecting the gate of the fifth N-channel transistor 51 is changed from 0 V to-
6V, and the source potential of the fifth N-channel transistor 51 also becomes -6V. Therefore, the fifth N-channel transistor 51 maintains the off state,
The write zener diode 27 remains disconnected from the -VPP line 13.

As described above, since the erasing Zener diode 25 is connected to the -VPP line 13 and the writing Zener diode 27 is cut off from the -VPP line 13, the potential of the -VPP line 13 becomes- 6
V is set to the Zener potential of the erasing Zener diode 25.

When writing to the memory element, a power supply voltage of 5 V is applied to the drain 17 of the first P-channel transistor 29 to which the erase program signal PG1 is connected, and the third program to which the write program signal PG2 is connected. A reference voltage of 0 V is applied to the drain 19 of the P-channel transistor 45.

At this time, the -VPP voltage generation circuit 15
Since it has not been operated yet, the voltage of the -VPP line 13 is 0V.

The erasing zener diode switching circuit block 21 applies a potential of 5 V from the PG1 terminal to the drain 17 of the first P-channel transistor 29, and 0 V of the reference potential line 43 is applied to the gate. Therefore, the potential of the first node 39 at the source of the first P-channel transistor 29 becomes 5V.

The second node connected to the first node 39
Of the P-channel transistor 31, the gate of the first N-channel transistor 33, and the drain of the second N-channel transistor 35 become 5 V, the second P-channel transistor 31 is turned off, and the first The N-channel transistor 33 is turned on, and the drain of the second P-channel transistor 31 and the first
The potential of the second node 41 of the drain of the N-channel transistor 33 becomes 0V.

As a result, the second N-channel transistor 35 has a gate potential of 0 V and a source potential of 0 V, so that the second N-channel transistor 35 is turned off, the first node 39 becomes 5 V, and the second N-channel transistor 35 becomes 5 V. Since 0 V is applied to the gate and 0 V to the source of the third N-channel transistor 37, the third N-channel transistor 3
7 is turned off, and the -VPP line 13 and the erasing zener diode 25 are disconnected.

The write zener diode switching circuit block 23 includes a third P-channel transistor 45.
0V potential is applied from the PG2 terminal to the drain 19 of
Since 0 V of the reference potential line 43 is applied to the gate, the third node 55 of the source of the third P-channel transistor 45 has 0 V.

The fourth node connected to the third node 55
Of the P-channel transistor 47, the gate of the fourth N-channel transistor 49, and the drain of the fifth N-channel transistor 51 become 0V,
The channel transistor 47 is turned on, and the fourth N
The channel transistor 49 is turned off, and the potentials of the drain of the fourth P-channel transistor 47 and the fourth node 57 of the drain of the N-type transistor 49 become 5V.

As a result, the fifth N-channel transistor 51 has a gate potential of 5 V and a source potential of 0 V, so that the fifth N-channel transistor 51 is turned on.
The voltage of the third node 55 becomes 0 V, and a potential of 5 V of the power supply voltage is applied to the gate of the sixth N-channel transistor 53.

As a result, the sixth N-channel transistor 53 is turned on, and the -VPP line 13 is connected to the write zener diode 27.

After each node of the erasing zener diode switching circuit block 21 and the writing zener diode switching circuit block 23 is stabilized, -VP
The P voltage generating circuit 15 is operated to set the -VPP line 13 to a negative high potential.

At this time, the operations of the erasing zener diode switching circuit block 21 and the writing zener diode switching circuit block 23 are as described below.

The zener diode switching circuit block 23 for writing is configured such that the -VPP line 13 has a negative high potential,
For example, when the voltage becomes −6 V, the source potential of the fifth N-channel transistor 51 connected to the −VPP line 13 becomes −6 V. The fourth node 57 of the gate of the fifth N-channel transistor 51 is Since the voltage is 5V, the fifth N-channel transistor 51 keeps on, and the potential of the third node 55 becomes -6V.

When the potential of the third node 55 becomes -6 V, the third P-channel transistor 45 is turned off to prevent the negative high voltage -VPP and the drain 19 from being short-circuited.

Even if the third node 55 becomes -6V, the fourth P-channel transistor 47 maintains the ON state, and the fourth N-channel transistor 49 maintains the OFF state. The potential of the fourth node 57 maintains 5V.

The fifth N connected to the fourth node 57
Since the gate potential of the channel transistor 51 remains at 5 V and the source potential is −6 V, the fifth N-channel transistor maintains the ON state, the potential of the fourth node 57 also maintains 5 V, and the sixth N-channel transistor maintains the ON state. Channel transistor 53
Maintains the ON state, the write zener diode 27 remains connected to the −VPP line 13.

On the other hand, the erasing zener diode switching circuit block 21 has the potential of the -VPP line 13 of -6.
When the voltage becomes V, the source potential of the second N-channel transistor 35 and the source potential of the third N-channel transistor 37 connected to the -VPP line 13 become -6V.

The second N-channel transistor 35 and the third
Since the third N-channel transistor 37 has a larger channel length and a larger channel width than the N-channel transistor 37, the second node 41 of the gate of the second N-channel transistor 35 is at 0V. Before the second N-channel transistor 35 changes from the off-state to the on-state, the potential of the second node 41 at the drain of the first N-channel transistor 33 goes from 0V to -6V.
Therefore, the gate potential of the third N-channel transistor 37 connected to this second node becomes -6 V, and the third N-channel transistor 37 maintains the off state.

The potential of the second node 41 connecting the gate of the second N-channel transistor 35 is changed from 0 V to-
6V, and the source potential of the second N-channel transistor 35 also becomes -6V. Therefore, the second N-channel transistor 35 maintains the off state,
The erasing Zener diode 25 remains disconnected from the -VPP line 13.

As described above, since the write zener diode 27 is connected to the -VPP line 13 and the erase zener diode 25 is cut off from the -VPP line 13, the potential of the -VPP line 13 becomes -6V
Is set to the Zener potential of the Zener diode 27 for writing.

[0083]

As described above, according to the present invention, the -VPP voltage value of the erasing voltage of the memory and the -VPP voltage value of the writing voltage of the memory can be set to different optimal values, respectively. A semiconductor nonvolatile memory device that is frequently used can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a switching circuit of a semiconductor nonvolatile memory device according to the present invention.

FIG. 2 is a waveform chart showing operation timing of a switching circuit of the semiconductor nonvolatile memory device of the present invention.

FIG. 3 is a circuit diagram illustrating a method of erasing and writing a memory element constituting a semiconductor nonvolatile memory device.

FIG. 4 shows an erasing operation in a conventional semiconductor nonvolatile memory device;
FIG. 3 is a circuit diagram illustrating a write voltage setting circuit.

FIG. 5 shows an erase Vt of a memory element according to the present invention and a conventional example.
7 is a graph showing the relationship between h, write Vth, and the number of rewrites.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Power supply voltage line 13 -VPP line 15 Negative high voltage generating circuit 17 Drain 19 Drain 21 Zener diode switching circuit block for erasing 23 Zener diode switching circuit block for writing 25 Zener diode for erasing 27 Zener diode for writing

Claims (2)

(57) [Claims] 1. A nonvolatile semiconductor memory device comprising an erasing Zener diode, a writing Zener diode, an erasing Zener diode switching circuit block, a writing Zener diode switching circuit block, and a negative high voltage generating circuit. At the start of the erase operation , the erase
Voltage of Zener diode switching circuit block for
From the negative high voltage generating circuit,
At the end of the erasing operation, the negative high voltage is generated by the negative high voltage generating circuit.
After the generation of the voltage is completed, the
Erasing zener diode switching circuit block
Input voltage is returned to the original voltage .
The write zener diode switching circuit block
The negative high-voltage generating circuit after changing the input voltage of the
When a write operation is completed , a negative high voltage is generated by the negative high voltage generation circuit.
After the generation of the high voltage is terminated,
Switch the Zener diode for writing with a system signal
A semiconductor nonvolatile memory device, wherein an input potential of a circuit block is returned to an original voltage . 2. A method for erasing a semiconductor nonvolatile memory device having an erasing Zener diode, a writing Zener diode, an erasing Zener diode switching circuit block, a writing Zener diode switching circuit block, and a negative high voltage generating circuit. In the writing method, at the start of the erasing operation, a negative high voltage is generated from the negative high voltage generating circuit after changing the input voltage of the erasing zener diode switching circuit block with an erasing program signal, At the end of the erasing operation, after the generation of the negative high voltage from the negative high voltage generating circuit is completed, the input voltage of the erasing zener diode switching circuit block is returned to the original voltage by the erasing program signal, At the start of the write operation, the write zener die is A negative high voltage is generated from the negative high voltage generation circuit after changing the input voltage of the ode switching circuit block, and when the write operation is completed, the generation of the negative high voltage is terminated by the negative high voltage generation circuit. And then returning the input potential of the write zener diode switching circuit block to the original voltage by the write program signal.