JP3315430B2 - Pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator for generating a desired number of pulses at equal intervals during a predetermined time, and more particularly to a clock control for maintaining the same signal as a clock immediately before the supply of a reference clock is interrupted. The present invention relates to a pulse generator used for a device.

A network synchronizing device is required for a network synchronizing system in which clocks of the same frequency are supplied to digital exchanges and synchronous terminal devices of a transmission network to exchange time slots, set up lines, demultiplex, and the like. . The network synchronizer synchronizes a signal from a highly stable oscillator placed in its own station with a reference clock from an upper station by using a phase-locked loop (PLL), and converts a stable clock into various stations in the station. It is a device that distributes to devices. In particular, in a network synchronizer to which a digital PLL is applied, a phase comparison result between an input frequency and an output frequency is digitized, phase difference data for several seconds is averaged, and only an extremely low frequency phase fluctuation is detected to obtain an oscillation frequency. Is controlling. As a result, the cutoff frequency of the jitter can be lowered, and the result of the phase comparison is once converted to a digital value, so that this value can be stored in the memory. With this storage function, even if the reference clock is not supplied from the upper station, a stable clock for several days can be supplied to each device in the station and the lower station.

[0003]

2. Description of the Related Art Conventionally, in a network synchronizer to which such a digital PLL is applied, when the supply of a reference clock from an upper station is interrupted, the network synchronizer is prepared in advance in accordance with the digitized phase comparison result immediately before the interruption. A suitable pulse pattern is selected from the plurality of pulse patterns, and the selected pulse pattern is added to or removed from the fixed oscillator output pulse of the PLL, whereby the reference clock Even if the supply was interrupted, the same clock as the clock immediately before the interruption was maintained.

[0004]

However, in order to generate a clock that exactly matches the reference clock before the interruption, it is necessary to prepare many types of pulse patterns.
There is a problem that the circuit scale of the device increases as the number of types of pulse patterns increases.

The present invention has been made in view of the above points, and has as its object to provide a pulse generator that outputs a desired number of pulses at regular intervals within a predetermined time without increasing the circuit scale. And

[0006]

According to the present invention, in order to achieve the above object, a pulse generator for generating a desired number of pulses at equal intervals during a first predetermined time as shown in FIG. Is provided. The pulse generating device measures a second predetermined time shorter than the first predetermined time, and outputs a termination signal each time the measurement is completed, and the desired number is set. A pulse generating means for generating the desired number of pulses each time the end signal is input, and a quotient obtained by dividing a pulse generated from the pulse generating means by a first predetermined time by a second predetermined time. And frequency dividing means 3 for dividing the frequency by the value of

[0007]

With the above arrangement, in FIG. 1, the pulse generating means 2 generates the desired number of pulses at every second predetermined time during a first predetermined time. That is, assuming that the desired number is m and the quotient obtained by dividing the first predetermined time by the second predetermined time is n, the pulse generation means 2 outputs
M × n pulses are generated during the predetermined time. The frequency dividing means 3 divides the m × n number of pulses by n (the pulse frequency is reduced to 1 / n).
Is output every n pulses. Therefore, a desired number m of pulses are output at equal intervals from the frequency dividing means 3 during the first predetermined time.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a configuration of the rate multiplier according to the embodiment of the present invention. Rate multiplier 20 is a pulse generator for generating at equal intervals a pulse of desired number m in the predetermined time T _1, firstly, the down counter 21, the number of pulses to be generated in a predetermined time T ₁ m Are input in parallel. In the down counter 21, a timer 22 is connected to a LOAD terminal, and a clock signal (CLK) is input to the CLK terminal.

[0009] Also inputted clock signal (CLK) is in the timer 22, the timer 22 performs counting by counting the number of clock signals, the pulse T every ₂ hours is an integer fraction of the first predetermined time T ₁ Rising of the down counter 21
Output to OAD terminal.

Each time a rising edge of a pulse is input from the timer 22, the down counter 21 loads a desired number m to the count value, and then decrements the count value for each clock signal input thereafter. When the count value reaches 0, the value is held until the next load. Then, the down counter 21 outputs a pulse (borrowout output) to the OR circuit 23 which falls at the rising timing of the pulse from the timer 22 and rises at the timing when the count value of the down counter 21 reaches 0.

A clock signal (CLK) is input to another input terminal of the OR circuit 23, and the down counter 21
While the borrow-out output from is low, the clock signal is output to divider 24. The frequency divider 24 divides the output pulse from the OR circuit 23 by n (n = T ₁ / T ₂ ) (the pulse frequency is set to 1 / n) and outputs the result.

FIG. 3 and FIG. 4 are timing charts showing signal forms in each section of the rate multiplier 20 configured as described above. 3A shows a clock signal (CLK), (B) shows an output of the timer 22, (C) shows a count value of the down counter 21,
(D) shows the output of the down counter 21 and (E) shows the output of the OR circuit 23.

That is, the timer 22 is operated, for example, at every rising of 11 clock pulses (corresponding to the lapse of time T ₂ )
(B). A desired number m (for example, 3) is loaded into the down counter 21 at the rising timing of the output of the timer 22, and the loaded count value is decremented every subsequent rising of the clock signal (C). The output of the down counter 21 falls at the rising timing of the output pulse of the timer 22, and rises at the timing when the count value of the down counter 21 reaches 0 (D). From the OR circuit 23 outputs the (D) inputs of the clock signal (A) and down-counter 21, a pulse of a desired number m is generated every T ₂ hours (E).

FIG. 4 (F) corresponds to FIG. 3 (B) and shows the output of the timer 22, and FIG. 4 (G) corresponds to FIG. 3 (E) and shows the output of the OR circuit 23. FIG. 4 (H)
4 shows the output of the frequency divider 24.

That is, n of the predetermined time T ₁ (for example, 8)
Minute output of the timer 22 every T ₂ hours 1 rises (F), from the OR circuit 23, the pulse of the desired number m for each T ₂ hours (e.g., 3) (falling) is generated (G ). The frequency divider 24 outputs a pulse every n (for example, 8) out of the pulses input from the OR circuit 23 (H). Therefore, the output of the frequency divider 24 is equal to the predetermined time T
A desired number m of pulses generated at intervals equal to _one are obtained.

As described above, the rate multiplier 20
Is the frequency 1 / T ₁ by appropriately selecting several m.
, A pulse signal of any frequency from the frequency of the clock signal to the frequency of the clock signal can be generated.

FIG. 5 is a block diagram showing a frequency control device using the rate multiplier 20. This frequency control device constitutes a part of a network synchronization device to which a digital PLL is applied. In the figure, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.

The frequency control unit 51 is a digital PLL.
Based on the result of phase comparison, the detected number of several or extra pulses of pulses missing during a predetermined period of time T _1. That is, the frequency control unit 51 sends a polarity signal indicating whether the pulse is insufficient or the pulse excess to the clock control unit 52,
Further, the number of insufficient pulses or the number of remaining pulses is sent to the down counter 21 of the rate multiplier 20 as a load value. Rate multiplier 20, as already described, it outputs a pulse of the load value min at equal intervals during the predetermined time T _1, and sends to the clock control unit 52.

The fixed oscillator 53 corresponds to the oscillator in the digital PLL, generates the clock signal (CLK) shown in FIG. 2 and supplies it to each part of the rate multiplier 20, and also controls the clock controller 52. Also supply.

The clock control unit 52 adds an output pulse from the rate multiplier 20 to the clock signal from the fixed oscillator 53 based on the polarity signal from the frequency control unit 51 (clock increase), or Remove (clock missing) and output.

The clock signal output from the clock control unit 52 becomes a clock signal synchronized with the reference clock input to the PLL, and since the phase comparison result is a digital value, the clock signal can be held. Even if the supply of the clock is cut off, the clock state immediately before the cutoff can be stably maintained.

[0022]

As described above, according to the present invention, a predetermined number of pulses are generated at every second predetermined time, and the pulses are divided, whereby a desired number of pulses are generated within the first predetermined time. Can be generated at equal intervals. In addition, the circuit scale of the device does not increase even if the desired number is within a predetermined range.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a rate multiplier.

FIG. 3 is a timing chart showing a signal form in each section of the rate multiplier.

FIG. 4 is a timing chart showing a signal form in each section of the rate multiplier.

FIG. 5 is a block diagram illustrating a frequency control device.

[Explanation of symbols]

 1 time measuring means 2 pulse generating means 3 frequency dividing means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 3/72 H04L 7/00 H03L 7/00

Claims (3)

(57) [Claims] 1. A pulse generator for generating a desired number of pulses at equal intervals during a first predetermined time, wherein a second predetermined time shorter than the first predetermined time is measured, and the time measurement ends. Timing means for outputting an end signal every time (1)
A pulse generating means (2) for setting the desired number and generating the desired number of pulses each time an end signal is input from the timing means (1); And a frequency dividing means (3) for dividing the divided pulse by a value of a quotient obtained by dividing the first predetermined time by the second predetermined time. 2. The apparatus according to claim 1, further comprising clock generation means for generating a clock pulse having a predetermined frequency, wherein said pulse generation means comprises a down counter and an OR circuit to which said clock generation means is connected. The desired number is set for each input of the end signal from the clocking means (1), and a low-level signal is supplied to the OR circuit while the desired number of clock pulses from the clock generating means are input. The pulse generator according to claim 1, wherein the pulse generator is configured to output the pulse. 3. The pulse generating means (2) sets data obtained by converting a phase comparison result into a digital value output from a digital PLL as the desired number, and outputs the data from the frequency dividing means (3). 2. The pulse generator according to claim 1, wherein the pulse generator is configured to be used for frequency control of an output pulse of the digital PLL.