JP3317032B2 - Inspection method of multilayer varistor - Google Patents
Inspection method of multilayer varistorInfo
- Publication number
- JP3317032B2 JP3317032B2 JP17084994A JP17084994A JP3317032B2 JP 3317032 B2 JP3317032 B2 JP 3317032B2 JP 17084994 A JP17084994 A JP 17084994A JP 17084994 A JP17084994 A JP 17084994A JP 3317032 B2 JP3317032 B2 JP 3317032B2
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- laminated
- cut out
- exposed
- internal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Thermistors And Varistors (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、積層バリスタの検査方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a laminated varistor.
【０００２】[0002]
【従来の技術】積層バリスタは、多数の内部電極を上下
バリスタ有効層を介して積層されたものである。2. Description of the Related Art A laminated varistor is formed by laminating a large number of internal electrodes via upper and lower varistor effective layers.
【０００３】[0003]
【発明が解決しようとする課題】このような積層バリス
タにおいては、積層された多数の内部電極中に、例え
ば、他の部分よりも層間距離の薄いものがあると、この
部分に集中的にバリスタ効果が生じ、その結果として過
大電流により焼損が生じてしまう。In such a multilayer varistor, if, for example, one of a large number of laminated internal electrodes has a thinner interlayer distance than other portions, the varistor is concentrated on this portion. The effect occurs, and as a result, burnout occurs due to an excessive current.
【０００４】そこで、本発明は、このような局部的な電
流集中による焼損を未然に防止することを目的とするも
のである。Accordingly, an object of the present invention is to prevent such burning due to local current concentration.
【０００５】[0005]
【課題を解決するための手段】そしてこの目的を達成す
るために本発明は、積層バリスタの外周側面の少なくと
も一部を切欠して、内部電極をこの切欠部に表出させ、
この表出部における上下の内部電極に端子を当接させて
電圧を印加するものである。Means for Solving the Problems In order to achieve this object, the present invention is to cut out at least a part of the outer peripheral side surface of the laminated varistor and expose the internal electrode to this notched portion.
The voltage is applied by bringing the terminals into contact with the upper and lower internal electrodes in the exposed portion.
【０００６】[0006]
【作用】以上の方法によれば、各内部電極間のバリスタ
特性を測定するので、局部的に電流集中を生じるものを
排除することができ、しかもこの時、積層バリスタの一
部が切欠され、そこに表出した内部電極に端子を当接さ
せるものであるので、端子と内部電極を容易に当接させ
ることができ作業性が良いものである。According to the above-mentioned method, since the varistor characteristics between the internal electrodes are measured, it is possible to eliminate a local current concentration, and at this time, a part of the laminated varistor is cut off. Since the terminal is brought into contact with the exposed internal electrode, the terminal and the internal electrode can be easily brought into contact with each other, and the workability is good.
【０００７】[0007]
【実施例】図１において、１は積層バリスタ素子で、そ
の内部には複数の内部電極２が設けられ、その両端には
外部電極３が設けられている。積層バリスタ素子１は、
ＳｒＴｉＯ3を主成分とし、副成分としてＮｂ2Ｏ5，Ｔ
ａ2Ｏ5，ＳｉＯ2，ＭｎＯ2などを添加して形成したもの
である。また、内部電極２はＮｉを主成分とし、副成分
としてＬｉ2ＣＯ3などを添加して形成したものである。
さらに外部電極３は、下層３ａがＮｉを主成分とし、副
成分としてＬｉ2ＣＯ3などを添加して形成され、上層３
ｂがＡｇで形成されたものである。以上の構成におい
て、積層バリスタの各層間のバリスタ電圧の測定を行う
には、図２に示すように、積層バリスタをエポキシ系の
試料埋込み樹脂でモールド４し、次に図３に示すごと
く、外部電極３を研磨機により切欠する。次に、その前
方側の左右角部を上下方向に切欠する。その時の角部は
３０〜６０°で切欠する。このように切欠すると、図４
に示すごとく切欠部１Ａに内部電極２が表出することに
なる。従って、この状態で、上下の内部電極２に、先の
細いピン５を当接させて電流を印加し、各層間のバリス
タ特性を測定する。In FIG. 1, reference numeral 1 denotes a laminated varistor element, in which a plurality of internal electrodes 2 are provided, and external electrodes 3 are provided at both ends thereof. The laminated varistor element 1
SrTiO 3 as a main component, and Nb 2 O 5 , T as a sub-component
a 2 O 5, SiO 2, is obtained by forming the like is added MnO 2. The internal electrode 2 is formed by using Ni as a main component and adding Li 2 CO 3 or the like as a sub-component.
Further, the external electrode 3 is formed such that the lower layer 3a contains Ni as a main component and Li 2 CO 3 or the like as an auxiliary component.
b is formed of Ag. In the above configuration, in order to measure the varistor voltage between the layers of the multilayer varistor, the multilayer varistor is molded 4 with an epoxy-based sample embedding resin as shown in FIG. The electrode 3 is cut out by a polishing machine. Next, the left and right corners on the front side are cut out in the vertical direction. The corner at that time is cut off at 30 to 60 °. When the notch is cut in this way, FIG.
The internal electrode 2 is exposed in the cutout 1A as shown in FIG. Accordingly, in this state, a current is applied by bringing the thin pin 5 into contact with the upper and lower internal electrodes 2, and the varistor characteristics between the respective layers are measured.
【０００８】この場合、良品は各層間のバリスタ特性
が、ほぼ一定になる。しかし、層間の厚みの変化、有効
層のバリスタ特性の変成などがある場合には、各層間の
バリスタ特性がばらつく。従って、それらのものは不良
品として排除するので、市場において局部的な電流集中
による焼損を未然に防止することができる。In this case, the varistor characteristics between the layers of the non-defective product become almost constant. However, when there is a change in the thickness between the layers and a change in the varistor characteristics of the effective layer, the varistor characteristics between the respective layers vary. Therefore, since those are excluded as defective products, burning due to local current concentration in the market can be prevented.
【０００９】なお、以上のような検査はロット毎に５〜
２０個を選出して行うものである。即ち、上記電流の局
部集中が発生する原因は、その製造条件によって決まる
ことが多く、この製造条件はロット毎に一定となってい
るので、上述のごとくロット毎に５〜２０個を選出して
検査を行えば、実質的にそのロットの全個数を検査した
ことになるのである。つまり検査したものが不良品であ
れば、そのロット全品を不良品、逆に検査したものが良
品であれば、そのロット全品を良品と判断することがで
きるのである。[0009] The above inspection is performed for each lot.
This is done by selecting 20 pieces. That is, the cause of the local concentration of the current is often determined by the manufacturing conditions, and since the manufacturing conditions are constant for each lot, 5 to 20 pieces are selected for each lot as described above. When the inspection is performed, the entire number of the lot is substantially inspected. In other words, if the inspected product is defective, all the lots can be determined to be defective. Conversely, if the inspected product is good, all the lots can be determined to be good.
【００１０】[0010]
【発明の効果】以上のごとく本発明は、積層バリスタの
外周側面の少なくとも一部を切欠して、内部電極をこの
切欠部に表出させ、この表出部における上下の内部電極
に端子を当接させて電圧を印加するものである。As described above, according to the present invention, at least a part of the outer peripheral side surface of the laminated varistor is cut out, the internal electrodes are exposed in the cutout portions, and terminals are applied to the upper and lower internal electrodes in the exposed portions. A voltage is applied by making contact.
【００１１】以上の方法によれば、各内部電極間のバリ
スタ特性を測定するので、局部的に電流集中を生じるも
のを排除することができ、しかもこの時、積層バリスタ
の一部が切欠され、そこに表出した内部電極に端子を当
接させるものであるので、端子と内部電極を容易に当接
させることができ作業性が良い。According to the method described above, since the varistor characteristics between the internal electrodes are measured, it is possible to eliminate a local current concentration, and at this time, a part of the laminated varistor is cut off. Since the terminal is brought into contact with the exposed internal electrode, the terminal and the internal electrode can be easily brought into contact with each other, and workability is good.
【図１】本発明の一実施例を示す断面図FIG. 1 is a sectional view showing one embodiment of the present invention.
【図２】積層バリスタを埋込み樹脂にモールドした断面
図FIG. 2 is a cross-sectional view in which a laminated varistor is molded into an embedded resin.
【図３】モールドした積層バリスタの外部電極を切欠し
た断面図FIG. 3 is a cross-sectional view of a molded multilayer varistor with external electrodes cut away.
【図４】その前方側の左右角部を上下方向に切欠した斜
視図FIG. 4 is a perspective view in which left and right corners on the front side are cut out in a vertical direction.
１ バリスタ素子 １Ａ 切欠部 ２ 内部電極 ３ 外部電極 DESCRIPTION OF SYMBOLS 1 Varistor element 1A Notch 2 Internal electrode 3 External electrode
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−107291（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) G01R 31/26 G01R 27/00 - 27/32 H01C 7/02 - 7/22 H01C 7/10 ────────────────────────────────────────────────── (5) References JP-A-5-107291 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) G01R 31/26 G01R 27/00-27 / 32 H01C 7/02-7/22 H01C 7/10
Claims (4)
部を切欠して、内部電極をこの切欠部に表出させ、この
表出部における上下の内部電極に端子を当接させて電圧
を印加する積層バリスタの検査方法。At least a portion of an outer peripheral side surface of a laminated varistor is cut out, an internal electrode is exposed in the cutout portion, and a terminal is brought into contact with upper and lower internal electrodes in the exposed portion to apply a voltage. Inspection method for laminated varistors.
方に向けて切欠し、この切欠部において内部電極を表出
させる請求項１記載の積層バリスタの検査方法。2. The method for inspecting a laminated varistor according to claim 1, wherein a corner of the rectangular varistor element is cut out from above to below, and the internal electrode is exposed in the cut out.
を上方より下方に向けて切欠し、この切欠部において内
部電極を表出させる請求項１または２記載の積層バリス
タの検査方法。3. The method for inspecting a laminated varistor according to claim 1, wherein the left and right corners of the rectangular varistor element are cut out downward from above, and the internal electrode is exposed in the notch.
この積層バリスタの外周側面の少なくとも一部を切欠し
て、内部電極をこの切欠部に表出させ、この表出部にお
ける上下の内部電極に端子を当接させて電圧を印加する
請求項１から３のいずれか一つに記載の積層バリスタの
検査方法。4. The laminated varistor is resin-molded, and then at least a part of the outer peripheral side surface of the laminated varistor is cut out to expose the internal electrodes to the cutouts. 4. The method for inspecting a laminated varistor according to claim 1, wherein a voltage is applied by bringing the varistor into contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17084994A JP3317032B2 (en) | 1994-07-22 | 1994-07-22 | Inspection method of multilayer varistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17084994A JP3317032B2 (en) | 1994-07-22 | 1994-07-22 | Inspection method of multilayer varistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0836021A JPH0836021A (en) | 1996-02-06 |
| JP3317032B2 true JP3317032B2 (en) | 2002-08-19 |
Family
ID=15912469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17084994A Expired - Fee Related JP3317032B2 (en) | 1994-07-22 | 1994-07-22 | Inspection method of multilayer varistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3317032B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8875312B2 (en) | 2005-10-18 | 2014-11-04 | Supreme Elastic Corporation | Modular cut and abrasion resistant protective garment and protective garment system |
-
1994
- 1994-07-22 JP JP17084994A patent/JP3317032B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0836021A (en) | 1996-02-06 |
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