JP3317207B2 - Dither circuit for digital video signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a dither circuit for digital video signals, in particular, relates to a dither circuit suitable digital video signal using the high-definition digital video signal processing.

[0002]

2. Description of the Related Art In digital processing of a video signal, the number of sampling bits of the video signal is sometimes increased in order to widen a dynamic range. It was difficult to apply as a video interface.

In order to reduce the transmission cost, it is only necessary to reduce the number of bits. However, this causes a reduction in the S / N ratio. In particular, in the case of a video signal whose luminance changes gently, it is sensitive to the eyes of the observer. The low-frequency noise that is perceived by the user appears remarkably.

To reduce the number of bits as described above, a technique of performing dither processing to suppress the deterioration of the S / N ratio is conventionally known. For example, in the system disclosed in Japanese Patent Application Laid-Open No. 7-162710 shown in FIG. 4, the lower two bits of an input 10-bit digital video signal are truncated, and an adder is added together with a dither signal generated by a dither signal generator 100. Enter 200.
The adder 200 adds the dither signal to the least significant 8 bits of the digital video signal and outputs the result, and the D / A converter 300 converts the output signal into an analog signal and outputs it.

[0005]

The above-mentioned conventional digital video signal dither circuit has the following problems. For example, the sampling frequency of a luminance signal in high definition digital video is a high frequency of 74.25 MHz, and it has been difficult to configure a circuit with TTL logic. Therefore, a dedicated circuit using ECL logic or the like is required, so that the circuit has to be expensive.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a digital video signal dither circuit and a digital video signal dither processing method capable of performing digital video signal dither processing with an inexpensive circuit configuration. With the goal.

[0007]

In order to achieve the above object, according to the present invention, there is provided a separation circuit for separating a digitally processed luminance signal into two signals by time division, and for each of the two signals. In a digital video signal dither circuit including two dither circuits for dither processing and a time axis multiplexing circuit for time axis multiplexing the two signals subjected to the dither processing, the dither circuit converts a pseudo random signal synchronized with a horizontal cycle. A first pseudo-random signal generator,
A second pseudo-random signal generator that generates a pseudo-random signal synchronized with a clock signal, and a pseudo-random signal generated by the first and second pseudo-random signal generators are input and several types of dither signals are output. Logic gates
When rounding the lower bits of the luminance signal, a selector is provided for selecting and outputting one of the several types of dither signals in accordance with the output of the lower bits.

According to a second aspect of the present invention, the logic gate group comprises an OR gate and an AND gate ,
%, 25%, 50%, 75%, and generates a pseudo-random signal at a high level, wherein the selector responds to the select signal from a decoder that generates a different select signal according to the output of the lower bit. 0%, 25%,
The configuration is such that one pseudo random signal is selected from the pseudo random signals that are at a high level at 50% and 75% and output.

The separation circuit is a digitally processed luminance signal.
Is time-divided into two signals with reduced frequency,
Separate dither circuits perform dither processing on the signals. This
If the frequency of the luminance signal is reduced as in
The circuit can be configured at low cost. Time axis multiplexing circuit
Is the time axis of the signal dithered by each dither circuit.
The signal is multiplexed into a luminance signal of the original frequency.

Here, the above-mentioned dither signal is, for example,
For example, a rectangle containing a high level and a low level in a predetermined ratio
Any shape signal can be used.
The method is various and is not particularly limited.

Each dither circuit performs dither processing based on a dither signal obtained by synthesizing a pseudo random signal synchronized with a horizontal synchronizing signal and a pseudo random signal synchronized with a clock signal. For example, if two pseudo-random signals each containing a high level and a low level at a rate of 50% are input to an OR gate, a dither signal having a high level at an average rate of 75% can be obtained. If both pseudo-random signals are input to an AND gate, on average 25
A dither signal which becomes high level at the rate of% is obtained.

[0012]

The dither circuit includes first and second pseudo-random signal generators, and generates a pseudo-random signal synchronized with a horizontal period and a pseudo-random signal synchronized with a clock signal. Both pseudo-random signals are input to a group of logic gates, and several types of dither signals are generated and output. When rounding the lower bits of the luminance signal, the selector selectively outputs several types of dither signals according to the output of the lower bits.

[0014]

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a digital video signal dither circuit according to an embodiment of the present invention. In FIG. 1, a DMPX 10 receives a digital video luminance signal Y, time-divides it into two signals consisting of a Y0 signal and a Y1 signal, and outputs it to a dither circuit 20. The dither circuit 20 includes a Y0 signal dither processing circuit 30.
And a dither processing circuit 40 for the Y1 signal, performs predetermined dither processing on the Y0 signal and the Y1 signal as described later, and outputs the Y0 ′ signal and the Y1 ′ signal.

FIG. 2 shows the dither circuit 20 in a schematic circuit diagram. In the figure, the Y0 signal dither processing circuit 30 and the Y1 signal dither processing circuit 40 have substantially the same circuit configuration. Hereinafter, the Y0 signal dither processing circuit 30 will be described. The Y0 signal input in a time-division manner as described above is a 10-bit digital video luminance signal, which is input to the sync separation circuit 31, and the lower 2 bits are truncated and the upper 8 bits are added as described later. Is input to the device 38.

The synchronizing separation circuit 31 detects a vertical synchronizing signal and a horizontal synchronizing signal from the input Y0 signal, generates a blanking signal (BLK) signal other than the video portion by using both signals, and outputs an AND gate 37 described later. Output to further,
The sync separation circuit 31 generates an H signal including one pulse in one line of the video signal from the horizontal sync signal and inputs the H signal to the pseudo random signal generator 33.

On the other hand, the lower 2 bits of the truncated Y0 signal are input to the 2to4 decoder 32.
The 2to4 decoder 32 outputs four types of select signals having different output levels according to a combination of bit arrangements with respect to 2-bit input binary data.
The output of the 2to4 decoder 32 is supplied to a selector 3 described later.
6 is input.

The Y0 signal dither processing circuit 30 includes two pseudo-random signal generators 33 and 34. The H signal is input to the pseudo-random signal generator 33. On the other hand, the pseudo-random signal generator 34 Is supplied with a clock signal (１ ／ CLK) obtained by dividing the sampling clock of the digital video luminance signal Y by half. Of course, this clock signal (１ ／ CLK) has the same frequency as the sampling clock of the time-divided Y0 signal and Y1 signal. Pseudo random signal generators 33 and 34
Are the H signal and the clock signal (（CL), respectively.
A pseudo random signal having an amplitude of one bit, which changes in each cycle of K) and includes a high level and a low level at 50% each, is output.

The output of the pseudo random signal generator 33 is O
R gate 35a, AND gate 35b, selector 3
6 and the output of the pseudo-random signal generator 34 is O
It is input to an R gate 35a and an AND gate 35b. Accordingly, the OR gate 35a outputs a pseudo-random signal that becomes high level at a rate of 75% when averaged.
The ND gate 35b similarly outputs a pseudo-random signal that goes high at a rate of 25%, and both outputs are input to the selector 36.

As described above, the output of the OR gate 35a, the pseudo-random signal generator 33, and the output of the AND gate 35b are input to the selector 36.
%, 50%, and 75%, which are high-level pseudo-random signals having one-bit amplitude. Further, a signal fixed at a high level of 0%, that is, a low level is input to the selector 36,
In addition, one signal is selectively output from the four types of signals. Specifically, as described above, the selector 36 is supplied with the select signal from the 2to4 decoder 32, selects one of the four types of signals according to the select signal, and generates a 1-bit dither signal. Output.

The above-mentioned blanking signal (BLK),
The output dither signal of the selector 36 is input to the AND gate 37, and is gated only during the active video period other than the horizontal and vertical synchronization periods, and the output dither signal is added to the adder 38.
Is input to As described above, the upper 8 bits of the Y0 signal are input to the adder 38, and the AND gate 37
Is added as an offset value to the least significant bit of the upper 8 bits of the Y0 signal, and the Y0 'signal is output.

The pseudo random signal output from the pseudo random signal generator 33 is inverted by an inverter circuit 39 and input to an OR gate 45a, a selector 46, and an AND gate 45b in the Y1 signal dither processing circuit 40. And 25%, 50%, as described above.
A pseudo random signal which becomes high level at a rate of 75% is generated. The selector 46 selects and outputs one of the four types of input signals as a dither signal in accordance with the select signal from the 2to4 decoder 42, and outputs the dither signal to the adder 4
8, the upper 8 bits of the Y1 signal during the active video period.
An offset is added to the least significant bit of the bit, and a Y1 ′ signal is output.

The Y0 'signal thus output and Y
The 1 ′ signal is time-multiplexed in the MPX 50 and Y ′
A signal is generated and output, and the Y 'signal is converted into an analog signal by the D / A converter 60 to obtain an analog video luminance signal. Here, the signal output at each stage will be considered while exemplifying a specific signal waveform. For example, when the luminance of the digital video luminance signal Y changes gradually as shown in FIG. 3A, the waveform shown in FIG. In the figure, Δ is
This represents a quantization step. If the signal shown in FIG. 3B is directly D / A converted and output as a monitor, extremely unpleasant quantization noise will be observed because the quantization step Δ is large.

To reduce the quantization noise, dither processing may be performed.
However, in order to perform dither processing on the data, the circuit configuration must be complicated. For example, the digital video luminance signal for high vision has a sampling frequency of 74.25 MHz.
In order to perform the dither processing as it is, it is necessary to use a peripheral circuit having precise frequency characteristics.

Therefore, as described above, the digital video luminance signal Y is time-divisionally divided into the Y0 signal and the Y1 signal using the DMPX 10, and the lower two bits of each signal are truncated. 36,
46 outputs a dither signal. An example of each signal waveform at this time is shown in FIGS. 3C and 3D.

The MPX 50 has an 8 to which a dither signal is added.
The bit Y0 'signal and the Y1' signal are time-division multiplexed to output the Y 'signal shown in FIG. put it here,
While the pseudo random signal output from the pseudo random signal generator 33 is inverted by the inverter circuit 39,
Since the Y1 signal dither processing circuit 40 generates a dither signal from the inverted pseudo random signal and the pseudo random signal having a clock signal (１ ／ CLK) cycle,
As shown in FIG. 3E, the Y 'signal has a waveform in which a high level and a low level are repeated.

Further, since the frequency component of the dither signal included in the Y 'signal is concentrated to one half of the sampling frequency, the analog signal is converted into an analog signal by the D / A converter 60 and then passed through a low-pass filter. The frequency components are averaged to form a waveform as shown in FIG. As can be seen from the figure, the waveform changes in level with a quantization step width of 1 / 2Δ, and the level change point also changes randomly, so that the quantization noise is not noticeable in the monitor output.

Next, the operation of this embodiment configured as described above will be described. The DMPX 10 receives the digital video luminance signal Y, time-divides it into two signals, a Y0 signal and a Y1 signal, and respectively performs a dither processing circuit 30 for the Y0 signal.
Is input to the Y1 signal dither processing circuit 40. When the Y0 signal is input to the Y0 signal dither processing circuit 30, the synchronization separation circuit 31 detects a vertical synchronization signal and a horizontal synchronization signal from the Y0 signal and outputs a blanking signal (B
LK) and outputs the same to the AND gate 37, generates an H signal from the horizontal synchronization signal, and inputs the H signal to the pseudo-random signal generator 33.

The pseudo-random signal generators 33 and 34 change the sampling frequency of the H signal and the digital video luminance signal Y at a cycle of a clock signal (１ ／ CLK) obtained by dividing the sampling frequency by half, and at a rate of 50%. And outputs a pseudo-random signal that goes high at the rate of
The pseudo-random signal output from each of the pseudo-random signal generators 33 and 34 is 25%, 50% by appropriately passing through an OR gate 35a and an AND gate 35b.
The signal is converted to a high-level pseudo-random signal at a rate of 75%, and is input to the selector 36.

On the other hand, the lower two bits of the Y0 signal are truncated and the upper eight bits are input to the adder 38, and the lower two bits are input to the 2to4 decoder 32. The 2to4 decoder 32 generates select signals having different output levels in accordance with the input 2-bit data and inputs the select signals to the selector 36. The selector 36 determines 0%, 25% according to the select signal.
One pseudorandom signal is selected from the pseudorandom signals that become high level at a rate of%, 50%, and 75%, and is input to the AND gate 37 as a dither signal.

The AND gate 37 has a synchronization separation circuit 31
, And the dither signal output from the selector 36 is input to the adder 38 only during the active video period. The adder 38 offset-adds the dither signal input from the AND gate 37 to the least significant 8 bits of the upper 8 bits of the Y0 signal input as described above, and outputs a Y0 ′ signal.

On the other hand, the same processing is performed in the Y1 signal dither processing circuit 40. However, the output of the pseudo random signal generator 33 on the Y0 signal dither processing circuit 30 side is inverted by the inverter circuit 39, and the inverted pseudo dither processing is performed. The random signal and the pseudo-random signal having the cycle of the clock signal (１ ／ CLK) output from the pseudo-random signal generator 44 are appropriately passed through an OR gate 45a and an AND gate 45b to obtain 25%, 50%, The selector 4 converts the signal into a pseudo random signal which becomes a high level at a rate of 75%.
6 is entered.

Then, similarly to the Y0 signal dither processing circuit 30, the dither signal is offset-added to the least significant 8 bits of the Y1 signal to output the Y1 'signal. The output Y0 ′ signal and Y1 ′ signal are MPX5
The signal is input to 0, time-division multiplexed and output as a Y 'signal, and the Y' signal is converted into an analog signal in the D / A converter 60 to generate an analog video luminance signal.

As described above, the digital video luminance signal Y is input to the DMPX 10 and is time-divided into the Y0 signal and the Y1 signal.
And the Y1 ′ signal dither processing circuit 40 individually dithers to generate a Y0 ′ signal and a Y1 ′ signal, and multiplexes them on the time axis using the MPX50. Without using
Dither processing of a digital video signal can be performed with an inexpensive circuit configuration.

[0036]

As described above, the present invention provides a digital
The processed luminance signal is time-divided into two signals, and each signal
Is dithered for
Digital signal dithering
Can provide dither circuit for digital video signal
You.

[0037]

[0038]

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital video signal dither circuit according to an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a dither processing circuit.

FIG. 3 is a waveform chart showing various signal waveforms.

FIG. 4 is a block diagram of a digital video signal dither circuit according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... DMPX 20 ... Dither circuit 30 ... Y0 signal dither processing circuit 40 ... Y1 signal dither processing circuit 50 ... MPX 60 ... D / A converter

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/14-5/217

Claims (2)

(57) [Claims] 1. A separation circuit for time-dividing a digitally processed luminance signal into two signals, two dither circuits for dithering each of the two signals, and time-division multiplexing of the two dithered signals. A digital video signal dither circuit comprising: a first pseudo-random signal generator for generating a pseudo-random signal synchronized with a horizontal period; A second pseudo-random signal generator that generates a signal; a logic gate group that receives the pseudo-random signals generated by the first and second pseudo-random signal generators and outputs several types of dither signals; Upon rounding lower-order bits of the luminance signal, Se for selecting and outputting one signal from among the several dither signal according to the output of the lower bits Digital video signal dither circuit, characterized by comprising a connector. 2. The logic gate group includes an OR gate and an AN.
A pseudo-random signal which is made up of a D gate and which is at a high level at a rate of 0%, 25%, 50%, and 75%; and wherein the selector generates a different select signal according to the output of the lower bit. 2. A pseudo random signal selected from 0%, 25%, 50%, and 75% high levels in response to the select signal and output. Dither circuit for digital video signals.