JP3318643B2 - Viterbi decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder, and more particularly, to a partial response PR (A,
A differential metric is used in multi-state Viterbi decoding, such as ternary 4-state Viterbi decoding using A) as an equalization characteristic, and 4-level 4-state Viterbi decoding using a partial response PR (A, 2A, A) as an equalization characteristic. The present invention relates to a Viterbi decoder having a simple circuit configuration, capable of performing high-speed operation without causing a metric to overflow without calculation.

[0002]

2. Description of the Related Art In the technical field of digital mass storage such as digital VTRs, hard disks and optical disks, recently, PRML (Partial Response Maximum
A reproduction equalization / detection method called "iklihood" is being studied earnestly. PRML is a multi-valued partial response method that enables recording and reproduction in a narrow band, and has a better quality than a bit-by-bit identification by recursively calculating the likelihood (metric) of state transition. This is a combination of maximum likelihood decoding schemes that can provide an error rate. Viterbi decoding is known as one of the representative algorithms of the maximum likelihood decoding method.

[0003] The Viterbi algorithm was originally devised as a technique for decoding convolutional codes for error correction. The convolutional encoding method is an encoding method in which, for each bit input to the encoder, a plurality of preceding bits and the currently input bit are added by mod2, and the result is used as an output bit.
As a method of expressing a convolutional code, two branches are used.
A tree-like expression (tree structure) and a trellis expression focusing on the state of an encoder are known. A decoder that decodes a signal based on the Viterbi decoding method is called a Viterbi decoder. In general, an addition / comparison / selection unit that calculates a path metric, a path memory circuit that stores and updates surviving paths, and a surviving path It is composed of a maximum likelihood determination circuit that determines a decoded output from the inside.

A Viterbi decoder used for reproduction or decoding in various recording / reproducing apparatuses, signal transmission apparatuses, and the like is an LSI.
It is often realized in. However, when the Viterbi decoder is realized according to the basic configuration, a problem that the circuit scale becomes large is encountered. When the coding rate is increased, a problem is encountered that the constraint length must be shortened (for example, Kato, "The basic architecture has a limit in speeding up," Nikkei Electronics, 1991, 9.30, 3
16-319). Therefore, various improvement measures have been proposed, such as using circuits in parallel and configuring a Viterbi decoder according to the application.

In many cases, a Viterbi decoder is required to operate at high speed. However, a critical path exists in a metric addition / comparison / selection circuit (ACS), which hinders high speed operation ( For example, Gerhard Fettwe
is, et al., "Speeding up the LSI of a Viterbi decoder (above), Eliminating a feedback loop is the key to LSI implementation", Nikkei Electronics, 1991, 9.30, pp. 320-325).

The applicant of the present application has proposed a method and a circuit configuration for increasing the speed of a Viterbi decoder (for example, filed on September 14, 1994, entitled "Viterbi Decoding Method and Viterbi Decoding Apparatus", Japanese Patent Application No. Hei 6 (1994)). 219873). This high-speed Viterbi decoder is suitable mainly for two-state Viterbi decoding.

[0007]

The ternary 4-state Viterbi decoding using the partial response PR (A, A) as the equalizing characteristic, and the 4-valued 4-state using the partial response PR (A, 2A, A) as the equalizing characteristic. It is known that multi-state Viterbi decoding such as state Viterbi decoding is suitable for recording modulation codes. These recording modulation codes are widely used as recording modulation codes for digital VTRs and magneto-optical disk drive devices. Even when such multi-valued Viterbi decoding is realized, the above-described problem, that is, an increase in the circuit scale and a limit of the operation speed are encountered. In addition, one encounters the problem of metric overflow. Therefore, a Viterbi decoder suitable for decoding a multi-state recording modulation code in a digital VTR or the like is desired.

An object of the present invention is to provide a partial response P
Multi-valued (multi-state) such as ternary 4-state Viterbi decoding using R (A, A) as an equalizing characteristic, and 4-valued 4-state Viterbi decoding using a partial response PR (A, 2A, A) as an equalizing characteristic It is an object of the present invention to provide a Viterbi decoder which can perform the Viterbi decoding at a high speed with a simple circuit configuration and does not overflow the metric.

[0009]

According to the present invention SUMMARY OF], a branch metric calculating circuit (BMC), the branch
Branch of each state output from the metric calculation circuit
An adder that adds the metric and the past metric;
Compare the output of the calculator and select the metric with the highest likelihood.
Selector / selector and metric storage circuit
Metric addition / comparison / selection circuit (AC
S) and selected by the metric addition / comparison / selection circuit
Keep the latest metrics that have been
A metric storage / normalization circuit for output ,
According to the selection signal of the comparison circuit of the comparison / selection circuit (ACS)
Te holds a path of a plurality of state path memory circuit (P
Possess a M), 3 value 4, PR (A, A) equalization characteristic
A Viterbi decoder suitable for multi-level multi-state Viterbi decoding such as Viterbi decoding of a state or 4-level 4-state Viterbi decoding having PR (A, 2A, A) as an equalizing characteristic , wherein the metric
The storage / normalization circuit is the addition / comparison / selection circuit (AC
Retention times for retaining the latest metrics output from S)
Path and the metric held in the holding circuit are halved.
And a subtraction circuit for subtracting the latest blank metric from the halved metric.
A Viterbi decoder for storing and normalizing a clock is provided.

[0010] good Mashiku is a subsequent circuit for the metric to 1/2, characterized in that further provided a subtraction circuit for subtracting a predetermined constant.

[0011]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a preferred embodiment of the present invention, a specific example of a PRML and a Viterbi decoder will be described.
A description will be given of an example of a 4-value 4-state Viterbi decoder effective for a recording modulation code having a minimum run length and RLmin = 2. The recording modulation code for RLmin = 2 is Mi
ller Square code, 8-14 (EFM) conversion code, RL
L (1,7) and NRZI (Non-Return to Zero Invers)
such modulation code which is a combination of e) and are known, these recording modulation code is widely used as a digital VTR or a magneto-optical disk drive equipment of which recording modulation code.

The reproduction equalization characteristics using these recording modulation codes include partial response: PR
(1,1) and partial response: PR (0.5,
It is known that the two types (1, 0.5) and their intermediate equalization characteristics are applicable. At this time, FIG.
As illustrated in FIG. 2A and FIG.
The amplitude of a signal at or above the Nyquist frequency, which is a frequency of / 2, becomes zero. FIGS. 1A to 1C show amplitude characteristics (FIG. 1A) and unit pulse response characteristics (FIG. 1) of PR (1, 1) equalization characteristics in the case of performing ternary discrimination.
2B is a graph showing an eye pattern (FIG. 1C). FIGS. 2A to 2C respectively show PR (0.5, PR) in the case of performing binary identification or quaternary identification.
3 is a graph showing an amplitude characteristic (FIG. 2A), a unit pulse response characteristic (FIG. 2B), and an eye pattern (FIG. 2C) of an equalization characteristic of (1, 0.5). 1 (A) and 2
In (A), the horizontal axis represents the normalized unit frequency,
The vertical axis indicates the amplitude. 1B and 2B, the horizontal axis represents the reference time 0.00 and the time before and after the reference time.
The vertical axis indicates the pulse response value (amplitude). 1C and 2C, the horizontal axis represents time, and the vertical axis represents amplitude. In FIG. 1C, the three-valued identification is performed by identifying whether the value of the identification target is larger than the threshold (+), smaller than the threshold (-), or between the threshold (-) and the threshold (+). Will be

For the sake of generality, numerical values A and B
Using, PR (A, A) and PR (B, 2A, B) to Table <br/> serial. In the illustrated example, A = 1, PR (1,1), A = B
= 0.5 and PR (0.5,1,0.5). The simplest identification method is binary identification using the center level of the amplitude as a threshold. However, if Viterbi decoding is applied, the error rate can be improved, and high-density recording can be performed.
Viterbi decoding, which is highly effective when applied to a recording modulation code in which RLmin = 2, includes ternary 4-state Viterbi decoding using PR (1,1) as an equalizing characteristic, and PR (0.5,1,0). .
This is 4-value 4-state Viterbi decoding in which 5) is equalized. As can be seen from the comparison of the frequency characteristics in FIGS. 1A and 2A, the half Nyquist frequency (1/4 of the data clock frequency) is compared with PR (0.5, 1, 0.5). Since the frequency characteristic that emphasizes the intermediate frequency region around the frequency (frequency) is the characteristic of PR (1, 1), PR (0.5, 1, 0.5) becomes the equalizing characteristic as the linear recording density increases. The error rate of the quaternary 4-state Viterbi decoding is improved. However, since various conditions are actually added,
It is not possible to determine the superiority of PR (1,1) and PR (0.5,1,0.5).

FIGS. 3A and 3B are a state transition diagram and a trellis diagram of ternary 4-state Viterbi decoding using PR (1, 1) as an equalizing characteristic. Table 1 shows the conditions for the state transition of the ternary and four-state Viterbi decoding.

[0016]

[Table 1]

3 (A) and 3 (B) and Table 1,
S0, S1, S2, and S3 indicate four states. Notation in Table 1, for example, m (0, k-1) indicates m is metric, 0 indicates state S0, and k-1 indicates time. The symbol z indicates an input signal. The method of applying the standardized metric to the ternary 4-state Viterbi decoding using PR (1,1) as an equalization characteristic is described in, for example, "Error Rate Characteristics of 4-State Viterbi Decoding for 1,7 Codes" . Technical report MR91-34, pp21-28, 1991
(Yamamoto, Itoi). However, no whole Viterbi decoder has been proposed yet.

FIGS. 4A and 4B show PR (0.5, 1, 1).
FIG. 3 is a state transition diagram and a trellis diagram of four-value, four-state Viterbi decoding with an equalization characteristic of 0.5). Table 2 shows the conditions for the state transition of Viterbi decoding in four values and four states.

[0019]

[Table 2]

Hereinafter, the process of deriving the conditions of the state transition of the four values and four states shown in Table 2 will be described. Generalized PR (B,
The following shows four state transitions of four-value, four-state Viterbi decoding using 2A, B) as equalization characteristics.

(A) S0 Next state a [k] = 0 → c [k] = − AB (S0) a [k] = 1 → c [k] = − A (S1)

(B) Next state of S1 a [k] = 0 → c [k] = A (S2)

(C) S2 Next state a [k] = 0 → c [k] = A + B (S2) a [k] = 1 → c [k] = A (S3)

(D) S3 Next State a [k] = 0 → c [k] = − A (S0)

For the above four states, four types of metrics are defined as follows.

L (0, k) = min ｛L (0, k-1)
+ (Z [k] A + B) ** 2, L (3, k-1) + (z
[K] + A) ** 2｝

L (1, k) = L (0, k-1) + (z
[K] + A) ** 2

L (2, k) = min ｛L (2, k−1)
+ (Z [k] -AB) ** 2, L (13, k-1) +
(Z [k] -A) ** 2｝

L (3, k) = L (2, k-1) + (z
[K] -A) ** 2

The memory L (j, k) has an arbitrary value z
Since the square calculation of [k] is included, the operation speed must be high and the circuit scale becomes large in consideration of the circuit for performing this operation. Therefore, it is not desirable to realize a Viterbi decoder according to this basic principle. In order to improve this problem, paying attention to the fact that the information required for updating the metric is only the magnitude relation of L (j, k),
A method using a standardized metric of subtracting a common value is preferable. Normalized metrics are defined as follows.

M (j, k) = ｛L (j, k) -z [k]
** 2- (A + B) ** 2｝ / 2 / (A + B)

The standardized metric for each state is as follows.

M (0, k) = min ｛m (0, k-1)
+ Z [k], m (3, k-1) + α * z [k] -β}

M (1, k) = m (0, k-1) + α * z
[K] -β

M (2, k) = min ｛m (2, k-1)
−z [k], m (1, k−1) −α * z [k] −β}

M (3, k) = m (2, k-1) -α * z
[K] -β

Where α = A / (A + B), β = B * (B + 2 * A) / 2 /
(A + B).

Basic Circuit of Viterbi Decoder Generally, the basic circuit of a Viterbi decoder is a branch metric calculation circuit (BMC), an addition / comparison / selection circuit (AC
S) and three blocks of a path memory circuit (PM). Branch metric calculation circuit (BMC)
Performs the operation of the following four branch metrics bm0 to bm3 in the case of four-value four-state Viterbi decoding with PR (0.5, 1, 0.5) as the equalization characteristic.

Bm0 [k] = z [k] bm1 [k] = α * z [k] −β bm2 [k] = − z [k] bm3 [k] = − α * z [k] −β

Each of these branch metrics has a reproduction signal z (k) and four reference values: -AB,-
A, A + B, and a relative value of the likelihood (metric) with A. This arithmetic circuit may perform arithmetic over several clocks.

The addition / comparison / selection circuit (ACS) is a circuit that adds and compares the branch metric and the past metric and selects the smallest one, and performs the following standardized metric calculation.

M (0, k) = min ｛m (0, k-1)
+ Bm0 [k], m (3, k-1) + bm1 [k]｝ m (1, k) = m (0, k-1) + bm2 [k] m (2, k) = min ｛m (2, k-1) + bm2
[K], m (1, k-1) + bm3 [k]｝ m (3, k) = m (2, k-1) + bm3 [k]

Here, the determined standardized metric m
To pass (j, k) to the operation on the next clock,
Latch is required. Therefore, since a feedback loop must be processed within one clock, it becomes a critical path when the addition / comparison / selection circuit (ACS) converts the Viterbi decoder into a circuit.

The path memory circuit (PM) is a circuit for storing and updating the identification result as the history of each state.

First Embodiment A first embodiment of the Viterbi decoder according to the present invention will be described. PR
Viterbi decoding of both ternary 4-state Viterbi decoding with (1, 1) equalization characteristics and 4-value 4-state Viterbi decoding with PR (0.5, 1, 0.5) equalization characteristics Are exactly the same, only the branch metrics are different. Hereinafter, as a first embodiment, a 4-level 4-state Viterbi decoding will be described. For the sake of simplicity, a case where the reproduction signal is AD-converted with 8 bits and the internal operation is performed with 8 bits as an example is illustrated, but the number of bits and the negative number of the internal operation are not limited to this example.

FIG. 5 is an overall block diagram of a 4-level 4-state Viterbi decoder according to a first embodiment of the present invention which uses PR (0.5, 1, 0.5) as an equalizing characteristic. The Viterbi decoder 100 illustrated in FIG. 5 includes a branch metric calculation circuit (BMC) 110 and a metric storage circuit (MM) 13
0, metric addition / comparison / selection circuit (ACS) 15
0, 4 path memory circuits (PM) 170, 17
2, 174, 176.

The basic operation of the Viterbi decoder 100 will be described.
The 8-bit input signal IN [0: 7] is input to a branch metric calculation circuit (BMC) 110. The branch metric calculation circuit (BMC) 110 responds to the clock signal CLK based on the reference values A [0: 7] and B [0: 7], and outputs four branch metrics BM0.
[0: 7] to BM3 [0: 7] are calculated and output to the metric addition / comparison / selection circuit (ACS) 150 in the next stage. Here, A [0: 7] and B [0: 7] correspond to α and β in the above equation. In the metric addition / comparison / selection circuit (ACS) 150, the previous metric M0
New metrics L0 [0: 7] to L3 [0: based on [0: 7] to M3 [0: 7] and the latest branch metrics BM0 [0: 7] to BM3 [0: 7]. 7] is output to the metric storage circuit (MM) 130 and the path selection signals SEL0 and SEL2 are output to the path memory circuits (PM) 170 and 172. The metric storage circuit (MM) 130 is a circuit for storing the metric output from the metric addition / comparison / selection circuit (ACS) 150. The metric L0 [0: 7] ~
L3 [0: 7] is input and latched.
[0: 7] to M3 [0: 7] are returned to the metric addition / comparison / selection circuit (ACS) 150. The metric storage circuit (MM) 130 and the metric addition / comparison / selection circuit (ACS) 150 constitute the above-described addition / comparison / selection circuit (ACS). Path memory circuit (P
M) 170, 172, 174, and 176 are circuits that store paths. In state 0 and state 2, which have two path candidates (self and another) to be inherited, path memory circuits (PM) 170 and 172 of the A system are used, and path candidates to be inherited are used. In state 1 and state 3 where there is only one (not inherited from itself), path memory circuits (PM) 174 and 176 of the B system are used. PM
x [0:15] is the identification result of each state up to 16 clocks before, and PMx

[0] is uniquely set internally, and P
Mx [0:14] is inherited by the next clock and PMx
[15] becomes the final identification result (decoding result) DEC _OUT . x shows the number of 0-3.

FIG. 6 is a circuit configuration diagram of the branch metric calculation circuit (BMC) 110 shown in FIG. The branch metric calculation circuit (BMC) 110 SIGs the 8-bit input signal IN [0: 7] three clocks before.
When [0: 7], the following four types of branch metrics are calculated and output.

BM0 = SIG, BM1 = A * SIG-B, BM2 = -SIG, BM3 = -A * SIG-B

When A is an arbitrary value, a multiplier is required. However, when PR (0.5, 1, 0.5) is based on the equalization characteristic, A = １ ／ may be set. In this case, since only one bit shift is required without performing multiplication, a simple shift register can be used without providing a multiplication circuit, and the circuit configuration is simplified. The value of B is a value to be determined according to the number of bits of the AD converter.

FIG. 7 is a block diagram of the metric addition / comparison / selection circuit (ACS) 150. The metric addition / comparison / selection circuit (ACS) 150 includes two-input adders (<C = A + B>) 152, 154, and 158 and a two-input comparison / selector (<COMPARE 2>) 156. And calculate the following metric.

L0 = min {M0 + BM0, M3 + BM1} L1 = M0 + BM2

Adders (<C = A + B>) 162, 16
4,168 and 2-input comparison / selector (<COMPAR
E 2>) 166 to calculate the following metric.

L2 = min {M2 + BM2, M1 + BM3} L3 = M2 + BM3

Two-input comparator / selector (<COMPARE)
2>) 156 and 166 output selection signals according to the following rules.

[0056]

FIG. 8 shows a metric storage circuit (MM) 130.
FIG. The metric storage circuit (MM) 130 includes 8-bit flip-flop circuits 131 to 1
34. Flip-flops 131 to 1
34 is a metric addition / comparison / selection circuit (ACS)
Latest metric compared and selected at 150, L0
[0: 7] to L3 [0: 7] are latched in response to the clock signal CLK, and the metric M0 used in the next calculation is latched.
[0: 7] to L3 [0: 7].

FIG. 9 shows a path memory circuit (PM) 17.
It is a circuit block diagram of 0,172,174,176. A-system path memory circuit (PM) 170 used to store the state 0 (S0) and state 2 (S2) paths,
172 is a metric addition / comparison / selection circuit (AC
S) Comparison circuit (<COMPARE 2>) 1 in 150
Serial shift and parallel load are selected according to the selection signal SELx from 56 and 166. That is, S
If EL = 0, the previous identification result PM _OUT [1:14] is inherited, and if SEL = 1, PM _IN [1:14], which is the identification result of another state, is inherited. PM

As the latest identification result corresponding to [0], 0 is uniquely given from the state transition of FIG. The path memory circuits (PM) 174 and 176 of the B system used for storing the paths of the state 1 (S1) and the state 3 (S3) perform only the parallel load. That is, PM which is the identification result of another state
_{Inherits INT} [1:14]. PM

As the latest identification result corresponding to [0], 1 uniquely from the state transition of FIG.
give.

In the above-described circuit to which the 4-value 4-state Viterbi decoding algorithm is applied as it is, the metric addition / comparison / selection circuit (ACS) 150 repeatedly selects the smaller metric. M3 monotonically decreases and overflows reliably in operations with a finite bit length. FIG. 10 shows PR (0.
5 is a graph showing how a metric changes when 4-value 4-state Viterbi decoding is applied to a reproduced signal equalized to (5, 1, 0.5). The horizontal axis shows the bit clock time, and the vertical axis shows the metrics M0 to M3. Referring to FIG. 10, it can be seen that the metric monotonically decreases when the identification of 10,000 bits is repeated. The monotonically occurring metric reaches −6.1 × 10 ⁺³ E. Therefore,
In order to realize a Viterbi decoder circuit with an effective bit length, it is necessary to perform some improvement processing.

As one of the methods, it is conceivable that the metric is cleared after processing a certain number of data by modifying the recording modulation code, but the existing recording modulation code without such modification is considered. Is difficult. Also, in ternary two-state Viterbi decoding for PR (1,1) and PR (1, -1), a Viterbi decoder calculates a difference (differential metric) between two state metrics and classifies the difference. Can be configured, so that the metric does not overflow. However, when trying to apply the differential metric to Viterbi decoding having a large number of states, such as the above-described 4-valued 4-state Viterbi decoding, the case is extremely divided. It is complicated and cannot be applied easily.

Second Embodiment A second embodiment of the Viterbi decoder according to the present invention improves the problem in the first embodiment described above. A second embodiment of the Viterbi decoder according to the present invention will be described. FIG. 11 is a configuration diagram of the Viterbi decoder 100A of the second embodiment. Viterbi decoder 100A
As in the Viterbi decoder 100 illustrated in FIG. 5, a branch metric calculation circuit (BMC) 110, a metric storage and compression circuit (MM1) 130A, a metric addition / comparison / selection circuit (ACS) 150, and a path .Memory circuits (PM) 170, 172, 174, 17
6. The Viterbi decoder 100 illustrated in FIG.
Comparing the Viterbi decoder 100A illustrated in FIG. 1, the metric storage and compression circuit (MM) 130A is different.
Branch / metric calculation circuit (BMC) 110, metric addition / comparison / selection circuit (ACS) 150, and path / memory circuits (PM) 170, 172, 17
4, 176 is substantially the same as the circuits illustrated in FIGS.

FIG. 12 is a diagram showing a circuit configuration of the metric storage and compression circuit (MM1) 130A illustrated in FIG. Comparing the metric storage and compression circuit (MM) 130A illustrated in FIG. 12 with the metric storage circuit (MM) 130 illustrated in FIG. 8, the metric storage circuit (MM) 130A has three D-type flip-flops 1.
It comprises 32 to 134 and three subtraction circuits 135 to 137. The D flip-flop 131 in FIG. 8 is deleted, and three subtraction circuits 135 to 137 are added. In the metric storage circuit (MM) 130 of FIG. 8, when the metrics L0 [0: 7] to L3 [0: 7] are latched by the D-type flip-flops 131 to 134 and used for the next calculation, as described above. In the meantime, the negative number increases and overflows. To solve this problem, the metric storage and compression circuit (MM) 130A shown in FIG. 12 uses a subtraction circuit (<C = AB).
>) 135 to 137 and Mn = Ln−L0 (n is 1 to 3)
, The D-type flip-flops 132 to
Latched at 134 and output as M0 [0: 7] to M3 [0: 7]. As is apparent, since M0 always becomes 0, M0 + BM0, M0 + in the metric addition / comparison / selection circuit (ACS) 150 shown in FIG.
The adders 152 and 158 for performing BM2 can be omitted.

FIG. 13 is a graph showing the effect of the second embodiment. As illustrated in FIG. 10, in the first embodiment, the metric that monotonously decreases to reach −6.1 × 10 ^+3, but in the present embodiment, as illustrated in FIG. 13, the metric is +4.5. It can be seen that it is within the range of about -4.0, and overflow no longer occurs. That is, the metric storage and compression circuit (M
M) Subtraction circuit (<C = AB>) 13 in 130A
At 5 to 137, overflow is prevented by subtracting Mn = Ln-L0 (n is 1 to 3).

Modification of the Second Embodiment In the second embodiment, the metric L0 is
3, but may be subtracted from L0 to L3 using any of L1, L2, and L3. Alternatively, the average value of L0 to L3 may be calculated and subtracted from L0 to L3. However, in this case, since an adder is required to calculate the average value, there are disadvantages in that the circuit configuration is somewhat complicated and the operable clock frequency becomes slow. However, in any of the above cases, overflow can be prevented.

Third Embodiment A digital mask to which the above-mentioned Viterbi decoder is applied.
Demands for high-speed storage devices are increasing. A problem when realizing a high-speed circuit of the Viterbi decoder is a metric addition / comparison / selection circuit (AC
S) This is a loop in 150, and the following operation must be performed within one clock.

Addition → comparison → selection → storage

When the second embodiment is applied, the following operation must be performed within one clock cycle.

Addition → Comparison → Selection → Subtraction → Storage

The operable clock frequency is reliably reduced by the amount of the subtraction processing performed by the subtraction circuits 135 to 137 in the metric storage and compression circuit (MM) 130A of the second embodiment. The third embodiment solves the above-mentioned problem. FIG. 14 is a configuration diagram of the Viterbi decoder 100B of the second embodiment. The Viterbi decoder 100B, like the Viterbi decoder 100 illustrated in FIG. 5, includes a branch metric calculation circuit (BMC) 110, a metric storage and compression circuit (MM2) 130B, and a metric addition / comparison / selection circuit (ACS) 150. And the path memory circuit (P
M) 170, 172, 174, 176; Comparing the Viterbi decoder 100 illustrated in FIG. 5 with the Viterbi decoder 100B illustrated in FIG. 14, the metric storage and compression circuit (MM2) 130B is different. The branch metric calculation circuit (BMC) 110, the metric addition / comparison / selection circuit (ACS) 150, and the path / memory circuits (PM) 170, 172, 174, and 176 are illustrated in FIGS. This is practically the same as the circuit shown.

FIG. 15 shows a metric storage circuit (MM) in the Viterbi decoder 100B of the third embodiment illustrated in FIG.
2) A diagram showing a circuit configuration of 130B. The metric storage and compression circuit (MM2) 130B includes D-type flip-flops 141 to 144, a division (division) circuit 145,
It has subtractors 146 to 149 and D-type flip-flops 131 to 134 similar to those illustrated in FIG.
The latest metrics L0 [0: 7] to L3 selected by the metric addition / comparison / selection circuit (ACS) 150
[0: 7] is the D-type flip-flop 141 to 141
Latched at 144, the normalized metric M0 [0:
7] to M3 [0: 7]. In the division (division) circuit 145, only the metric M0 [0: 7] is 1 /
2 Since the division (division) circuit 145 reduces the metric M0 [0: 7] to １ ／, it is actually realized by a shift register and does not perform division. The metric M0 [0: 7] that has been halved in the division (division) circuit 145 by the subtraction circuits 146 to 149 is subtracted from the latest branch metrics BM0 to BM3 [0: 7], and the branch metric is calculated. After being held by the D-type flip-flops 131 to 134, normalized branch metrics NBM0 to NBM3 [0: 7] are output. As described above, the operation for normalizing the metric is performed by the metric addition / comparison / selection circuit (ACS) 1
The process goes out of the 50 operation processing loops, and the following operation may be performed within one clock.

Addition → comparison → selection → store

As a result, the Viterbi decoder 10 of the third embodiment
0B enables high-speed operation as compared with the case where the metric storage and compression circuit (MM1) 130 of the second embodiment is applied. That is, the Viterbi decoder 10 of the third embodiment
0B is a Viterbi decoder capable of high-speed operation. In the third embodiment, what is important is that one
The / 2 metric M0 is to be subtracted from BM0 to BM3 by subtractors 146 to 149. In the subtractors 146 to 149 that perform the metric control, the operation for normalizing the metric is performed with a delay of one clock as compared with the Viterbi decoder 100A of the second embodiment, so that the dead time increases. Therefore, M0 [0:
7] directly to the branch metrics BM0 to BM3
When subtracted from [0: 7], the loop gain is too large, the phase margin is lost, and the metric may diverge. This phenomenon is shown in FIG. Referring to FIG. 16, it can be seen that the metric does not converge but gradually increases. Over a longer period of time, the metric will diverge, so it will definitely overflow in real circuits. Therefore, the branch metric BM0
The metric M0 subtracted from ＢBM3 must be multiplied by a suitable value less than one. If a value smaller than an arbitrary value of 1 is used, a multiplication circuit is required, and thus the loop in the metric control circuit is as follows.

Multiplication → subtraction → storage

In this processing method, the operable clock frequency is slower than the loop processing time of the metric addition / comparison / selection circuit (ACS) 150. On the other hand, in the third embodiment, the division circuit 145 is actually constituted by a shift register, and the operation for halving only uses a value shifted by one bit, so that the time required for the operation is very short. The loop in the metric control process described above is as follows.

Subtraction → storage

As is clear from this processing, the Viterbi decoder 100B operates reliably earlier than the loop processing time of the metric addition / comparison / selection circuit (ACS) 150. The metric M0 is halved before branching
FIG. 17 shows the metrics when the metrics are subtracted from the metrics BM0 to BM3. In FIG. 17, the metric is −
It is in the range of about 4.5 to +2.5, does not overflow, and the number of loop processes in the metric addition / comparison / selection circuit (ACS) 150 is minimized.

First Modification of Third Embodiment In the third embodiment, the metric M0, which is the simplest and most effective, is halved before the branch metrics BM0 to BM0.
Although the method of subtracting BM3 has been exemplified, it is also possible to reduce any of the metrics M1, M2, and M3 to 1/2 instead of the metric M0 and to subtract the branch metrics BM0 to BM3 from the metric thus reduced to 1/2. Good.

Second Modification of Third Embodiment Further , the average value of the metrics M0 to M3 may be reduced to half and then subtracted from BM0 to BM3. However, in this case, an adder circuit is required to calculate the average value of the metrics M0 to M3.

Third Modification of Third Embodiment The metric M0 does not necessarily have to be halved, and may be multiplied by an arbitrary value of 1 or less. However, in this case, the division circuit 145 is not a shift register but a circuit for actually performing division.

Fourth Modification of Third Embodiment FIG. 18 is a modification of the metric storage and compression circuit (MM) 130B illustrated in FIG. The metric storage and compression circuit (MM) 130 illustrated in FIG.
B ′ is provided after the division circuit (shift register) 145,
After the metric M0 is reduced to 1/2, a subtraction circuit 145A for reducing the constant γ is added. For example, the constant γ
= 0.4, the division circuit 145 and the subtraction circuit 145A
Thus, the calculation of 1 / 2-0.4 of the metric M0 has been performed. Therefore, it is also possible to realize the division circuit 145 with a shift register and to subtract the branch metric from a metric other than half of the metric M0 without using the division circuit or the multiplication circuit. The metric storage and compression circuit (MM) 130 illustrated in FIG.
FIG. 19 shows the variation of the metric when B = 0.4 in B ′. The metric shown in FIG.
It is in the range of 5 to 3.0. Here, it should be noted that the fluctuation of the metric on the positive side and the fluctuation of the metric on the negative side are almost the same. This has an advantage that the number of bits can be reduced because the required number of bits is substantially the same on the + side and the − side, and the fluctuation width is smaller than the fluctuation of the metric in FIG.

Fifth Modification of Third Embodiment In the third embodiment, the metric control processing does not have to be completed within one clock, but is controlled using the metrics M0 to M3 several clocks earlier. Is also good. However, in this case, since the dead time increases, the loop gain of the metric control process needs to be further reduced.

In the above, the description has been made focusing on the four-value / four-state Viterbi decoding with PR (0.5, 1, 0.5) as the equalizing characteristic.
The same applies to Viterbi decoding with three values and four states using PR (1, 1) as the equalization characteristic.

[0083]

According to the present invention, by normalizing the metric in the Viterbi decoder, it is possible to prevent the metric from monotonously decreasing and overflowing, and to implement the Viterbi decoder with a finite bit length. realizable. Also,
In the Viterbi decoder of the present invention, several adders in the metric adder / comparator / selector (ACS) can be eliminated.

According to the present invention, metric addition
A feedback loop in the comparison / selection circuit (ACS) is reduced, and high-speed operation is enabled. In this case, metric overflow can be avoided.

[Brief description of the drawings]

FIGS. 1A to 1C respectively show an amplitude characteristic, a unit pulse response characteristic, and an eye pattern of a PR (1, 1) equalization characteristic when performing ternary identification. It is a graph.

FIGS. 2A to 2C respectively show PR (0.5, PR) in the case of performing binary identification or quaternary identification.
2 is a graph showing an amplitude characteristic, a unit pulse response characteristic, and an eye pattern of the equalization characteristic of (1, 0.5).

FIGS. 3A and 3B are a state transition diagram and a trellis diagram of ternary 4-state Viterbi decoding using PR (1, 1) as an equalization characteristic.

FIGS. 4A and 4B show PR (0.5, 1, 0.
FIG. 4 is a state transition diagram and a trellis diagram of four-value four-state Viterbi decoding with 5) being an equalization characteristic.

FIG. 5 is an overall block diagram of a 4-value 4-state Viterbi decoder as a first embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a branch metric calculation circuit (BMC) shown in FIG. 5;

FIG. 7 is a diagram illustrating addition, comparison, and addition of the metrics shown in FIG. 5;
It is a block diagram of a selection circuit (ACS).

FIG. 8 is a metric storage circuit (M) shown in FIG. 5;
It is a circuit diagram of M).

FIG. 9 is a diagram illustrating the path memory circuit (P) shown in FIG. 5;
FIG. 3M is a circuit configuration diagram of FIG.

10 is a diagram illustrating a metric of a case where quaternary 4-state Viterbi decoding is applied to a reproduced signal equalized to PR (0.5, 1.0.5) in the Viterbi decoder illustrated in FIG. 5; It is a graph which shows a mode of a change.

FIG. 11 is a configuration diagram of a Viterbi decoder according to a second embodiment of the present invention.

FIG. 12 is a diagram showing a circuit configuration of a metric storage circuit (MM1) in the Viterbi decoder illustrated in FIG. 11;

FIG. 13 is a graph showing the effect of the second embodiment of the present invention.

FIG. 14 is a diagram illustrating a circuit configuration of a metric storage circuit (MM2) according to a third embodiment;

FIG. 14 is a diagram illustrating a circuit configuration of a metric storage circuit (MM2) according to a third embodiment;

FIG. 16 is a graph showing metric fluctuations when metric control is not performed.

FIG. 17 is a graph showing metric fluctuation when the metric storage and compression circuit of FIG. 15 is used.

FIG. 18 is a modified circuit diagram of the metric storage and compression circuit (MM) illustrated in FIG.

FIG. 19 is a graph showing metric fluctuation when the metric storage and compression circuit of FIG. 18 is used.

[Explanation of symbols]

100, 100A, 100B Viterbi decoder 110 Branch metric calculation circuit (BMC) 130 Metric storage circuit (MM) 150 Metric addition / comparison / selection circuit (AC
S) 170, 172, 174, 176 pass memory circuit (PM)

Continuation of the front page (56) References JP-A-8-180608 (JP, A) JP-A-8-8763 (JP, A) JP-A-7-264079 (JP, A) JP-A-7-66736 (JP) JP-A-7-66735 (JP, A) JP-A-6-338914 (JP, A) JP-A-6-338913 (JP, A) JP-A-6-334692 (JP, A) 6-268531 (JP, A) JP-A-5-211447 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00 G11B 20/00 H04L 25/00 H04L 1 / 00

Claims (2)

(57) [Claims] 1. A branch metric calculation circuit (BMC)
And each state output from the branch metric calculation circuit.
The branch metric of the state and the past metric
Compare the output of the adder with the most likely
The compare / selector for selecting metrics and the metrics
Metric addition / comparison /
A selection circuit (ACS) and the metric addition / comparison / selection circuit.
Keep new metrics and output standardized metrics
Of a metric storage / normalization circuit and a comparison circuit of the addition / comparison / selection circuit (ACS)
Possess a path memory circuit for holding path of the plurality of states (PM) in response to the signal, PR (A, A) a Viterbi decoding or PR ternary 4 states that the equalization characteristic (A, 2A, A) a Viterbi decoder suitable for multi-level multi-state Viterbi decoding such as 4-level 4-state Viterbi decoding having A) as an equalizing characteristic , wherein the metric storage / normalization circuit includes the addition / comparison / selection circuit ( ACS)
A holding circuit for holding a new metric, and a circuit for halving the metric held in the holding circuit
And the latest blanc met from the halved metric
A Viterbi decoder having a subtraction circuit for reducing licks and storing and normalizing the metric . 2. The Viterbi decoder according to claim 1, further comprising a subtraction circuit for reducing a predetermined constant, at a subsequent stage of the circuit for reducing the metric to 1/2.