JP3322239B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device such as a BiCMOS.

[0002]

2. Description of the Related Art Hitherto, a BiCMOS integrated circuit has been used in which the low power consumption of a MOS integrated circuit and the high speed of a bipolar integrated circuit are compatible in one integrated circuit. In such a BiCMOS integrated circuit, it is known that the size of the bipolar transistor greatly affects the transistor performance. That is, there is a problem that the size of the transistor is increased and the parasitic resistance and the parasitic capacitance are increased due to the element isolation regions provided between the collector and the base in the bipolar transistor and around the transistor.

Therefore, how to narrow the element isolation region is one of the important factors in improving the performance of a transistor. For example, JP-A-8-203994
Japanese Patent Application Laid-Open Publication No. H11-163873 discloses that a device isolation oxide film formed by a LOCOS method and a device isolation oxide film formed by a U-groove (hereinafter referred to as a shallow trench) shallower than a well are used as a device isolation of a BiCMOS.

The element isolation oxide film formed in the shallow trench is formed to a position shallower than the depth of the buried layer of the bipolar transistor, and is used as an element isolation region between the collector and the base. . Around the active region of the bipolar transistor, a U-groove (hereinafter referred to as a deep trench) having a depth penetrating the buried layer and the CMOS well and reaching the silicon substrate.
Are formed in a ring shape, and the bipolar transistor and C
It is used for element isolation from MOS. further,
The deep trench is formed between a CMOS N-type well and a P-type well.
Also provided between the mold well and used for PN separation.

Here, a method for manufacturing a BiCMOS disclosed in Japanese Patent Application Laid-Open No. 8-203994 will be described.

FIGS. 12 (a) to 12 (d) and FIGS. 13 (e) to 13 (e)
14 (g) and FIGS. 14 (h) and 14 (i) are cross-sectional views showing the manufacturing steps of the BiCMOS disclosed in the above publication. First, as shown in FIG. 12A, a high-concentration N-type buried layer region 502 is formed on a P-type semiconductor substrate 501 made of silicon by using a known method, 2.0
A μm N-type epitaxial layer region 503 is formed. Further, after forming an element isolation oxide film 504 by using a known LOCOS method or by burying an oxide film in a groove (corresponding to the above-described shallow trench), an N-type well region 505 and a P-type well region 506 are formed. It is formed by using a known high energy implantation method.

Next, as shown in FIG. 12B, a gate oxide film 507 having a thickness of 1 to 10 nm is formed on the surface of the substrate, and then polycrystalline silicon, amorphous silicon, or 100 to 400 nm thick. , to form a conductive film 508 Ru polycrystalline silicon Tona containing impurities.

Next, as shown in FIG. 12C, after a gate electrode formation region is masked using a photoresist (not shown), a known anisotropic etching technique is used.
A gate electrode 509 is formed. Thereafter, after removing the photoresist, a high-concentration N-type diffusion layer region 510 used for extracting a collector of the bipolar transistor;
A P-type diffusion layer region 512, an N-type diffusion layer region 513, and an intrinsic base region 511 are sequentially formed.

Next, as shown in FIG. 12D, after an oxide film (not shown) having a thickness of 50 to 400 nm is formed,
The gate electrode 50 is formed using a known anisotropic etching technique.
An oxide film is left only on the side wall of
6 is formed. Thereafter, a high-concentration P-type diffusion layer region 517 and a high-concentration N-type diffusion layer region 518 are sequentially formed (LDD).
An oxide film 514 having a thickness of 50 to 200 nm is formed, and a photoresist (not shown) is used to form the oxide film 514 in the emitter diffusion window of the bipolar transistor and the element isolation region. Using anisotropic etching.

After removing the photoresist, a thickness of 10
A conductive film made of polycrystalline silicon, amorphous silicon or impurity-containing polycrystalline silicon having a thickness of 0 to 400 nm is formed, and an emitter extraction electrode is formed using a photoresist (not shown) and a known anisotropic etching technique. 515 is formed. In addition, heat treatment in the manufacturing process and R
Impurities are diffused from the emitter extraction electrode 515 into the intrinsic base region 511 by a heat treatment such as TA (Rapid Thermal Anneal), and a high-concentration N-type diffusion layer region 519 is formed.

Next, as shown in FIG.
After the photoresist 520 is formed, the element isolation oxide film 504 and the high-concentration N-type buried layer region 50 are formed by using a known oxide film etching technique and a silicon etching technique.
2 and reaches the P-type semiconductor substrate 501, from 1.0 to
A deep trench 521 having a depth of 5.0 μm is formed.

Next, as shown in FIG.
After the photoresist 520 is removed, a second photoresist 522 is newly formed, and B is ion-implanted with an energy of 10 to 30 KeV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^−2. The channel stopper layer 523 is formed only at the bottom of the deep trench 521 provided between the CMOS and the bipolar transistor.

Next, as shown in FIG.
After the photoresist 522 is removed, a first interlayer insulating film 524 having a thickness of 50 to 150 nm, which has no thermal fluidity and contains no impurities, is formed by using a known CVD technique.

Next, as shown in FIG. 14 (h), a film having thermal fluidity (second interlayer insulating film 525) such as BPSG (Boron Phospho Silicate Glass) is formed by a CVD technique. The inside of the deep trench 521 is buried by performing a heat treatment at 950 ° C. for about 20 minutes or the like.

Next, as shown in FIG. 14 (i), a contact hole is opened after the surface of the substrate is flattened by a known CMP (Chemical Mechanical Polishing) technique or a BPSG overall etch-back technique.
And a contact plug 526 formed of TiN / TiN / Ti barrier metal. Then, a metal wiring 527 is formed on the second interlayer insulating film 525 so as to be connected to the contact plug 526. From the above, P
A CMOS composed of MOS and NMOS and an NPN transistor which is a bipolar transistor are completed.

[0016]

As apparent from the above description, in the related art, a deep isolation (deep trench) and a shallow isolation (shallow trench) are separately formed. Further, since the deep trench is formed through the shallow trench after the formation of the second groove, the following problems occur.

That is, when the mask is misaligned, as shown in FIG.
The hole 604 provided in the trench may be displaced from the end of the shallow trench, and the oxide film may be etched by the oxide film dry etching reflecting the shape of the end portion of the element isolation oxide film 602 (FIG. 15 ( b ')). as a result,
The depth of the deep trench 605 ′ becomes narrower as approaching the bottom thereof, and voids (voids) are easily generated when the deep trench 605 ′ is filled with the BPSG film. By the way, if the alignment of the mask 603 is normal, as shown in FIGS. 15A and 15B, the deep trench 605 reaching the substrate 601 does not change its diameter even at the bottom thereof and has no void. Does not occur.

As a matter of course, by reducing the size of the transistor in order to improve the degree of integration, the tolerance for mask misalignment is reduced, and the above-mentioned phenomenon becomes remarkable.

An object of the present invention is to solve such a problem, and to solve the above-mentioned problem of voids and to improve transistor performance when forming element isolation regions having different depths. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can perform the above.

[0020]

Means for Solving the Problems] To achieve the above object, a method of manufacturing a semiconductor device according to the present invention, the semiconductive <br/> body substrate, and the desired device isolation region and the active element forming a first mask having a plurality of through holes provided in correspondence with, on the semiconductor substrate, forming a first conductive film so as to cover the first mask ,
On said first conductive film, forming a second mask that covers at least one of the through holes on the active element exposed from the second mask of said first conductive film By etching the portion of the first conductive film and the semiconductor substrate thereunder .
A second conductive film consisting of a portion covered by a second mask.
As well as it formed, and forming a groove in the semiconductor substrate, after removing the second mask, to form a first groove by etching the bottom of the groove, the second conductive film and By etching the underlying semiconductor substrate, the upper surface of the active element
The second shallower than the first groove is located at a position corresponding to the through hole .
And a step of forming a groove. Further, according to the present invention,
A method of manufacturing a conductor device includes a method of mounting a plurality of active elements on a semiconductor substrate.
Forming and separating desired elements on the semiconductor substrate.
First having a plurality of through holes provided corresponding to the region
Forming a mask, and forming the mask on the semiconductor substrate.
Forming a first conductive film so as to cover the first mask;
And forming a small number of the through holes on the first conductive film.
Forming a second mask covering at least one;
Exposed from the second mask in the first conductive film
Part and the above semiconductor substrate under it
By doing so, the second conductive film out of the first conductive film
Forming a second conductive film comprising a portion covered with a mask;
And forming a groove in the semiconductor substrate.
After removing the second mask, etch the bottom of the groove with an etchant.
To form a first groove,
The second conductive film and the underlying semiconductor substrate are etched.
The second groove is shallower than the first groove.
Forming a groove in the first and second grooves.
Filling with an insulator. Further, according to the present invention,
A method of manufacturing a semiconductor device includes the steps of:
And forming a desired element on the semiconductor substrate.
A plurality of active regions provided in correspondence with the separated region and the active element.
Forming a first mask having a through hole;
On the conductor substrate, cover the first mask
Forming a first conductive film; and forming the first conductive film on the first conductive film.
At least one of the through holes on the active element is covered.
Forming a second mask to cover the first conductive layer;
A portion of the film exposed from the second mask; and
By etching the semiconductor substrate therebelow,
And the first conductive film is covered with the second mask.
Forming a second conductive film consisting of the
Forming a groove in the semiconductor substrate and the second mask
Is removed, and then the bottom of the groove is etched.
To form the first groove, and the second conductive film and the
And etching the semiconductor substrate below it
A position corresponding to the through hole on the active element.
Forming a second groove shallower than the first groove,
Filling the first and second grooves with an insulator;
Having.

On the other hand, the present invention includes the following embodiments. That is, when the second conductive film is removed by etching, by leaving a part of the second conductive film,
A portion of this remaining the second conductive film may be used as an electrode of the active element. Further, the semiconductor device may be a CM
BiC composed of OS and bipolar transistor
It may be a MOS. Further, the first groove is formed in the C groove.
The second groove may be formed between a MOS and the bipolar transistor, and the second groove may be formed between a collector and an emitter in the bipolar transistor .

Further, a high-concentration N-type buried layer region is formed on a P-type semiconductor substrate made of silicon, and then an N-type epitaxial layer region is formed. Forming a gate electrode in each of the N-type well region and the P-type well region via a gate oxide film, and forming a bipolar transistor in the N-type epitaxial layer region. Forming a high-concentration N-type diffusion layer region for extracting a collector, forming a P-type diffusion layer region around the gate electrode located in the N-type well region, and surrounding the gate electrode located in the P-type well region; Forming an N-type diffusion layer region in the N-type epitaxial layer region and forming an intrinsic base region in the N-type epitaxial layer region; And the region for forming a bipolar
Through holes corresponding to a region for forming a second groove for separating the emitter and the collector of the transistor and a region for forming a first groove for separating the bipolar transistor and the CMOS, respectively. Forming an oxide film on the P-type semiconductor substrate, and forming a conductive film so as to cover the oxide film, and then forming the second groove other than the region where the emitter diffusion window is to be formed. Removing the conductive film other than the region to be etched by etching, forming a groove in a region where the first groove is formed by over-etching at this time, and penetrating the high concentration N-type buried layer region by etching. And forming a first groove reaching the P-type semiconductor substrate and a second groove shallower than the high-concentration N-type buried layer region. Forming an interlayer insulating film for filling the second trench and the first trench on the P-type semiconductor substrate; forming the interlayer insulating film on the P-type semiconductor substrate; Connecting an electrode to each of the transistors.

An N-type well region for forming a CMOS and a P-type semiconductor substrate are formed on a P-type semiconductor substrate made of silicon.
Forming a gate electrode in each of an N-type well region and a P-type well region for forming the CMOS through a gate oxide film;
An N-type well region for forming a bipolar transistor is formed on a type semiconductor substrate, and a P-type region is formed around a gate electrode located in the N-type well region for forming the CMOS.
Forming an N-type diffusion layer region, forming an N-type diffusion layer region around a gate electrode located in the P-type well region, and forming an intrinsic base region in the N-type well region for forming the bipolar transistor. Forming a region for forming an emitter diffusion window of the bipolar transistor, forming a second groove for separating the emitter and the collector of the bipolar transistor, and forming a region for separating the bipolar transistor and the CMOS. Forming an oxide film on the P-type semiconductor substrate having through holes corresponding to the regions where the first grooves are to be formed, and forming a conductive film so as to cover the oxide film. Removing the conductive film by etching other than the region where the emitter diffusion window is formed and the region where the second groove is formed; Forming a groove in a region where the first groove is formed by etching; etching the first groove reaching the P-type semiconductor substrate; and shallower than an N-type well region for forming the bipolar transistor. Forming a second groove, and forming an emitter lead-out electrode made of the conductive film; and an interlayer insulating film filling the second groove and the first groove on the P-type semiconductor substrate. And connecting an electrode to each of the CMOS and the bipolar transistor after opening the interlayer insulating film.

Further, an N-type well region for forming a CMOS and a P-type semiconductor substrate are formed on a P-type semiconductor substrate made of silicon.
Forming a gate electrode in each of an N-type well region and a P-type well region for forming the CMOS through a gate oxide film;
An N-type well region for forming a bipolar transistor is formed on a type semiconductor substrate, and a P-type region is formed around a gate electrode located in the N-type well region for forming the CMOS.
Forming an N-type diffusion layer region, forming an N-type diffusion layer region around a gate electrode located in the P-type well region, and forming an intrinsic base region in the N-type well region for forming the bipolar transistor. Forming a bipolar transistor, a region for forming an emitter diffusion window of the bipolar transistor, a region for forming a second trench for extracting a collector of the bipolar transistor;
Forming an oxide film on the P-type semiconductor substrate, having a through hole corresponding to each of the first trenches for separating S from the S region; After forming the conductive film, the conductive film is removed by etching other than the region for forming the emitter diffusion window and the region for forming the second groove, and the first groove is removed by over-etching at this time. Forming a groove in a region to be formed, a first groove reaching the P-type semiconductor substrate by etching, and a second groove shallower than an N-type well region for forming the bipolar transistor;
Forming an emitter extraction electrode made of the conductive film, and
Forming an interlayer insulating film filling the second groove and the first groove; and connecting an electrode to each of the CMOS and the bipolar transistor after opening the interlayer insulating film. It may be something.

The first trench provided between the CMOS and the bipolar transistor may have a channel stopper layer at the bottom.
Further, the semiconductor device may be a CMOS .

An N-type well region for forming a CMOS and a P-type semiconductor substrate are formed on a P-type semiconductor substrate made of silicon.
Forming a gate electrode in each of an N-type well region and a P-type well region for forming the CMOS through a gate oxide film;
Forming a P-type diffusion layer region around the gate electrode located in the P-type well region, and forming an N-type diffusion layer region around the gate electrode located in the P-type well region; A region for forming a second groove for separating the N-type well region, a region for forming a first groove for separating the N-type well region and the P-type well region,
Forming an oxide film on the P-type semiconductor substrate, having a through hole corresponding to each of the above, and forming a conductive film so as to cover the oxide film, and then forming the second groove the conductive film is removed by etching except a step of forming a groove in a region for forming the first groove by the over-etching in this, the first groove reaching to the P-type semiconductor substrate, the upper Symbol N Forming a second groove shallower than the mold well region; forming an interlayer insulating film filling the second groove and the first groove on the P-type semiconductor substrate; After opening the interlayer insulating film, the C
Connecting an electrode to the MOS. Further, the gate electrode may have an LDD structure.

[0027]

Next, an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment] FIGS.
(D), FIGS. 2 (e) to (h), FIGS. 3 (i) and (j)
It is sectional drawing which shows 1st Embodiment (manufacturing process) of this invention.

First, as shown in FIG. 1A, a high-concentration N-type buried layer region 102 is formed on a P-type semiconductor substrate 101 made of silicon by a known method.
An N-type epitaxial layer region 103 of 4 to 2.0 μm is formed. Then, an element isolation oxide film 104 is formed by embedding a known LOCOS method or an oxide film in the trench,
The N-type well region 105 and the P-type well region 106 are formed by using a known high energy implantation method or the like.

Next, as shown in FIG. 1B, a gate oxide film 107 having a thickness of 1 to 10 nm is formed on the substrate surface, and then polycrystalline silicon having a thickness of 100 to 400 nm is formed.
Amorphous silicon, or to form a conductive film 108 Ru polycrystalline silicon Tona containing impurities.

Next, as shown in FIG. 1C, after a gate electrode formation region is masked using a photoresist (not shown), a gate electrode 109 is formed using a known anisotropic etching technique. I do. After removing the photoresist, a high-concentration N-type diffusion layer region 110 for extracting the collector of the bipolar transistor and a P-type diffusion layer region 1 are formed.
12, the N-type diffusion layer region 113, and the intrinsic base region 11
1 are sequentially formed.

Next, as shown in FIG. 1D, after an oxide film (not shown) having a thickness of 50 to 400 nm is formed, the gate electrode 109 is formed by using a known anisotropic etching technique.
The oxide film is left only on the side wall of
To form Then, after a high-concentration P-type diffusion layer region 116 and a high-concentration N-type diffusion layer region 117 are sequentially formed, an oxide film 114 having a thickness of 50 to 200 nm is formed, and a first photoresist 118 is used. Oxide film 1 located at a portion of an emitter diffusion window of a bipolar transistor and a portion for forming a shallow trench and a deep trench
14 is removed using a known anisotropic etch.

Next, as shown in FIG. 2E, after the first photoresist 118 is removed, the thickness is set to 100 to 4
A first conductive film 119 made of 00 nm polycrystalline silicon, amorphous silicon, or polycrystalline silicon containing impurities is formed.

Then, as shown in FIG. 2F, after masking with a second photoresist 120 so as to cover the emitter lead-out electrode and the shallow trench formation region, a known anisotropic etching technique is applied. The second conductive film 119a is formed using the second conductive film 119a. At this time, a groove 121 is formed in a region where a deep trench is to be formed by over-etching.
To form

Next, as shown in FIG. 2G, after a third photoresist 124 is formed, the high-concentration N-type buried layer region 10 is formed by using a known silicon etching technique.
2 and reaches the P-type semiconductor substrate 101;
0 μm deep trench 122 and high concentration N
Shallow trench 12 shallower than mold buried layer region 102
Form 3 At the same time as the formation of the shallow trench 123, the emitter extraction electrode 119b is formed.

It is to be noted that a heat treatment in the manufacturing process or a heat treatment such as RTA causes
Impurities are diffused into the intrinsic base region 111, and a high-concentration N-type diffusion layer region 125 is formed.

Next, as shown in FIG. 2 (h), after removing the third photoresist 124, a photoresist (not shown) is formed, and then the channel is removed by ion implantation.
The stopper layer 127 is formed. After removing the photoresist, a first interlayer insulating film 126 having a thickness of 50 to 150 nm and having no thermal fluidity and containing no impurities is formed by using a known CVD technique.

Next, as shown in FIG. 3I, a film (second interlayer insulating film 128) having thermal fluidity such as BPSG is formed by a CVD technique, and
The deep trench 122 and the shallow trench 123 are buried by performing a heat treatment at 50 ° C. for about 20 minutes.

Finally, as shown in FIG. 3 (j), after planarization is performed by a known CMP technique or a BPSG overall etch-back technique, a contact hole is opened.
For example, a contact plug 129 formed of W and a barrier metal made of TiN / Ti, and a metal wiring 130 are formed. As a result, a BiCMOS composed of PMOS and NMOS and an NPN transistor are completed.

Next, another embodiment of the present invention will be described. As disclosed in JP-A-8-203994, the collector region of a bipolar transistor is formed of a high-concentration N-type buried layer region and an N-type epitaxial layer region.

However, such a method has a problem that the number of steps is increased when forming the collector region. In recent years, for example, the literature (1998 IEDM (International Electron D
As disclosed in Technical Digest, p. 213-216), a collector region is formed by high-energy implantation of phosphorus or the like. This is B
This contributes to forming the iCMOS at low cost. Therefore, such a latest technique is applied to the present invention,
A method for forming a shallow trench and a deep trench simultaneously will be described.

[Second Embodiment] FIGS.
(D), FIGS. 5 (e) to (h), FIGS. 6 (i) and (j)
It is sectional drawing which shows 2nd Embodiment (manufacturing process) of this invention. First, as shown in FIG. 4A, a known LOCOS method or an oxide film is buried in a groove in a P-type semiconductor substrate 201 made of silicon to thereby form an element isolation oxide film 204.
Are formed, and the N-type well region 205 and the P-type well region 20 are formed.
6 are formed using a known high energy implantation method.

Next, as shown in FIG. 4B, a gate oxide film 207 having a thickness of 1 to 10 nm is formed on the surface of the substrate, and then polycrystalline silicon having a thickness of 100 to 400 nm is formed.
Amorphous silicon, or to form a conductive film 208 Ru polycrystalline silicon Tona containing impurities.

Next, as shown in FIG. 4C, after a gate electrode formation region is masked using a photoresist (not shown), a gate electrode 209 is formed by using a known anisotropic etching technique. I do. After removing the photoresist, an N-type well region 210 for forming a collector of the bipolar transistor and a P-type diffusion layer region 212 are formed.
And an N-type diffusion layer region 213 and an intrinsic base region 211 are sequentially formed.

Next, as shown in FIG. 4D, after an oxide film (not shown) having a thickness of 50 to 400 nm is formed, the gate electrode 209 is formed using a known anisotropic etching technique.
The oxide film is left only on the side wall of
To form Then, after sequentially forming a high-concentration P-type diffusion layer region 216 and a high-concentration N-type diffusion layer region 217, an oxide film 214 having a thickness of 50 to 200 nm is formed. afterwards,
Using the first photoresist 218, the oxide film 214 located at the portion of the emitter diffusion window of the bipolar transistor and the portion where the shallow trench and the deep trench are to be formed is removed using a known anisotropic etching.

Next, as shown in FIG. 5E, after the first photoresist 218 is removed,
A first conductive film 219 made of 00 nm polycrystalline silicon, amorphous silicon, or polycrystalline silicon containing impurities is formed.

Next, as shown in FIG. 5F, after masking with a second photoresist 220 so as to cover the emitter lead-out electrode and the shallow trench formation region, a known anisotropic etching technique is applied. The second conductive film 219a is formed using the second conductive film 219a. At this time, a groove 221 is formed in a region where a deep trench is to be formed by over-etching.
To form

Next, as shown in FIG. 5 (g), after forming a third photoresist 224, the P-type semiconductor substrate 201 is penetrated through the N-type well region 210 by using a known silicon etching technique. Reaches 1.0 to 5.0 μm
Is formed, and a shallow trench 223 shallower than the N-type well region 210 is formed. At the same time as the formation of the shallow trench 223, the emitter extraction electrode 219b is formed.

The impurity is diffused from the emitter lead-out electrode 219b into the intrinsic base region 211 by the heat treatment such as RTA in the manufacturing process, and the high concentration N-type diffusion layer region 225 is formed.

Next, as shown in FIG. 5H, after the third photoresist 224 is removed, a photoresist (not shown) is formed, and then the channel is removed by ion implantation.
A stopper layer 227 is formed. After removing the photoresist, a first interlayer insulating film 226 having a thickness of 50 to 150 nm and having no thermal fluidity and containing no impurities is formed using a known CVD technique.

Next, as shown in FIG. 6I, a film having thermal fluidity (second interlayer insulating film 228) such as BPSG is formed by the CVD technique.
Deep heat treatment at 50 ° C for about 20 minutes
The trench 122 and the shallow trench 123 are buried.

Finally, as shown in FIG. 6 (j), after planarization is performed by a known CMP technique or a BPSG overall etch-back technique, a contact is opened and, for example, W and TiN / Ti are formed. A contact plug 229 formed of a barrier metal and a metal wiring 230 are formed. As a result, B, which is composed of PMOS and NMOS,
The iCMOS and the NPN transistor are completed.

[Third Embodiment] Next, a third embodiment of the present invention will be described.
An embodiment will be described. In the above-described second embodiment, the collector region is formed by high energy implantation. However, in this case, as disclosed in Japanese Patent Application Laid-Open No. 8-203994, the collector region of the bipolar transistor is formed of a high-concentration N-type buried layer region and an N-type epitaxial layer region. As a result, the impurity concentration of the collector region becomes lower as a whole. Especially N
When the type epitaxial layer region is used, the concentration near the substrate surface is almost uniform, whereas the peak of the impurity concentration exists deeper than the substrate surface with high energy implantation. The concentration is quite low. For this reason, in the second embodiment, the draw-out resistance of the collector resistance tends to increase, and the third embodiment solves such a problem.

FIGS. 7A to 7D and FIGS. 8E to 8E.
(H) and FIGS. 9 (i) and 9 (j) are cross-sectional views showing a third embodiment (manufacturing process) of the present invention. First, FIG.
As shown in (a), a known LOCOS method or an oxide film is buried in a trench in a P-type semiconductor substrate 301 made of silicon to form an element isolation oxide film 304.
An N-type well region 305 and a P-type well region 306 are formed by using a known high energy implantation method.

Next, as shown in FIG. 7B, a gate oxide film 307 having a thickness of 1 to 10 nm is formed on the surface of the substrate, and then polycrystalline silicon having a thickness of 100 to 400 nm is formed.
Amorphous silicon, or to form a conductive film 308 Ru polycrystalline silicon Tona containing impurities.

Next, as shown in FIG. 7C, after the gate electrode formation region is masked using a photoresist (not shown), a gate electrode 309 is formed using a known anisotropic etching technique. I do. After removing the photoresist, an N-type well region 310 for forming a collector of a bipolar transistor and a P-type diffusion layer region 312 are formed.
And an N-type diffusion layer region 313 and an intrinsic base region 311 are sequentially formed.

Next, as shown in FIG. 7D, after an oxide film (not shown) having a thickness of 50 to 400 nm is formed, the gate electrode 309 is formed by using a known anisotropic etching technique.
The oxide film is left only on the side wall of
To form Then, after a high-concentration P-type diffusion layer region 316 and a high-concentration N-type diffusion layer region 317 are sequentially formed, an oxide film 314 having a thickness of 50 to 200 nm is formed, and a first photoresist 318 is used. The oxide film 314 located at the portion of the emitter diffusion window of the bipolar transistor, the portion for forming the shallow trench and the deep trench, and the portion for forming the collector extraction region is removed by using a known anisotropic etching.

Next, as shown in FIG. 8E, after the first photoresist 318 is removed,
A first conductive film 319 made of 00 nm polycrystalline silicon, amorphous silicon, or polycrystalline silicon containing impurities is formed.

Next, as shown in FIG. 8F, after masking with a second photoresist 320 so as to cover the emitter extraction electrode and the shallow trench formation region, a known anisotropic etching technique is used. The second conductive film 319a is formed using the second conductive film 319a. At this time, a groove 321 is formed in a region where a deep trench is to be formed by over-etching.
To form

Next, as shown in FIG. 8 (g), after forming a third photoresist 324, the P-type semiconductor substrate 301 penetrates the N-type well region 310 by using a known silicon etching technique. Reaches 1.0 to 5.0 μm
Is formed, and a shallow trench 323 shallower than the N-type well region 310 is formed in a portion where a collector lead-out region is to be formed. At the same time as the formation of the shallow trench 323, the emitter extraction electrode 319b is formed.

Note that impurities are diffused from the emitter lead-out electrode 319b into the intrinsic base region 311 by heat treatment such as RTA in the manufacturing process, and a high-concentration N-type diffusion layer region 325 is formed.

Next, as shown in FIG. 8 (h), after removing the third photoresist 324, a photoresist (not shown) is formed, and then the channel is removed by ion implantation.
The stopper layer 327 is formed. After removing the photoresist, a first interlayer insulating film 326 having a thickness of 50 to 150 nm and having no thermal fluidity and containing no impurities is formed using a known CVD technique.

Next, as shown in FIG. 9 (i), a film having thermal fluidity (second interlayer insulating film 328) such as BPSG is formed by the CVD technique.
Deep heat treatment at 50 ° C for about 20 minutes
The trench 322 and the shallow trench 323 are buried.

Finally, as shown in FIG. 9 (j), after planarization is performed by a known CMP technique or BPSG overall etch-back technique, a portion where a contact is opened and a collector lead-out region is formed is formed. After the high concentration N-type diffusion layer region 331 is formed, the contact plug 32 formed of, for example, W and a barrier metal composed of TiN / Ti is formed.
9 and a metal wiring 330 are formed.

As described above, in the third embodiment, the portion for forming the collector lead-out region is dug to the same depth as the shallow trench. Therefore, by connecting to the metal wiring near the peak of the impurity concentration of the collector region by high energy implantation, the resistance of the portion where the collector resistance is drawn out can be reduced. The inventors of the present application have conducted an experiment, and found that the collector resistance, which was about 1000Ω in the past, can be reduced up to about 30 to 40% by using this embodiment.
And a collector resistance of 600 to 700Ω can be realized.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described.
A method of manufacturing a CMOS according to the embodiment will be described. In the fourth embodiment, the above-described embodiment is applied to a CMOS portion, a deep trench is formed in a PN isolation portion, and a shallow trench is formed in a source / drain and a portion for taking a well potential. Is what you do.

FIGS. 10 (a) to 10 (c) and FIGS. 11 (d) to
(F) is a sectional view showing a fourth embodiment (manufacturing process) of the present invention. First, as shown in FIG. 10A, a known LOC is formed on a P-type semiconductor substrate 401 made of silicon.
An OS isolation method or an oxide film is buried in the trench to form an element isolation oxide film (not shown). Then, the N-type well region 402, the P-type well region 403, and the P-type diffusion layer region 4
04, the N-type diffusion layer region 405, and the gate oxide film 406
And a gate electrode 407 are formed. FIG.
Is illustrated, but a PMOS provided adjacent to the NMOS can be manufactured in the same procedure.

Next, as shown in FIG. 10B, after an oxide film (not shown) having a thickness of 50 to 400 nm is formed,
The gate electrode 40 is formed using a known anisotropic etching technique.
The oxide film is left only on the side wall of
0 is formed. High concentration P type diffusion layer region 408 and high concentration N
After sequentially forming the mold diffusion layer region 409, the thickness is 50 to
An oxide film 411 having a thickness of 200 nm is formed, and the first photoresist 412 is used to form an oxide film 411 located between a PN isolation portion and a portion at which a source / drain and a well potential are obtained, by a known anisotropic process. It is removed using a reactive etch.

Next, as shown in FIG.
After removing the photoresist 412, the thickness is 100 to
400nm polycrystalline silicon, amorphous silicon,
Alternatively, a first layer made of polycrystalline silicon containing impurities
To form a conductive film 413.

Then, as shown in FIG. 11D, after masking with a second photoresist 414 so as to cover the shallow trench formation region, a second anisotropic etching technique is used to form a second photoresist. Of the conductive film 413a is formed. At this time, a groove 415 is formed in a region where a deep trench is to be formed by over-etching.

Next, as shown in FIG.
Using a photoresist 416 and a well-known silicon etching technique, the PN isolation portion is penetrated through the N-type well region 402 and the P-type well region 403 to reach the P-type semiconductor substrate 401, and has a thickness of 1.0 to 5.0 μm. Is formed. At the same time, a shallow trench 418 shallower than the P-type well region 403 is formed between the source / drain and the portion that takes the potential of the well.

Next, as shown in FIG.
After depositing the interlayer insulating film 419 and the second interlayer insulating film 420, the contact plug 421 and the metal wiring 422 are formed by flattening by etch back or CMP. As a result, an NMOS having a well electrode (the rightmost electrode in FIG. 11F) is completed. Similarly PMO
By making S, a CMOS can be made.

As described above, according to the fourth embodiment of the present invention, a deep trench is formed in a PN isolation portion, and a shallow trench is formed in a device isolation portion between a source / drain and a portion for taking a well potential. A trench is formed. According to the present embodiment, the width of the PN isolation and the width of the element isolation between the source / drain and the portion that takes the potential of the well can be reduced.

[0074]

As described above, according to the present invention, grooves having different depths can be formed at the same time by using the first mask and the second mask in combination. By forming the shallow trench and the deep trench at the same time, it is not necessary to strictly control the mask alignment as in the related art. In particular, in the portion of the bipolar transistor, there is no need to form a deep trench in a shallow trench unlike the prior art, so that there is no need to be concerned about misalignment due to mask alignment. Further, since the size of the element isolation region in the bipolar transistor can be reduced, the area occupied by the transistor can be reduced, and the transistor performance can be improved by reducing the parasitic resistance.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a first embodiment (manufacturing process) of the present invention.

FIG. 2 is a sectional view showing a step continued from FIG.

FIG. 3 is a sectional view showing a step continued from FIG. 2;

FIG. 4 is a cross-sectional view showing a second embodiment (manufacturing process) of the present invention.

FIG. 5 is a sectional view showing a step continued from FIG. 4;

FIG. 6 is a sectional view showing a step continued from FIG. 5;

FIG. 7 is a sectional view showing a third embodiment (manufacturing process) of the present invention.

FIG. 8 is a cross-sectional view showing a step that follows the step shown in FIG. 7;

FIG. 9 is a sectional view showing a step continued from FIG. 8;

FIG. 10 is a cross-sectional view illustrating a fourth embodiment (manufacturing process) of the present invention.

FIG. 11 is a sectional view showing a step continued from FIG. 10;

FIG. 12 is a cross-sectional view showing a conventional example (manufacturing process).

FIG. 13 is a sectional view showing a step continued from FIG. 12;

FIG. 14 is a sectional view showing a step continued from FIG.

FIG. 15 is a cross-sectional view showing a conventional example (manufacturing process).

[Explanation of symbols]

101: P-type semiconductor substrate, 102: high-concentration N-type buried layer region, 103: N-type epitaxial layer region, 104: element isolation oxide film, 105: N-type well region, 106: P-type well region, 107: gate oxide film, 108 ... conductive film, 1
09: gate electrode, 110: high-concentration N-type diffusion layer region, 1
11 ... intrinsic base region, 112 ... P-type diffusion layer region, 11
3 N-type diffusion layer region, 114 oxide film, 115 sidewall, 116 high-concentration P-type diffusion layer region, 117 high-concentration N-type diffusion layer region, 118 photoresist first photoresist,
119 ... first conductive film, 119a ... second conductive film, 11
9b ... Emitter extraction electrode, 120 ... Second photoresist, 121 ... Groove, 122 ... Deep trench, 1
23 ... shallow trench, 124 ... third photoresist, 125 ... high concentration N-type diffusion layer region, 126 ... first interlayer insulating film, 127 ... channel stopper layer, 128
... second interlayer insulating film, 129 ... contact plug, 1
Reference numeral 30: metal wiring, 201: P-type semiconductor substrate, 202: high-concentration N-type buried layer region, 203: N-type epitaxial region, 204: element isolation oxide film, 205: N-type well region, 206: P-type well region , 207 ... gate oxide film,
208 ... conductive film, 209 ... gate electrode, 210 ... N-type well region, 211 ... intrinsic base region, 212 ... P-type diffusion layer region, 213 ... N-type diffusion layer region, 214 ... oxide film, 2
Reference numeral 15: sidewall, 216: high-concentration P-type diffusion layer region, 217: high-concentration N-type diffusion layer region, 218: first photoresist, 219: first conductive film, 219a: second
219b ... Emitter extraction electrode, 220 ...
Second photoresist, 221 groove, 222 deep trench, 223 shallow trench, 224 third photoresist, 225 high-concentration N-type diffusion layer region,
226: First interlayer insulating film, 227: Channel stopper layer, 228: Second interlayer insulating film, 229: Contact plug, 230: Metal wiring, 301: P-type semiconductor substrate, 302: High-concentration N-type filling Embedded region, 303: N-type epitaxial region, 304: isolation oxide film, 305: N
Type well region, 306 ... P-type well region, 307 ... gate oxide film, 308 ... conductive film, 309 ... gate electrode, 31
0 ... N-type well region, 311 ... Intrinsic base region, 312
... P-type diffusion layer region, 313 ... N-type diffusion layer region, 314 ...
Oxide film, 315 ... sidewall, 316 ... high-concentration P-type diffusion layer region, 317 ... high-concentration N-type diffusion layer region, 318 ...
First photoresist, 319 ... first conductive film, 319
a: second conductive film, 319b: emitter extraction electrode,
320 ... second photoresist, 321 ... groove, 322 ...
Deep trench, 323 ... Shallow trench, 3
24, a third photoresist, 325, a high-concentration N-type diffusion layer region, 326, a first interlayer insulating film, 327, a channel stopper layer, 328, a second interlayer insulating film, 329,
Contact plug, 330: metal wiring, 331: high concentration diffusion layer region, 401: P-type semiconductor substrate, 402: N-type well region, 403: P-type well region, 404: P-type diffusion layer region, 405: N-type Diffusion layer region, 406 gate oxide film, 407 gate electrode, 408 high-concentration P-type diffusion layer region, 409 high-concentration N-type diffusion layer region, 410 sidewall, 411 oxide film, 412 first Photoresist, 413: first conductive film, 413a: second conductive film, 414: second photoresist, 415: groove, 41
6 Third photoresist, 417 deep trench, 418 shallow trench, 419 first interlayer insulating film, 420 second interlayer insulating film, 421 contact plug, 422 metal wiring.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8249 H01L 21/76 H01L 21/8222 H01L 21/8238 H01L 27/06-27/092

Claims (13)

(57) [Claims] To 1. A semi conductor substrate, and the desired device isolation region
Forming a step of forming a first mask having a plurality of through holes provided in correspondence with an active element, on the semiconductor substrate, the first conductive film so as to cover said first mask a step of, on the first conductive film, forming a second mask that covers at least one of the through hole on the active element, the second of said first conductive film By etching the portion exposed from the mask and the semiconductor substrate thereunder, the second conductive film of the first conductive film is formed.
Forming a second conductive film comprising a portion covered with a mask;
Rutotomoni, forming a groove in said semiconductor substrate, after removing the second mask, to form a first groove by etching the bottom of the groove, the second conductive film and its By etching the underlying semiconductor substrate, the penetration on the active element
The method of manufacturing a semiconductor device characterized by a step of forming a shallow second groove than the first groove at a position corresponding to the hole. 2. A plurality of active elements are formed on a semiconductor substrate.
Process, on the semiconductor substrate, corresponding to a desired element isolation region
Forming a first mask having a plurality of provided through holes;
And covering the semiconductor substrate with the first mask.
Forming a first conductive film, and forming at least one of the through holes on the first conductive film.
Forming a second mask to cover, and exposing the first conductive film from the second mask.
Part and the semiconductor substrate under it
The first conductive film to form the second conductive film.
Forming a second conductive film comprising a portion covered with a mask;
Forming a groove in the semiconductor substrate, and etching the bottom of the groove after removing the second mask.
To form a first groove,
The second conductive film and the underlying semiconductor substrate are etched.
By doing so, the first shallower than the first groove
Forming a second groove; and filling an insulator in the first and second grooves.
A method for manufacturing a semiconductor device, comprising: 3. A plurality of active elements are formed on a semiconductor substrate.
Forming a desired element isolation region and the active element on the semiconductor substrate.
A plurality of through holes provided in correspondence with the
Forming a mask, and covering the semiconductor substrate with the first mask.
Forming a first conductive film, and forming the through hole on the active element on the first conductive film.
Forming a second mask covering at least one
If, exposed from the second mask of said first conductive film
Part and the semiconductor substrate under it
The first conductive film to form the second conductive film.
Forming a second conductive film comprising a portion covered with a mask;
Forming a groove in the semiconductor substrate, and etching the bottom of the groove after removing the second mask.
To form a first groove,
The second conductive film and the underlying semiconductor substrate are etched.
The penetration on the active element by
A second groove shallower than the first groove at a position corresponding to the hole;
Forming; filling the first and second grooves with an insulator;
A method for manufacturing a semiconductor device, comprising: 4. In any of claims 1 to 3, when removing by etching the second conductive film, by leaving a portion of the second conductive film, the remaining second Using a part of the conductive film as an electrode of the active element. 5. The semiconductor device according to claim 4, wherein the semiconductor device comprises a CMOS and a bipolar transistor.
A method of manufacturing a semiconductor device, which is a BiCMOS configured with a semiconductor device. 6. The device according to claim 5 , wherein the first groove is formed between the CMOS and the bipolar transistor.
And the second groove is formed between the bipolar transistor and the transistor.
A method of manufacturing a semiconductor device, wherein the method is formed between a collector and an emitter . 7. A high-concentration N-type buried layer according to claim 6 , wherein said P-type semiconductor substrate is made of silicon.
Form N-type epitaxial layer region after forming region
Then, a CMOS is formed in the N-type epitaxial layer region.
N-type well region and P-type well region for forming
And a step for each of the N-type well region and the P-type well region.
A gate electrode is formed via a gate oxide film, and the N-type
Bipolar transistor collection in the epitaxial layer region
Forming a high-concentration N-type diffusion layer region for extracting
A P-type electrode is formed around the gate electrode located in the N-type well region.
A diffusion layer region is formed, and a region located in the P-type well region is formed.
Forming an N-type diffusion layer region around the gate electrode;
Step of forming an intrinsic base region in the epitaxial layer region
And form an emitter diffusion window for a bipolar transistor
Region and the emitter and collector of the bipolar transistor
An area for forming a second groove for separating the
For separating the polar transistor and the CMOS
Penetrate in correspondence with each of the regions forming one groove
Forming an oxide film having holes on the P-type semiconductor substrate
A step, after a conductive film is formed to cover the oxide film, the d
The area other than the area where the mitter diffusion window is formed and the second groove
The conductive film other than the region to be formed is removed by etching.
Then, the first groove is formed by over-etching at this time.
Forming a groove in a region in which a high concentration N-type buried layer region is formed by etching.
A first groove reaching the P-type semiconductor substrate, and a high-concentration N-type
Forming a second groove shallower than the buried layer region;
Next, an emitter extraction electrode made of the conductive film is formed.
Forming the second groove and the first groove on the P-type semiconductor substrate.
Forming an interlayer insulating film that fills the trench, and opening the interlayer insulating film and then forming the CMOS and the CMOS.
Connecting the electrodes to each of the bipolar transistors
And a method of manufacturing a semiconductor device. 8. The method according to claim 6 , wherein a CMOS is formed on a P-type semiconductor substrate made of silicon.
N-type well region and P-type well region for forming
And a N-type well region and a P-type region for forming the CMOS.
Gates in each of the well regions through a gate oxide
An electrode is formed, and a bipolar transistor is formed on the P-type semiconductor substrate.
Forming an N-type well region for forming a transistor;
Located in an N-type well region for forming the CMOS
Forming a p-type diffusion layer region around the gate electrode;
N-type diffusion layer area around the gate electrode located in the well region
Region and form said bipolar transistor
For forming an intrinsic base region in an N-type well region for forming
And form an emitter diffusion window for a bipolar transistor
Region and the emitter and collector of the bipolar transistor
An area for forming a second groove for separating the
For separating the polar transistor and the CMOS
Penetrate in correspondence with each of the regions forming one groove
Forming an oxide film having holes on the P-type semiconductor substrate
A step, after a conductive film is formed to cover the oxide film, the d
The area other than the area where the mitter diffusion window is formed and the second groove
The conductive film other than the region to be formed is removed by etching.
Then, the first groove is formed by over-etching at this time.
Forming a groove in a region for forming the first groove, and etching the first groove to reach the P-type semiconductor substrate.
And N for forming the bipolar transistor.
Forming a second groove shallower than the mold well region;
Next, an emitter extraction electrode made of the conductive film is formed.
Forming the second groove and the first groove on the P-type semiconductor substrate.
Forming an interlayer insulating film that fills the trench, and opening the interlayer insulating film and then forming the CMOS and the CMOS.
Connect electrodes to each of the bipolar transistors
And a method of manufacturing a semiconductor device. 9. The method according to claim 6 , wherein a CMOS is formed on a P-type semiconductor substrate made of silicon.
N-type well region and P-type well region for forming
And a N-type well region and a P-type region for forming the CMOS.
Gates in each of the well regions through a gate oxide
An electrode is formed, and a bipolar transistor is formed on the P-type semiconductor substrate.
Forming an N-type well region for forming a transistor;
Located in an N-type well region for forming the CMOS
Forming a p-type diffusion layer region around the gate electrode;
N-type diffusion layer area around the gate electrode located in the well region
Region and form said bipolar transistor
For forming an intrinsic base region in an N-type well region for forming
And form an emitter diffusion window for a bipolar transistor
Extracting area and collector of bipolar transistor
Forming a second groove for forming a bipolar transistor;
Forming first trench for separating transistor and CMOS
Having a through-hole corresponding to each of the
Forming an oxide film on the P-type semiconductor substrate; forming a conductive film so as to cover the oxide film;
The area other than the area where the mitter diffusion window is formed and the second groove
The conductive film other than the region to be formed is removed by etching.
Then, the first groove is formed by over-etching at this time.
Forming a groove in a region for forming the first groove, and etching the first groove to reach the P-type semiconductor substrate.
And N for forming the bipolar transistor.
Forming a second groove shallower than the mold well region;
Next, an emitter extraction electrode made of the conductive film is formed.
Forming the second groove and the first groove on the P-type semiconductor substrate.
Forming an interlayer insulating film that fills the trench, and opening the interlayer insulating film and then forming the CMOS and the CMOS.
Connect electrodes to each of the bipolar transistors
And a method of manufacturing a semiconductor device. 10. The method according to claim 6 , further comprising the step of: connecting the CMOS to the bipolar transistor.
The first groove provided has a channel stopper at the bottom thereof.
A method for manufacturing a semiconductor device, comprising: 11. The method according to claim 4, wherein the semiconductor device is a CMOS . 12. The method according to claim 11, wherein an N-type well region and a P-type well region for forming the CMOS are formed on a P-type semiconductor substrate made of silicon; Well region and P
Forming a gate electrode in each of the type well regions via a gate oxide film, forming a p-type diffusion layer region around the gate electrode located in the n-type well region, and forming a gate electrode located in the p-type well region; Forming an N-type diffusion layer region around the region, separating a region for forming a second trench for separating a source or drain from a well electrode, separating the N-type well region and the P-type well region from each other. Forming an oxide film on the P-type semiconductor substrate, having a through-hole corresponding to each of the regions for forming the first trenches, and forming a conductive film so as to cover the oxide film. Then, the conductive film other than the region where the second groove is formed is removed by etching, and a groove is formed in a region where the first groove is formed by over-etching at this time; Semiconductor base A first groove that reaches the front Symbol N-type and the second groove shallower than the well region, and forming a, the P-type semiconductor substrate, said second groove and said first
Forming an interlayer insulating film filling the trench, and connecting an electrode to the CMOS after opening the interlayer insulating film. 13. The method according to claim 6, wherein the gate electrode has an LDD structure.