JP3322345B2 - Layout method of test element pattern of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of laying out test element patterns of a semiconductor integrated circuit, and more particularly to a method of laying out test element patterns in a test chip formed simultaneously with the present chip on a semiconductor wafer.

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, the number of semiconductor elements integrated on a substrate is increasing year by year. For example,
The storage capacity (the number of bits) of a memory formed on a semiconductor substrate has increased about four times in about three years. Such a large increase in storage capacity is mainly due to the fact that each dimension of a semiconductor device is reduced by approximately 3
This is due to the fact that it has been reduced by a factor of 0.7 every year. In the manufacture of an integrated circuit chip accompanied by such a rapid decrease in dimensions, a chip to be shipped as a product and a test chip for testing the performance of a semiconductor element used in the chip are mounted on a semiconductor wafer. It is common to form them simultaneously.

FIG. 8 shows a general example in which the present chip and a test chip are mounted on one semiconductor wafer.
As shown in FIG. 1A, a large number of actual chips 12 and a small number of test chips 13 are arranged on a wafer 11. As shown in FIG. 1B, the test chip 13 includes test elements 14 that simulate various types of semiconductor elements formed on the chip.

FIG. 9 shows an example of the test device shown in FIG. 8 and shows two types of MOSFETs used in this chip.
In order to evaluate the characteristics of the above, two test elements are formed. The test element A (14A) is formed as a p-channel MOSFET that simulates the p-channel MOSFET of this chip, and the test element B (14B) is an n-channel MOSFET that simulates the n-channel MOSFET of this chip.
Formed as ET. In order to measure the characteristics of the MOSFET test element, as shown in FIG. 9, a probe pad 1 for four terminals of a gate, a drain, a source, and a substrate is used.
5 is required. The probe pad 15 is formed, for example, as a first-layer metal wiring, and is usually 50 × 50 μm ² to
The size is about 120 × 120 μm ² and the distance between them is 5
0 to 100 μm.

FIGS. 10A and 10B are a plan view illustrating the structure of the test element 14A except for a metal wiring layer including a probe pad, and an AA cross-sectional view thereof. The size of the test element itself is the same as the size of the semiconductor element of this chip, and is generally 20 × 20 μm ² or less.

That is, the probe pad 15 is extremely large compared to the size of the test element itself.
The size of the test chip 13 for measuring the FET is
It is substantially determined by the number and size of the probe pads. For this reason, there is an interval of about 200 to 400 μm between the test elements other than the metal wiring layer, and the pattern density of the test elements is extremely smaller than that of the present chip.

Here, the layout and structure of a general chip will be described. FIG. 11 shows a 256M DRAM.
FIG. 3 is a plan view of the present chip using a semiconductor integrated circuit device configured as an example. FIG. 12 is a plan view of the array region of the DRAM of FIG. The DRAM includes four array regions 17 and a peripheral circuit region 16 disposed therebetween.
Consists of The array region 17 is, as shown in FIG.
It comprises a memory cell array area 18, a word driver array area 19, and a sense amplifier array area 20. In a normal DRAM, the memory cell array region 18 occupies 50 to 70% of the area of the chip 12.

FIG. 13A shows a memory cell array region 1
8 is a partially detailed plane, and FIG. 8B is a sectional structural view thereof. In the memory cell array region 18, each layer pattern is densely laid out using the finest design rule.

[0009]

SUMMARY OF THE INVENTION The above conventional chip 1
2 and the test chip 13, the transistor characteristics are different between the MOSFET which is a semiconductor element used in the present chip 12 and the MOSFET which is a test element formed in the test chip 13. There is a problem that it is difficult to measure characteristics.

The first reason for the difference in the characteristics is that FIG.
As shown in (1), in the test chip, the gate length of the MOSFET is not constant in the channel region due to the recess 151 of the gate electrode. The reason why the depression 151 of the gate electrode occurs is as shown in FIG. 10B, due to the shape of the element isolation insulating film 105 formed by the trench isolation method. That is, the recess 1 of the element isolation insulating film in which the height of the element isolation insulating film 105 is lower than the height of the substrate surface.
52 causes a step between the substrate surface and the element isolation insulating film 105. Due to this step, the resist film thickness for forming the gate electrode 107 changes near the step and changes the size of the resist pattern.

The reason why the depression 152 of the element isolation insulating film occurs is due to its manufacturing method and pattern density. DRA
In the manufacturing process of M, first, a mask made of a silicon nitride film is formed in the element region 104 on the p-type silicon substrate 101, and a groove is formed by etching the p-type silicon substrate 101 in a region without the mask. After depositing the silicon oxide film so as to fill the groove, there is a step of shaving the mask portion by a chemical mechanical polishing (CMP) method. At this time, in the case of a test element having a small element region and a large space between adjacent element regions, the silicon oxide film buried in the groove is excessively removed.

The second reason for the different characteristics is that the test element 1
4B, the contact resistance of the peripheral contact 118 connecting the peripheral n-type diffusion layer to the first-level metal wiring, and the bit contact 118 connecting the cell n-type diffusion layer 208 and the first-level metal wiring 219 in the chip 12 to each other. This is different from the contact resistance. MOSF to be measured
The characteristics of the ET include a channel resistance and a parasitic resistance connected in series to the channel resistance. The contact resistance is
Since it is a part of the parasitic resistance, the measured MOSFET characteristics are different if the value is different. The difference in the contact resistance is caused by the fact that the capacitor lower electrode 213 and the capacitor upper electrode 215 serving as capacitors exist in the memory cell region, whereas the test element does not have a corresponding capacitor. And the bit contact depth is different. Here, in the test chip, the contact is shallow because the pattern density of the gate electrode is low.

SUMMARY OF THE INVENTION The present invention has been made to solve the problem of the semiconductor device having different characteristics between the present chip and the test chip in the prior art. An object of the present invention is to provide a layout method of a test element pattern of a semiconductor integrated circuit, in which a difference in characteristics is reduced and an effective test can be performed by a test chip.

[0014]

In order to achieve the above object, a method of laying out a test element pattern of an integrated circuit according to the present invention is to lay out a test element simulating a semiconductor element of the present chip in a test chip. In a layout method of a test element pattern of an integrated circuit, a dummy pattern prohibited area is formed in a test chip, and a pattern in an area corresponding to the dummy pattern prohibited area is removed from a desired pattern of the present chip to form a dummy pattern. And combining the dummy pattern and the test element pattern.

Here, the dummy pattern prohibited area is
To be formed based on the test element pattern of the same layer as the pattern of the simulated chip, to be formed based on the test element pattern of the same layer as the pattern of the simulated chip and the test element pattern of another layer, or , May be formed based on a test element pattern of a layer different from the pattern of the present chip to be simulated. In this case, it is preferable that the dummy pattern prohibited area is determined based on an element pattern constituting the test element pattern.

Further, the element pattern is determined based on a layer formed by the same lithography step as the dummy pattern, is determined based on a layer formed by a lithography step different from the dummy pattern, or It may be determined based on a layer formed by the same lithography step as the dummy pattern and a layer obtained by combining layers formed by different lithography steps.

According to the test element pattern layout method for a semiconductor integrated circuit of the present invention, a dummy pattern can be arranged around a test element pattern without affecting the characteristic measurement of the test element pattern. The difference in characteristics between the semiconductor element and the test element caused by the difference in density can be reduced.

The present inventor has found that the problem that the characteristics differ between the semiconductor element used in the present chip and the test element formed in the test chip is due to the difference in pattern density between the present chip and the test element. In consideration of the difference in the number of existing pattern layers, the pattern density of the test element is made equal to the pattern density of this chip, and at that time, without affecting the characteristic measurement of the test element. I came up with a method of placing a dummy pattern,
The present invention has been completed.

Japanese Patent Laid-Open No. 7-335844 describes a semiconductor device in which a dummy pattern similar to the pattern of the present chip is arranged around a test pattern. No specific method for forming a pattern is described.

In the test element pattern layout method for a semiconductor integrated circuit according to the present invention, each pattern of the test chip is formed by synthesizing a part of the CAD data of the present chip with the CAD data of the test chip. The reason for this is that simply combining the data of the test chip with the data of the present chip causes a problem. In order to prevent such a problem from occurring, only the data of the present chip in a region that does not affect the measurement of the test element is added, and the pattern density of each layer of the test chip and the present chip is made substantially equal. Thus, the difference in characteristics between the present chip and the test chip is reduced.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart showing a procedure for producing CAD data of a test chip for implementing a test element pattern layout method for a semiconductor integrated circuit according to the present invention. 2. Description of the Related Art A semiconductor integrated circuit is formed by combining a number of pattern layers such as an element region, a gate electrode, a contact, and a wiring. FIG. 1 shows a certain A layer among the many pattern layers.

First, design CAD of a test chip before processing
The data (test chip data) D1 of all the pattern layers constituting the data is prepared. Similarly, data (present chip data) D2 of all the pattern layers constituting the design CAD data of the present chip is prepared. Paying attention to one pattern layer A, a data layer necessary for forming the pattern layer A is extracted from the test chip data D1 (step S1), and is set as CAD data D3 of the pattern layer A. Further, a data layer necessary for forming a pattern prohibition region so as not to affect the characteristic measurement of the pattern layer A is extracted (step S).
2). In this case, not only a data layer for the pattern layer A but also a data layer for another pattern layer is extracted as necessary, and the extracted data layer is used as prohibited area formation data D4 for the pattern layer A. A forbidden area of the test chip A layer is formed from the data D4, and is defined as forbidden area CAD data D5.

Separately, each data layer for the pattern layer A of the present chip is extracted (step S4), and is used as CAD data D6 of the pattern layer A of the present chip. From the prohibited area data D5 of the pattern layer A for the test chip and the CAD data D6 of the pattern layer A of the present chip, all the data included in the prohibited area in the pattern of the pattern layer A of the present chip is deleted. By doing this (step S5), the present chip correction data (dummy pattern data) D7 in which the prohibited area data of the pattern layer A of the present chip is deleted is created. The data D7 is combined with the previously created CAD data D3 of the test chip (step S6) to obtain CAD data D8 of the pattern layer A of the test chip.

In the above configuration, the prohibited area data D5 of the pattern layer A of the test element is created so as not to affect the measurement of the test element. From the pattern data D6 of the present chip, the present chip correction data D7 is created by deleting the data portion included in the prohibited area. By synthesizing the CAD data D3 of the test chip and the chip correction data D7, the A of the test chip according to the present invention is synthesized.
The layer data D8 is formed. Hereinafter, the present invention will be described in more detail with reference to specific examples.

As a specific example, a case where the present invention is applied to a DRAM described in the prior art with reference to FIGS. 8 to 13 will be described. That is, an example will be described in which the present invention is applied to the wafer illustrated in FIG. 8A and the p-channel MOSFET test element 14A and the n-channel MOSFET test element 14B illustrated in FIG. 9 are formed on the test chip. .

FIGS. 2A to 2E respectively show pattern layers A
Indicates pattern data used for forming a test chip when an element region is selected. Generally, the element region is the first step in the process of forming an integrated circuit except for the ion implantation process. Therefore, only the element layer pattern of the test element, which is the same layer, is used to form the forbidden area. FIG. 7A shows pattern data D3 having a pattern 104m in the element region of the test element. Since the element region is the first step, the data D5 of the pattern prohibition region (FIG. 9B) is obtained by enlarging the element region pattern 104m of the test element and forming the element region dummy pattern prohibition region 404m. can get. Such pattern enlargement can be easily performed by using a CAD tool. As the size of the enlargement, a value equal to or larger than the minimum element isolation width is selected in a rule for designing the semiconductor integrated circuit. For example, 256MDR
In AM, it is about 0.3 μm.

Next, C of the present chip shown in FIG.
Memory cell pattern 204m in AD data D6
From the element area dummy pattern prohibited area 4 of the data D5
When the pattern within 04m is deleted, the chip correction data D7 shown in FIG. This deletion is also CAD
This can be done easily by using a tool. Thereafter, the pattern data D3 of the test element shown in FIG.
By combining both patterns of the present chip correction pattern data D7 of FIG. 9D, the CAD data D8 for the element region pattern of the test element shown in FIG.
Is obtained. By forming a device area pattern of a test chip on a wafer using a reticle manufactured by the pattern shown in the CAD data D8, the element area pattern shown in FIGS. can get. FIG. 3A is a plan view of the test element 14A, and FIG. 3B is a cross-sectional view of the test elements 14A and 14B along the line AA in FIG. In the element region pattern shown in FIG. 3, there is no step between the p-type substrate 101 and the element isolation insulating film 105, which is caused by the formation of the conventional element region.

FIG. 4 shows the same CAD data as FIG. 2 for the gate electrode forming step performed after the formation of the element region. FIG. 3A shows CAD data D3 having a gate electrode pattern 107m of a test element. FIG. 3B shows the data D5 of the dummy pattern prohibited area together with the method of forming the data D5. Since the formation of the gate electrode is a step subsequent to the element area forming step, the element area pattern 104m of the test element and the gate electrode pattern 1
07m, and these are enlarged as in the previous example to form data D5 for the prohibited area 407. Not only the gate electrode pattern 107m but also the element region pattern 104m
Is used in consideration of a contact connecting the element region and the first-layer metal wiring. That is, in the data D5 of the gate electrode dummy pattern prohibition area, the test element pattern 104m of the data D3 of the element area and the test element pattern 107m of the gate electrode are enlarged by the minimum element separation width to form the prohibition area 407m.

Next, C of the present chip shown in FIG.
From the gate electrode pattern 207m in the AD data D6, the gate electrode dummy pattern prohibited area 4 in the data D5
When the pattern at 07m is deleted, the chip correction data D7A shown in FIG. Here, as shown in FIG. 2D, the gate electrode pattern 2 of this chip is used.
If a gate electrode pattern 207m smaller than the minimum design dimension is generated when the data of the prohibited area is deleted from 07m, the pattern smaller than the minimum design dimension is also deleted as shown in FIG. Thus, the present chip correction data D7B is obtained. If a pattern smaller than the minimum design size is left, it will be difficult to create a reticle, and even if a reticle can be created, an extremely fine pattern will be formed on the wafer, so dust due to pattern peeling It is because it causes. As a result, the density of the gate electrode pattern of the test chip is almost the same as that of the present chip.

Thereafter, C of the test element shown in FIG.
AD data D3 and the present chip correction data D in FIG.
By combining both patterns of FIG. 7B, CAD data D8 of the gate electrode pattern of the test element shown in FIG. By using a reticle having the pattern shown in the CAD data D8 to form a gate electrode pattern on the wafer, the structure shown in FIG.
As shown in (a) and (b), the gate electrode pattern 107 formed on the element region pattern is formed in the test element.
Is obtained.

FIG. 6 shows the same CAD data as FIG. 4 for the layout step of the contact of the test chip. The contact is, as shown in FIG.
It is formed as a test element for a bit contact 217 of a memory cell that connects a first upper metal wiring 219 and a diffusion layer in an element region. FIG.
(A) is a CAD of a contact pattern of a test chip.
This is data D3. To form the contact pattern of the test element, the test element pattern 119m for the first layer metal wiring pattern of the test chip shown in FIG.
Is generated using the CAD data D3 ′ having That is, as shown in FIG. 11C, the test element pattern 119m for the first layer metal wiring is enlarged in the same manner as in the previous example, and the CAD having the first layer metal wiring dummy pattern forbidden area 419m is provided. Let it be data D5.
Data D having contact pattern 217 of this chip
6 ((d) in the same figure), the prohibited area 419m of the data D5
Then, the bit contact of the present chip which slightly overlaps with that of the present chip is removed, and the corrected CAD data D7 of the present chip (FIG. 9E) is obtained. Next, CAD data D8 of the test element pattern is obtained from the test element pattern data D3 and the present chip correction CAD data D7 ((f) in the same figure). From the obtained CAD data D8, test element patterns shown in FIGS. 7A and 7B are formed.

In forming the contact pattern of the test chip, if the contact of the present chip is not deleted in the portion of the forbidden area obtained by the first-layer metal wiring 119m, the first-layer metal wiring in the test chip becomes There is a case where an element region that should not be connected is connected via a contact.

According to the method of the above embodiment, since the pattern density of the test chip is substantially the same as the pattern density of the present chip, for example, as shown in FIG. Does not occur, and the film thickness of the element isolation insulating film becomes constant. As a result, even after the element isolation region is formed, a flat substrate surface can be obtained, and the flat substrate surface does not cause a gate electrode dent in the formation of a gate electrode pattern.

Although the present invention has been described based on the preferred embodiment, the layout method of the test element pattern of the semiconductor integrated circuit according to the present invention is not limited to the configuration of the above embodiment. Various modifications and changes made to the configuration of the above-described embodiment are also included in the scope of the present invention.

[0035]

As described above, according to the test element pattern layout method for a semiconductor integrated circuit of the present invention, when a dummy pattern is formed on a test chip, a dummy pattern prohibited area is formed in the test chip. Therefore, the technique of forming a dummy pattern from a desired pattern of the present chip except for the pattern included in the dummy pattern prohibition area and combining the dummy pattern and the test element pattern is employed, which may affect the characteristic measurement of the test element. , The pattern density between the test chip and the present chip can be made substantially the same, and there is an effect of enabling effective characteristic measurement by the test element.

[Brief description of the drawings]

FIG. 1 is a flowchart of a test element pattern layout method for a semiconductor integrated circuit according to an embodiment of the present invention.

2 (a) to 2 (e) are pattern data used when forming a test element pattern in an element region by the method of FIG. 1;

3A and 3B are element region patterns actually formed based on the test element pattern data obtained in FIG. 2, respectively.

FIGS. 4A to 4F respectively show pattern data used when forming a test element pattern of a gate electrode by the method of FIG.

FIGS. 5A and 5B are gate electrode patterns actually formed by the test element pattern data obtained in FIG. 4, respectively.

6A to 6F are pattern data used when forming a contact test element pattern by the method of FIG. 1;

7A and 7B are contact patterns actually formed based on the test element pattern data obtained in FIG. 6, respectively.

FIGS. 8A and 8B are a plan view of a general semiconductor wafer having the present chip and a test chip, respectively, and FIGS.
The top view of a test chip.

FIG. 9 is a plan view showing an example of a test element formed on a test chip.

FIGS. 10A and 10B are a detailed plan view and a cross-sectional view of a test element, respectively.

FIG. 11 is a plan view of the present chip in a general DRAM.

FIG. 12 is a plan view of an array region of the DRAM in FIG. 11;

13A and 13B are a detailed plan view and a cross-sectional view of the memory cell array of FIG. 12, respectively.

[Explanation of symbols]

 11: Wafer 12: This chip 13: Test chip 14: Test element 15: Probe pad 16: Peripheral circuit area 17: Array area 18: Memory cell array area 19: Word driver array area 20: Sense amplifier array area 101: p-type silicon Substrate 102: p-well 103: n-well 104: element region 104m: element region pattern of test element 105: element isolation insulating film 106: gate oxide film 107: gate electrode 107m: gate electrode pattern of test element 118: peripheral contact 118m: Peripheral contact pattern of test element 119: First-layer metal wiring 119m: First-layer metal wiring pattern of test element 151: Depression of gate electrode 152: Depression of element isolation region 201: p-type silicon substrate 202: p-well 204: element Territory 204m: Element region pattern of memory cell 205: Element isolation insulating film 206: Gate oxide film 207: Gate electrode 207m: Gate electrode pattern of memory cell region 208: Cell n-type diffusion layer 211: First interlayer insulating film 212: Capacitance contact 213: Capacitance lower electrode 214: Capacitance insulating film 215: Capacitance upper electrode 216: Second interlayer insulating film 217: Bit contact 217m: Bit contact pattern of memory cell 219: First layer metal wiring (bit line) 307: Dummy gate electrode 312: Dummy capacitance contact 313: Dummy capacitance lower electrode 314: Dummy capacitance insulating film 315: Dummy capacitance upper electrode 404m: Prohibited area of element area dummy pattern 404m: Prohibited area of gate electrode dummy pattern 407: Prohibited area 407m: Gate electrode dam Prohibited area of the pattern 419m: prohibited area of the first layer metal wiring dummy pattern

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 17/50 H01L 21/822 H01L 27/04

Claims (8)

(57) [Claims] 1. A method of laying out a test element pattern of a semiconductor integrated circuit, in which a test element simulating a semiconductor element of the present chip is laid out in a test chip. Forming dummy pattern data; and removing second pattern data having a size corresponding to the outer shape of the test element pattern from the first dummy pattern data to form second dummy pattern data having a blank data portion. Forming test chip pattern data by inserting pattern data of a test element into the blank data portion of the second dummy pattern data; and arranging the test chip pattern data in a test chip. Testing semiconductor integrated circuits Layout method of element pattern. 2. The test element pattern layout method for a semiconductor integrated circuit according to claim 1, wherein the pattern data of a desired area of the present chip is pattern data of the same layer as a layer forming the test element pattern. 3. The test element pattern of a semiconductor integrated circuit according to claim 1, wherein the pattern data of a desired area of the chip includes pattern data of the same layer and a different layer as a layer forming a test element pattern. Layout method. 4. The test element pattern layout method for a semiconductor integrated circuit according to claim 1, wherein the pattern data of a desired region of the present chip is pattern data of a layer different from a layer forming the test element pattern. 5. The semiconductor integrated circuit according to claim 1, wherein the pattern of the test element forming the blank portion is an element pattern for forming one element forming the test element. Layout method of test element pattern. 6. The method according to claim 5, wherein said element pattern is determined based on a layer formed by the same lithography step as said second pattern data. 7. The method according to claim 5, wherein said element pattern is determined based on a layer formed by a lithography process different from said second pattern data. 8. The layout of a test element pattern of a semiconductor integrated circuit according to claim 5, wherein the element pattern is determined based on a layer formed by the same lithography step and a different lithography step as the second pattern data. Method.