JP3323656B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device for accessing a plurality of banks by connecting a dedicated circuit for a plurality of ways to a storage device having a plurality of banks. In recent years, as a technique for reducing the cost of a printed circuit board, an LSI, or the like, it has been considered to reduce the number of ways of an interleaved bus. For this reason, an m-way operation dedicated circuit (LSI)
Need to correspond to the n-way.

[0002]

2. Description of the Related Art As an information processing apparatus having a conventional circuit dedicated to m-way operation, for example, there is one as shown in FIG. In FIG. 9, reference numeral 1 denotes a storage device, and the storage device 1 has a bank 2 divided into a plurality. The storage device 1 is connected via a bus 3 to an m-way operation dedicated circuit 4 composed of an LSI operating on the m-way.

An access permission signal generation circuit 5 receives a request signal for the bank 2 from the bus 3 and outputs an access permission signal. The m-way operation dedicated circuit 4 outputs a bank access signal to the storage device 1 according to the access permission signal generated by the access permission signal generation unit 5. m-way operation dedicated circuit 4
Has a processor 6, a register 7, an address converter 8, a bus monitor 9, and a bus controller 10. When the processor 6 receives the access permission signal from the access permission signal generation circuit 5, the processor 6 refers to an address corresponding to the request signal in the register 7, converts the address into a bank access signal by the address conversion unit 8, The converted bank access signal is sent to the storage device 1. The bus monitor 9 monitors the access mode of the bus 3.

[0004]

However, in such a conventional information processing apparatus, an m
Since the circuit dedicated to the way operation cannot be connected to the bus operating in the way n, the LSI for the way n must be newly designed. For this reason, there has been a problem that development cost and development man-hour for newly designing an LSI are required.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and forcing an m-way operation dedicated circuit to correspond to an n-way without newly designing an LSI. It is an object of the present invention to provide an information processing apparatus that can be operated in a way and supplements an n-way operation, and can reduce development costs and development man-hours.

[0006]

FIG. 1 is a diagram illustrating the principle of the present invention. The present invention relates to an information processing apparatus for accessing a bank by connecting a storage device having a plurality of banks and a dedicated circuit for a plurality of ways to operate on a plurality of ways via an interleave bus capable of operating on a plurality of ways. A suppression signal generating means for generating a suppression signal of a predetermined cycle based on the bank access signal and the operation way number information;
The inhibition signal and the request signal generated by the inhibition signal generation means are input, and the access permission signal is inhibited for a predetermined cycle by the inhibition signal, so that the multiple-way operation dedicated circuit is activated.
An access permission signal generating means for operating by way is provided.

Further, the present invention is characterized in that when the operation way number information has a value indicating a plurality of ways, the suppression signal generating means does not generate a suppression signal. Also, the present invention provides the bank suppression signal generation unit, wherein the suppression signal generation unit generates a suppression signal by inputting a bank access signal to each bank, and an OR circuit to which each output of the bank suppression signal generation unit is input And an AND circuit to which the output of the OR circuit and the operation way number information are input.

Further, in the present invention, the bank inhibition signal generation unit may include a plurality of flip-flops to which the bank access signal is input, an output of a last one of the flip-flops and the bank access signal. It is characterized by comprising one flip-flop directly inputted, and an OR circuit to which the output of the flip-flop and the bank access signal are directly inputted.

[0009]

According to the information processing apparatus of the present invention having such a configuration, a suppression signal of a predetermined cycle is generated by the bank access signal and the number of operation ways, and the access permission signal is converted to a predetermined cycle by the generated suppression signal. Only the multiple-way operation circuit 15 is operated in one way, and when the inhibition signal is not output, an access permission signal is output to operate the multiple-way operation circuit 15 in multiple ways. By switching to one-way operation, the operation of a certain number of ways can be compensated.
There is no need to newly design an LSI for a certain number of ways.

As a result, development costs and man-hours can be reduced.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 8 are views showing an embodiment of the present invention.
FIG. 2 is an overall configuration diagram showing one embodiment of the present invention. FIG.
In the figure, 11 is a storage device (system storage memory), and the storage device 11 has a bank 12 divided into a plurality.

As shown in FIG. 3, the bank 12 is composed of a bank 0, a bank 1, a bank 2 and a bank 3, and is accessed by bank access signals (BNKU0 to BNKU3). For example, in the 4-way operation, when the bank 0 starts to be occupied, the bank 1 starts to be occupied at the next timing, the bank 2 starts to be occupied at the next timing, and the bank 3 starts to be occupied at the next timing. That is, the banks 0 to 3 are occupied in parallel at certain timings. On the other hand, for example, during the two-way operation, bank 0 occupies 4 slots, and then bank 1 occupies 4 slots.
Bank 0 and bank 1 alternately occupy four slots, such that slots are occupied.

13 is an m-way and an n-way (m> n, m,
This is an interleave bus that can be switched to operate (n is an integer), and the storage device 11 and the m-way operation processing device 14 are connected via the interleave bus 13. The m-way operation processing device 14 includes an m-way operation dedicated circuit 15 composed of an LSI, an access permission signal generation unit 16, and a suppression signal generation unit 17.

The inhibition signal generation means 17 generates an inhibition signal of a predetermined cycle based on a bank access signal from the CPU (not shown) and information on the number of operation ways, which are input via the interleave bus 13, and outputs the signal. That is, the suppression signal generation unit 17 outputs a suppression signal when the operation way number information has a value indicating the n-way, and does not output the suppression signal when the operation way number information has a value indicating the m-way number.

The access permission signal generating means 16 outputs an access permission signal based on the input of the inhibition signal and the request signal (REQ) to the bank 12. That is,
The access permission signal generator 16 does not output the access permission signal when the suppression signal is input, and outputs the access permission signal when the suppression signal is not input. When receiving the access permission signal, the m-way operation dedicated circuit 15 outputs a bank access signal to the bank 12. When there is no input of the access permission signal, the m-way operation dedicated circuit 15 does not output the bank access signal. Bank 1 corresponding to
2 is occupied, and it is recognized that the bank 12 is occupied even if there is a request signal to another bank 12.

Next, FIG. 4 shows an example of the internal configuration of the m-way operation processing device 14. In FIG. 4, reference numerals 18A to 18D denote bank 0 to bank 3 inhibition signal generation units, and the bank 0 to the bank 3 inhibition signal generation units 18A to 18D are connected to the bank 0 from the m-way operation dedicated circuit 15 via the interleave bus 13. Access signals (BNKU0 to BNKU3) are input, respectively.

Bank 0 to bank 3 inhibit signal generator 18A
-18D are two D flip-flops 19 and 20,
It comprises a JK flip-flop 21 and an OR circuit 22A. The bank access signal is sent directly to the OR circuit 22A.
To the K terminal of the JK flip-flop 21, and further to the D flip-flop 19.

The bank access signal input to the D flip-flop 19 is output from the D flip-flop 19 at the next timing, is input to the D flip-flop 20, and is output from the D flip-flop 20 at the next timing. Input to the J terminal of the flip-flop 21,
The output of the JK flip-flop 21 is changed from “1” to “0”. Therefore, bank 0 to bank 3 having three cycles are provided by bank 0 to bank 3 inhibition signal generation units 18A to 18D.
~ Bank 3 inhibit signal is generated.

Reference numeral 22B denotes an OR circuit.
Include bank 0 to bank 3 inhibition signal generators 18A to 18
The bank 0 to bank 3 inhibition signals generated in D are input, and the OR operation outputs the bank 0 to bank 3 inhibition signals. Reference numeral 23 denotes a suppression signal generation unit composed of an AND circuit. The suppression signal generation unit 23 includes an OR circuit 22.
B to bank 3 inhibit signal from B and CP not shown
The operation way number information from U is input. When the operation way number information is a value indicating m-way (when it is 0), the suppression signal generator 23 does not output the suppression signal (SPRQXOK),
The value indicating the number of operation ways indicating two ways (way 2SL,
If (1), a suppression signal is output. The bank 0 to bank 3 inhibition signal generators 18A to 18D, the OR circuit 22B, and the inhibition signal generator 23 constitute the inhibition signal generator 17 as a whole.

Reference numeral 16 denotes an access permission signal generation unit comprising an AND circuit as the access permission signal generation means. The access permission signal generation unit 16 includes a suppression signal generation unit 2
3 and a request signal (REQ0-REQ) from a CPU (not shown) via the interleave bus 13.
When 3) is input and the inhibition signal is "1", the access permission signal is not output, and when the inhibition signal is "0", the access permission signal is output to the m-way operation dedicated circuit 15.

Next, an example of the configuration of the m-way operation dedicated circuit 15 is shown in FIG. In FIG. 5, an m-way operation dedicated circuit 1
5 includes a processor 24, a register 25, an address conversion unit 26, a bus monitoring unit 27, and a bus control unit 28.
The register 25 stores a request signal, an address, data, and the like. When receiving the access permission signal, the processor 24 refers to the address corresponding to the request signal in the register 25 and performs the address conversion in the address conversion unit 26 to generate a bank access signal. The data is sent to the storage device 11 via the interleave bus 13.

When the processor 24 does not receive the access permission signal, it does not generate a bank access signal even if it receives another request signal, and allows the bank 12 to be occupied by the previous bank access signal. The bus monitor 27 monitors the mode (access mode) of the interleaved bus 13. Next, the operation will be described.

First, a four-way operation where m = 4 will be described. The operation way number information is input as a value (signal of 0) indicating four ways from the CPU (not shown) to the suppression signal generation unit 23 via the interleave bus 13 so that the suppression signal (SPRQXOK) is not output. Therefore, the access permission signal generator 16 receives the request signal as usual, and outputs an access permission signal when there is no request signal having a higher priority than the request signal.

FIG. 6 shows a time chart during the four-way operation. As shown in FIG. 6, during the 4-way operation, the way 2SL signal is not output as the operation way number information.
The SPRQXOK signal which is a suppression signal is not output. BNKU0-RE which is a request signal for bank 0
In response to the Q signal, the 4-way operation dedicated circuit 15 uses the BN which is the bank access signal for the bank 0 at the next timing.
It outputs a KU0 signal, which occupies bank 0. BNK at the next timing of the BNKU0-REQ signal
When the U1-REQ signal is output, 4 at the next timing
The BNKU1 signal is output from the way operation dedicated circuit 15, and the bank 1 is occupied. Similarly, BNKU2,3-
The banks 2 and 3 are sequentially occupied by the REQ signal. That is, banks 0 to 3 are occupied in parallel.

Next, the operation when the one-way operation is forcibly performed will be described. In FIG. 4, it is assumed that the BNKU0 signal is output from the m-way operation dedicated circuit 15. As a result, the occupation of the bank 0 starts. The BNKU0 signal is supplied to the bank 0 suppression signal generator 1 via the interleave bus 13.
Input to 8A. The bank 0 suppression signal is generated by ORing the directly input BNKU0 signal and the output of the JK flip-flop 21 with the OR circuit 22A. On the other hand, D
The BNKU0 signal input to the flip-flop 19 is output from the D flip-flop 19 at the next timing, is input to the D flip-flop 20, is output from the D flip-flop 20 at the next timing, and is output from the JK flip-flop 21 at the next timing. Enter the terminal. As a result, "0" is output from the JK flip-flop 21. Thus, the bank 0 inhibit signal is not output after three cycles.

The bank 0 inhibition signal enters the inhibition signal generator 23 via the OR circuit 22B, and is ANDed with the WAY2SL signal to generate an inhibition signal (SPRQXOK). The generated suppression signal is transmitted to the access permission signal generator 16.
Then, the access permission signal generation unit 16 stops outputting the access permission signal. That is, the access permission signal is not output during the three cycles in which the inhibition signal is output. Therefore, even if another request signal is output, bank 0 occupies four slots, and other banks 1 to 3 are not occupied.

FIG. 7 shows a time chart when the one-way operation is forcibly performed. In FIG.
There is a REQ signal requesting access to bank 0 at the timing of (1), and the request signal is
3 and its priority is fourth. Also, R
The EQs 0 to 2 have the first to third priorities. In this case, the access permission for REQ3 is REQ0 to REQ2.
This is a case where there is no request signal with a high priority as described above, that is, a case where the values of REQ0 to REQ2 are 0 and the value of the suppression signal (SPRQXOK) is 0. In (1), the above condition is satisfied.

At the next timing (2), access to bank 0 starts, and bank 0 is occupied. This (2)
BNKU0 signal is output at the timing of
An XOK signal is generated, and no access permission signal is output. Next, at the timing (3), even if an REQ signal requesting access to the bank 1 is received, the SPRQXO
Since the access permission signal is suppressed by the K signal, the bank 0 remains occupied. At the timing of (3), D
There is an output of flip-flop 19.

Next, at the timing of (4), SPRQX is also used.
The access permission signal is suppressed by the OK signal, and the bank 1
In this case, the bank 0 remains occupied. At the timing of (4), the D flip-flop 20
This output inhibits the output of the JK flip-flop 21 at the next timing (5).
The output of the RQXOK signal is prohibited at the next timing (5).

As described above, the BNK at the timing of (2)
The U0 signal is directly input to the K terminal of the JK flip-flop 21, and the output of the D flip-flop 20 at the timing of (4) is input to the J terminal of the JK flip-flop 21, so that the output of the JK flip-flop 21 becomes "0". And B
The SPRQXOK signal is generated by ORing the NKU0 signal and the output of the JK flip-flop 21. As a result, even if there is a request signal for access to the other banks 1 to 3 after the timing of (2), it is recognized that the timings of (2) to (4) are occupied by the bank.

Therefore, at the timing of (5), SP
Since the RQXOK signal is not output and the access permission signal is output, the next request signal for access to the bank 1 becomes valid at the timing (6), the access to the bank 1 starts, and the bank 1 is occupied. . Since the SPRQXOK signal is output during the timings (6) to (8) by the BNKU1 signal at the timing (6), the bank 1 is occupied up to the timings (6) to (9), and (1)
At the timing of 0), the occupation of the bank 2 starts.

That is, bank 0 is occupied by 4 slots, then bank 1 is occupied by 4 slots, then bank 2 is occupied by 4 slots, and then bank 3 is occupied by 4 slots. Thus, the occupation of the banks 0 to 3 is performed every four slots. Thus, the m-way operation dedicated circuit 15 can be operated in one way.

Here, the n-way operation can be supplemented by forcibly performing the one-way operation. m = 4
FIG. 8 shows a time chart of the two-way operation when switching to the two-way operation where n = 2. By inputting the WAY2SL signal to the suppression signal generation unit 23, the SPRQXO
A K signal is generated, and the access permission signal generation unit 16 does not output an access permission signal, and recognizes that the bank 0 is being accessed even when another request signal comes.

Bank 0 is occupied by 4 slots, and then bank 1 is occupied by 4 slots. As described above, by forcibly operating the m-way operation dedicated circuit 15 in one way, it is possible to switch to the two-way operation. That is,
In the two-way operation, the occupation of the bank 1 starts during the occupation of the bank 0. However, as shown in FIG.
Even if the four slots of the bank 1 are occupied after the occupation of the four slots, the two-way operation is performed.

That is, bank 0 is occupied by 4 slots,
Even if the bank 1 is occupied by four slots, the m-way operation dedicated circuit 15 does not care much about the performance degradation, so the two-way operation can be compensated by forcibly switching to the one-way operation. As described above, since the m-way operation dedicated circuit 15 is forcibly operated by one way to compensate for the n-way operation, it is not necessary to newly design an LSI, and the development cost and the number of development steps can be reduced.

[0036]

As described above, according to the present invention, the inhibit signal of the predetermined cycle is generated by the inhibit signal generating means, and the access permission signal is inhibited by the inhibit signal. Is forcibly operated by one way, thereby compensating for the n-way operation.
There is no need to newly design a way LSI, and development costs and development man-hours can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an overall configuration diagram showing one embodiment of the present invention.

FIG. 3 is a diagram showing a bank;

FIG. 4 is a diagram showing an example of the internal configuration of a processing apparatus.

FIG. 5 is a diagram showing a configuration example of a circuit dedicated to m-way operation;

FIG. 6 is a time chart for a four-way operation.

FIG. 7 is a time chart at the time of one-way operation.

FIG. 8 is a time chart for a two-way operation.

FIG. 9 shows a conventional example.

[Explanation of symbols]

11: storage device 12: bank 13: interleave bus 14: m-way operation processing device 15: circuit dedicated to m-way operation 16: access permission signal generation unit (access permission signal generation means) 17: inhibition signal generation means 18A to 18D: bank 0 to bank 3 inhibit signal generator 19, 20: D flip-flop 21: JK flip-flop 22A, 22B: OR circuit 23: inhibit signal generator 24: processor 25: register 26: address converter 27: bus monitor 28: Bus control unit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasutoshi Sakurai 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. 72) Inventor Eiji Kanaya 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-5-20181 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB G06F 12/00-12/06 G06F 13/16-13/18

Claims (4)

(57) [Claims] An information processing apparatus for accessing a bank by connecting a storage device having a plurality of banks and a dedicated circuit for a plurality of ways to operate on a plurality of ways via an interleave bus operable on a plurality of ways. A suppression signal generating means for generating a suppression signal of a predetermined cycle based on the bank access signal and the number of operation ways; a suppression signal and a request signal generated by the suppression signal generation means; For a predetermined cycle, and the dedicated circuit
An information processing apparatus comprising: an access permission signal generating unit that operates on a way. 2. The information processing apparatus according to claim 1, wherein said suppression signal generating means does not generate a suppression signal when said number-of-operations-way information indicates a plurality of ways. A plurality of bank inhibition signal generators for generating an inhibition signal by inputting a bank access signal to each bank; and an OR circuit receiving each output of the bank inhibition signal generator. 2. The information processing apparatus according to claim 1, further comprising an AND circuit to which an output of the OR circuit and the information on the number of operation ways are input. 4. The bank inhibition signal generating unit according to claim 1, wherein the plurality of flip-flops to which the bank access signal is input, and the output of the last flip-flop of the flip-flops and the bank access signal are directly input.
4. The information processing apparatus according to claim 3, comprising: a plurality of flip-flops; and an OR circuit to which an output of the flip-flop and the bank access signal are directly input.