JP3323751B2 - Printing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus, and more particularly to a printing apparatus, in which when a VIDEO circuit transfers print data to an engine unit and simultaneously initializes a drawing memory, the print data is transferred to the engine. The present invention relates to a printing apparatus having a function of efficiently performing memory access by changing an access order (priority) for initialization during and after transfer.

[0002]

2. Description of the Related Art In a conventional printing apparatus, when initializing a drawing memory (for example, clearing to zero) while transferring print data, the printing mechanism becomes complicated and the DMAC becomes complex.
When the number of request channels of the (direct memory access controller) increases, there is a possibility that a failure such as an overflow may occur due to waiting for the end of the request of the other party to the other block accessing the DMAC. If there is a risk as described above, increase the data latch memory of each block (for example, FIFO
Or the like, or the VIDEO data reading operation and the initialization operation are sequentially performed to avoid this danger. In this case, the use efficiency of the memory and the overall processing efficiency have been reduced.

[0003]

Accordingly, the first aspect of the present invention is as follows.
Is to change the access order (priority) to the DMAC at the time of initializing the drawing memory, without lowering the memory use efficiency and the processing efficiency.
An object of the present invention is to provide a printing apparatus that performs initialization efficiently.

[0004]

[0005]

In order to achieve the first object, the present invention provides an input means for inputting print data, a storage means for storing the print data input by the input means, Output means for outputting print data, transfer means for transferring print data to the output means, control means for directly controlling access to the storage means in response to a request signal, and a request signal for the control means A transfer request means for requesting the control means to read the print data stored in the storage means,
A write request signal for requesting a write for initializing the storage means, and the priority assigning means increases the priority of the read request signal while print data of one line is being transferred; When the transfer of one line of print data is completed, the priority of the write request signal is increased, and a printing apparatus is adopted.

[0006]

[0007]

According to the present invention, at the time of initialization of the drawing memory, the period for transferring the print data to the output unit and the period for not transferring the print data are determined.
By changing the priority of memory access for initialization, it is possible to achieve efficient memory access, especially for a system with many sources accessing memory, improve processing efficiency, and reduce unnecessary temporary use. Reduce storage memory.

According to the present invention, when the drawing memory is initialized, the frequency of the memory access for initialization is changed between the transfer period of the print data to the output unit and the period during which the print data is not transferred. The present invention realizes efficient memory access to a system having a large number of sources to be accessed, improves processing efficiency, and reduces unnecessary temporary storage memory.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing main circuits common to each embodiment of the present invention. In FIG. 1, 10
0 is a CPU (Central Processing Unit). 101 is
A work memory (RAM and ROM) for storing a control program and various data and a work area. 102
D directly controls memory access without going through the CPU.
MAC (Direct Memory Access Controller). A drawing memory 103 stores print data. The print data is transferred from the drawing memory 103 to a printing unit (engine unit) 107 via the VIDEO circuit 104. 105 and 106 are VIDEO for DMAC
This indicates that there are many DMA request sources other than circuits.

According to the present invention, when a bus is congested because a large number of DMA request sources are present and performing arbitration, the VIDEO circuit having the highest priority order prints the print data stored in the drawing memory to the engine. A printing apparatus that can efficiently initialize a drawing memory so that another block or the VIDEO circuit itself does not break down due to an overflow or the like when the drawing memory is initialized while transferring the data to the system. Is provided.

(Embodiment 1) FIG. 2 shows a VIDEO circuit and D
FIG. 3 is a block diagram illustrating exchange of signals between MACs. It is assumed that the DMAC circuit 202 (corresponding to 102 in FIG. 1) manages addresses. Note that 201
Is a VIDEO circuit (corresponding to 101 in FIG. 1);
Reference numeral 3 denotes a drawing memory (corresponding to 103 in FIG. 1).

FIG. 3 is a block diagram showing main elements inside the DMAC circuit 201. 302 to 305 are address setting registers. Start addresses are set in these registers from outside these blocks. In FIG. 3, it is assumed that the priority is higher in the order from 302. Numeral 301 denotes a DMAC control main unit, which stores an external DMA request and read /
When a write signal is input, various control signals are generated,
First, an output address is determined by the address selector 310, and then a DRAM control signal such as RAS / CAS is output. Here, when one reading and writing is completed, the count (for example, 4 counts in the case of general burst access) is added to the start address, and the selectors 306 to 309 are switched to the address write back bus. , Address registers 302 to 305
Written back to At this point, one access cycle is completed.

FIG. 4 shows an example of a timing chart between the VIDEO circuit and the DMAC circuit. In FIG. 4, BD is a horizontal synchronization signal output from the engine. LEND is a signal indicating that the transfer of one line of print data has been completed. VDORQ-R / VDOR
QW is a data request signal for read / write (initialization). WNR-R / WNR-W is VDO
This is a read / write signal for the RQ-R / VDORQ-W signal. COMP is VDORQ-R and VDORQ-W
Are signals (signals instructing completion of initialization) when the address values match. PEND is 1
This signal indicates the end of the page. A section from BD to LEND is a section for transferring one line of print data.

In general, the access right of the VIDEO circuit has the highest priority. Here, when the initialization mode (for example, the memory is cleared to zero while transferring the print data) is entered, the read access and the write access for zero clear are performed. Requires twice the access time as compared to the case of only reading. In this section, other blocks such as a drawing circuit for preparing the next print data are frequently accessed. If the highest priority VIDEO circuit takes twice as long an access time, the other blocks such as overflows may occur. The chances are high.

Therefore, according to the present invention, the access of the VIDEO circuit is for reading (VDORQ-R, WNR-R).
And for writing (VDORQ-W, WNR-W), the section in which the VIDEO circuit transfers one line of print data keeps the priority of the initialization access low and transfers one line of print data. Upon completion, the above danger is avoided by prioritizing the initialization operation. In each block, the gate efficiency can be increased by minimizing the number of data latches from the memory (for example, the FIFO is used to avoid a failure such as overflow).
Double the depth of O).

In FIG. 4, symbols VDORQ-R indicate read access. In addition, initialization access VDOR having a low priority follows read access.
QW occurs sparsely. Here, in FIG. 3, the address setting register 302 is an address register for VDORQ-R (address 1), and the address setting register 305 is an address register for VDORQ-W (address 3).

In the initialization mode, VDORQ-W
Until the last address of one line of VDORQ-R is matched, that is, CO is output from the comparator 313 shown in FIG.
The initialization operation is repeated until the MP signal is generated (in other words, until the COMP signal becomes high level and becomes enabled). Until LEND occurs, the comparator 313 compares address 1 of the address register 302 with address 3 of the address register 305 (address 1 is directly input from the address register 302 to the converter 313, and address 3 is Input from the address register 305 via the selector 312). If these addresses do not match, CO
MP is in a disabled state (low level in FIG. 4). If the addresses match, COM
P is enabled (high level in FIG. 4).

LEND occurs, and at this point, COMP
Is disabled (COMP is in an enabled state, and if initialization has been completed, the operation described below will not be performed), the address register 311 (address 2) is output from the VIDEO circuit. , A latch signal ADDLT2 is input to the address register 302, and the current final address (final address of read) 1 is written from the address register 302 to the address register 311 (address 2).
At the same time, the address 3 select signal ADDSEL2 is input to the selector 312, and the selector 312 selects the address 2 (corresponding to the last address 1) of the address register 311 instead of the address 3 from the address register 305. Therefore, hereafter (COMP
Until is enabled), the address 2 (that is, the last address 1) from the address register 311 is input to one input terminal of the comparator 313.

Next, the address 1 select signal ADDSE
L1 is input to the selector 306, and the address 1 latch signal ADDSEL1 is input to the address register 302.
Is written to the address register 302, and is input to the other input terminal of the comparator 313. As a result, the comparator 313 continues to compare the last address 1 of the read with the current address 3 during the write operation.

As described above, the change of the write address is performed by the address register 30 having the highest priority.
2, the initialization operation (write operation) has the highest priority after the occurrence of LEND. Thereafter, the process is executed until the initialization operation is completed, that is, until the write address matches the final address of the read.
In this section (from the occurrence of LEND to the completion of the initialization operation), WNR-R functions as a write signal WNR-W. When initialization is completed up to the final address and COMP occurs, the VIDEO circuit stops operating and ADDSEL
2 is input to the selector 312, and the selector 312 again selects the address 3 in place of the address 2 of the address register 311 and waits for the next horizontal synchronizing signal BD.

It goes without saying that the present invention relates to a mechanism for initializing a VIDEO circuit, and the DMAC circuit may take any form. In the embodiment, the DMAC manages the address, but each block may separately manage the address. In that case, the mechanisms denoted by reference numerals 302, 305, 311 to 313 in FIG. 3 are included in the VIDEO circuit.

(Embodiment 2) In the first embodiment, it is assumed that the initialization operation is completed up to the last address for each child, but the initial operation for the previous one line is required before the next horizontal synchronizing signal BD comes. In some cases, it may not be possible to make it in time. If there is a possibility that there is not enough time for the initialization to be completed by the next BD after the occurrence of the LEND, the address 3 latch enable signal ADDLT3EN is supplied from the VIDEO circuit to this section. The same value is input to the address register 305 and the same value is forcibly written back to the address 3 simultaneously with the write back to the address 1.

FIG. 5 is a timing chart in the case of the second embodiment. If the next BD arrives when the initialization of the previous line is completed, the address register 305 stores
Since the start address has already been set, the initialization of the next line starts from the previous line, and finally the initialization of one page is completed until a vertical synchronization signal indicating the start of printing of the next page comes. Then, the PEND signal of FIG. 5 is output (the COMP signal is enabled). Note that the above-described operation may be performed such that the initialization is completed in a fixed area unit (band unit).

(Embodiment 3) FIG. 6 shows a VIDEO circuit and D
FIG. 3 is a block diagram illustrating exchange of signals between MACs. It is assumed that the DMAC circuit 402 (corresponding to 102 in FIG. 1) manages addresses. Note that 401
Is a VIDEO circuit (corresponding to 101 in FIG. 1);
Reference numeral 3 denotes a drawing memory (corresponding to 103 in FIG. 1).

FIG. 7 is a block diagram schematically showing the inside of the VIDEO circuit, and particularly shows a block of an interface with the DMAC related to the present invention. FIG.
, 502 and 503 are write and read address setting registers. A start address is set in these registers 502 and 503 from outside this block. 501 is an address counter.

A read or write address is loaded into the address counter 501 through the selector 506, and is appropriately incremented for each access. The final address in one access output from the address counter 501 to the DMAC 402 (FIG. 6) is written back to the read address register 503 or the write address register 502 through the selector 504 or 505 by an address write-back path. Reference numeral 508 denotes a FIFO memory for storing DATA obtained by a DMAC request signal issued to the DMAC.

This FIFO is 3/4, 1/2, 1/4
Etc., and the information is DMACI /
It is configured to be sequentially passed to the F control circuit 309. This DMACI / F control circuit 309 includes selectors 504, 505, 506, address counters 501, F
It is a sequencer that controls the IFO 508 and the like. From this, signals such as the DMAC request signal VDORQ to the DMAC are output at appropriate timing. A comparison circuit 507 compares a read address value and a write address value. When both values match, an enable “H” signal is input to the DMACI / F control circuit 309.

FIG. 8 is an example of a basic timing chart between the DMAC and blocks other than the DMAC. First, when the DMAC request signal DREQ is output,
In the first 1 CLK period, the abbreviated with the DMAC request signal of another block is set inside the DMAC, and as shown in FIG. 8, the data enable signal DATAEN is returned to the source of the data request from the rising edge of the second CLK. The block receiving the DATAEN signal reads and writes data with this signal as a trigger.

FIG. 9 shows VIDEO and D related to the present invention.
It is an example of a timing chart between MAC. VDORQ
Is a data request signal of the VIDEO circuit, VDODEN
Is a data enable signal for VIDEO. WN
R is a read / write signal. LEAVE is FI
This flag indicates the remaining amount of the FO, and is enabled when the amount exceeds a predetermined amount (when the remaining amount of the FIFO decreases).

First, when outputting VDORQ, it is necessary to observe the remaining amount flag LEAVE before judging whether to perform access by read or write. FIG. 9A shows a state in which the LEAVE flag is still in the disabled state and the write access operation is started. Here, if VDODEN does not return even after a predetermined arbitration period, it is determined that the VIDEO side has not obtained the data request right, and VDORQ is temporarily disabled at the next falling edge of CLK, and The remaining amount flag LEAVE is checked again. At this time, if the LEAVE flag is enabled, access is performed for reading this time to fill the FIFO. When the read access is performed, the VDOD is not applied even after the appointment section as described above.
Even if EN is not returned, VDORQ is not disabled (FIG. 9-b).

FIG. 10 is an example of a timing chart inside the VIDEO circuit. BD is a horizontal synchronization signal output from the engine. LEND is a signal indicating that the transfer of one line of print data has been completed. COM
P (output of the comparator 507) is an address value of VDORQ-R and VDORQ-W, that is, read address 5
This signal is enabled when the address value of the address 03 and the address value of the write address 502 match. PEN
D is a signal indicating the end of one page. BD to LE
ND is a section for transferring one line of print data.

In general, the access right of the VIDEO circuit has the highest priority. Here, when an initialization mode is entered (for example, the memory is cleared to zero while transferring print data), read access and write access for zero clear are performed. Requires twice as long access time as compared to the case of only reading. In this section, other blocks such as a drawing circuit for preparing the next print data are frequently accessed.
If the highest priority VIDEO circuit takes twice the access time, there is a high possibility that mutual failures such as overflow will occur.

Therefore, according to the present invention, when the VIDEO performs write access to initialize the drawing memory and the access right cannot be immediately obtained due to the DMAC ablation, as described above. Then, VDORQ is once disabled and the remaining amount flag is checked without fail. In the section in which the VIDEO circuit is transferring one line of print data, the number of accesses for initialization is suppressed low, and When the transfer of the print data is completed, the above-mentioned danger is avoided by giving the highest priority to the initialization operation, and the data latch from the memory can be minimized in each block, thereby increasing the gate efficiency. . (For example, double the FIFO depth to avoid a failure such as overflow)

In FIG. 10, the waveform of a solid line of VDORQ indicates a read access, and the waveform of a dotted line indicates a write access. In the section from BD to LEND where print data is transferred, read access is prioritized, and initialization access (dashed line) having a low access right occurs sparsely following the read access. When LEND occurs and transfer of one line of print data is completed, the drawing memory is initialized with the highest priority toward the final address for reading. Here, when the next BD comes, the read access again has the highest priority. When these operations are repeated and the last LEND comes, initialization is performed at once to the last address of the read access, and when COMP becomes enabled, one page ends. And waits for the next vertical synchronization signal.

[0036]

As described above, according to the present invention,
When initializing the drawing memory, by changing the priority of the memory access for initialization between the transfer period of the print data to the output unit and the non-printing period, there are many sources that access the memory, in particular. There are effects of realizing effective memory access to the system, improving processing efficiency, and reducing unnecessary temporary storage memory.

Further, according to the present invention, when the drawing memory is initialized, the memory access frequency for the initialization is changed between the transfer period of the print data to the output unit and the period during which the print data is not transferred. This has the effect of realizing efficient memory access for a system having a large number of sources accessing the memory, improving the processing efficiency, and reducing unnecessary temporary storage memory.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a main circuit of each embodiment of the present invention.

FIG. 2 shows VIDEO and DM according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a signal flow between an AC and a drawing memory.

FIG. 3 is a simplified block diagram of the inside of a DMAC according to the first embodiment;

FIG. 4 is a timing chart of the first embodiment.

FIG. 5 is a timing chart of the second embodiment.

FIG. 6 is a diagram illustrating a flow of signals between a VIDEO, a DMAC, and a drawing memory according to a third embodiment.

FIG. 7 is a diagram illustrating a DMAC in a VIDEO according to the third embodiment;
It is a block diagram which simplified the I / F part.

FIG. 8 is an example of a timing chart for a data request between a DMAC and another block according to the third embodiment.

FIG. 9 is an example of a timing chart for a data request between a DMAC and a VIDEO according to a third embodiment;

FIG. 10 is an example of a timing chart inside a VIDEO of a third embodiment;

[Explanation of symbols]

 100 CPU 102 DMAC 103 Drawing Memory 104 VIDEO Circuit 107 Engine 201, 401 VIDEO Circuit 202, 402 DMAC 203, 403 Drawing Memory 301 DMAC Control Body 302-305 Address Register 306-309 Selector 310 Address Selector 311 Address Register 312 Selector 313 Comparator 501 Address counter 502 Write address register 503 Read address register 504 to 506 Selector 507 Comparator 508 FIFO 509 DMAC I / F control circuit

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification code FI G06F 13/362 510 G06F 1/00 350A (56) References JP-A-7-178972 (JP, A) JP-A-5-35653 (JP, A) JP-A-7-17873 (JP, A) JP-A-2-70465 (JP, A) JP-A-8-207365 (JP, A) JP-A-4-83674 (JP, A) JP-A-5-16452 (JP, A) JP-A-5-274249 (JP, A) JP-A-8-132690 (JP, A) JP-A-8-85240 (JP, A) JP-A-3-94573 ( JP, A) JP-A-60-183627 (JP, A) JP-A-62-128326 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) B41J 5/30 B41J 2/44 G06F 1/24 G06F 3/12 G06F 13/28 310 G06F 13/362 510

Claims (5)

(57) [Claims] An input unit for inputting print data; a storage unit for storing print data input by the input unit; an output unit for outputting print data; and transferring the print data to the output unit. Transfer means, control means for directly controlling access to the storage means in accordance with the request signal, and priority ordering means for prioritizing the request signal to the control means, the transfer means, The control unit supplies a read request signal for requesting reading of print data stored in the storage unit, and a write request signal for requesting writing for initializing the storage unit. While the print data of one line is being transferred, the read request signal is given a higher priority, and when the transfer of the print data of one line is completed, Printing apparatus characterized by a higher priority request signal write attempts. 2. The control unit is a direct memory access controller, the output unit is a printing unit, the transfer unit is a video circuit for transferring print data to the printing unit, and the storage unit is a drawing memory. The printing device according to claim 1, wherein 3. A VIDEO for transferring print data to an engine unit by a direct memory access controller for directly controlling access to a drawing memory for storing print data.
Transfer the print data from the drawing memory to the circuit;
A printing apparatus, wherein an IDEO circuit transfers print data to the engine unit to perform printing, and initializes a drawing memory in parallel with transferring print data from the drawing memory to the VIDEO circuit. The first with the highest access priority to memory
An address register; a second address register having a lower access priority to the drawing memory than the first address register; start signal generating means for generating a start signal indicating the start of printing of one line; Transfer completion signal generation means for generating a transfer completion signal indicating the completion of the transfer of the data, and printing from when the start signal is generated by the start signal generation means until the transfer completion signal is generated by the transfer completion signal generation means. Read request signal supply means for supplying an address indicated by a read signal for requesting data read to the first address register; and, after a transfer completion signal is generated by the transfer completion signal generation means, the print data of the drawing memory is The address indicated by the write request signal requesting the write to be initialized is the second address Printing apparatus characterized by having a write request signal supplying means capable of supplying to the first address instead of the register. 4. A comparison means for comparing an address indicated by the first address register with an address indicated by the second address register, and generating a match signal indicating a match when the addresses match. When the transfer completion signal is generated by the transfer completion signal generating means, and the comparison means does not generate a coincidence signal, the write request signal supply means replaces the second address register with the first address register. 4. The printing apparatus according to claim 3, wherein an address indicated by the write request signal is supplied. 5. If the comparison means does not generate a coincidence signal before the start signal generation means generates the next start signal, the address currently indicated by the first address register is written to the second address register. The printing apparatus according to claim 4, wherein: