JP3323977B2 - Signal switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal switching circuit, and more particularly to a switching circuit for selecting and transmitting signals transmitted through a plurality of transmission lines.

[0002]

2. Description of the Related Art A single signal (hereinafter, referred to as "path signal") obtained by multiplexing a plurality of signals (hereinafter, referred to as "path units") from one signal source.
When transmitting as a signal (section unit), it is general that the transmission path is made redundant and transmitted via separate transmission paths. In this case, after receiving the section unit signal and matching the phases thereof, each signal is monitored, and a normal path unit signal is always selected and output.

A conventional switching device is disclosed in Japanese Patent Application Laid-Open No. 63-9 / 1988.
There is one described in Japanese Patent No. 8259. This device includes a buffer memory that absorbs a signal delay of each input signal, a unit that detects a phase of the input signal, a unit that detects a phase difference of a signal from an output of the phase detection circuit, and a buffer memory that uses the phase difference information. It comprises a means for controlling the write / read address and a selection means for inputting the output of the buffer memory and selecting one of them.

In such a configuration, a signal from a certain transmission line route among a plurality of input signals originally from the same signal source is sequentially written into a buffer memory. In addition, a signal from another transmission line route among a plurality of input signals from the same signal source is sequentially written into another buffer memory.

Next, the frame synchronization circuit synchronizes the signals of the two routes with each other, and outputs a timing pulse indicating the head position of each signal. The timing pulses are compared with each other, and the read / write or both read / write addresses of the buffer memories are controlled so that the output phases of the two buffer memories match.

[0006] Finally, the output signal of the buffer memory having the same phase is input to the selector.

As described above, even if the selector is switched, the continuity of the signal is guaranteed, and the instantaneous interruption switching function can be realized.

Further, as a conventional signal switching circuit, there is a method of monitoring an input signal, detecting an abnormality such as a signal error, and automatically switching an output signal. This will be described with reference to FIG.

Referring to FIG. 1, a conventional signal switching circuit has a phase matching circuit 3 which receives a signal 1 and a signal 2 having a redundant configuration as inputs and outputs the same signal in phase with each other. And a switching control circuit 18 having a control circuit 180 for outputting a switching instruction signal 17 in accordance with the contents of the monitoring outputs 14 and 15 of the monitoring circuits 12 and 13, respectively. It is composed of Also, the conventional signal switching circuit,
A selection circuit 10 for selecting and outputting the output signals 4 and 5 of the phase matching circuit 3 in response to the switching instruction signal 17, and outputting a signal for a time longer than a time required for detecting an abnormality in the monitoring circuits 12 and 13 And delay circuits 6 and 7 for delaying the respective circuits.

The phase matching circuit 3 includes a buffer memory or a register, and adjusts the write timing and the read timing in accordance with the phase detection result to adjust the phases of the signals. The internal configuration of the phase matching circuit 3 will be described later in detail.

In such a configuration, in the case where the input section unit signal is a signal obtained by multiplexing three path unit signals, the operation after the signal is decomposed into path unit signals will be described.

The input signals 1, 2 in units of three paths,
Is input to the phase matching circuit 3 and after the phase is detected,
Written at the detected frame phase. If the read phase of the buffer memory 3 is set to be slower than the phase of all the path unit signals, the phase of all the path unit signals can be matched.

The signals 4 and 5 in the path unit having the same phase are
The signals are input to monitoring circuits 12 and 13 which detect signal errors and abnormalities by known methods such as parity check, CRC error detection, error detection by a path pattern, and signal abnormality notification signal detection, and are monitored for errors and abnormalities. .

At the same time, the signals 4 and 5 in path units having the same phase are input to delay circuits 6 and 7 for delaying the signals by a time longer than a time required for the monitoring circuit to detect an error or abnormality. You. Thereby, the monitoring circuits 12 and 13
In the case where several frames are required to detect an error or abnormality in the above, a signal having an error or abnormality is not selected until the switching instruction signal 17 instructs the selection circuit 10 to switch the selection state in response to the detection.

The output signals 8 and 9 of the delay circuits 6 and 7 are input to a selection circuit 10 to automatically select a signal indicated by a switching instruction signal 17 and output an output signal 11 as a selection result.

Here, the internal configuration of the phase matching circuit 3 will be described with reference to FIG.

In FIG. 1, a phase matching circuit 3 includes a buffer memory 3 in which input signals 1 and 2 are successively written.
1 and 32, phase detection circuits 33 and 34 for detecting the phases of the signals 1 and 2, and a read control circuit 3 for reading the buffer memories 31 and 32 in accordance with the outputs of the phase detection circuits.
5 is included.

In such a configuration, the signal 1 input to the phase matching circuit 3 is input to the buffer memory 31 and also to the phase detection circuit 33. Similarly, the signal 2 is input to the buffer memory 32 and also to the phase detection circuit 34. The phase detection circuits 33 and 34 detect the phases, respectively, and write signals are supplied to the buffer memories 31 and 32 according to the detection results, and each frame is written. The read control circuit 35 receives the detection results of the phase detection circuits 33 and 34 as inputs, and simultaneously supplies a read signal 350 to the buffer memories 31 and 32. As a result, the phases of the signal 4 and the signal 5 output from both buffer memories coincide.

Next, the operation of the conventional signal switching circuit shown in FIG. 9 will be described with reference to FIGS. 11 to 13 are time charts showing an operation example of the conventional signal switching circuit. FIG. 11 is a continuation of FIG. 11 and FIG. 13 is a continuation of FIG.

In these figures, the signals 1-
1, 1-2 and 1-3, and signal 2 which is also an input signal
-1, 2-2 and 2-3, output signals 4-1 4-2 and 4-3 of the phase matching circuit 3 and output signals 5-1 5-2 and 5-2 of the phase matching circuit 3 3 and delay circuit 6
Output signals 8-1, 8-2 and 8-3, output signals 9-1, 9-2 and 9-3 of the delay circuit 7, and output signals 14-1, 14-2 and 14 of the monitoring circuit 12. -3, output signals 15-1, 15-2, and 15-3 of the monitoring circuit 13, and a switching instruction signal 17 from the control circuit 180 to the selection circuit 10.
1, 17-2, and 17-3, and output signals 11-1, 11-2, and 11-3 as selection results of the selection circuit are shown.

In this example, it is assumed that n frames are one multi-frame, and the phases of all the path unit signals are made to coincide with the phase of the two-frame signal after the most delayed path unit signal.

Referring first to FIG. 11, as shown in FIG. 11, signals 1-1, 1-2 and 1-3 and signals 2-1 2-2 and 2-3 are transmitted. The phases of the frames do not match. That is, focusing on the frame 1-1-1 of the signal 1-1, the frame 1-1-1 is originally a frame 1-2-1, a frame 1-3-1, a frame 2-1-1, and a frame 2-1-1. 2-1 and frame 2-3
It should be input at the same timing as -1. However, the frame 1-1-1 in the figure is the frame 1-2- (n-1) of the signal 1-2 and the frame 1-3- of the signal 1-3.
(N-3), frame 2-1-1-n of signal 2-1, signal 2
The frame 2-2 is input at the same timing as the frame 2-2 (n-2) and the frame 2-3- (n-3) of the signal 2-3. Therefore, the signals 1-1, 1-2 and 1-3 and the signals 2-1 2-2 and 2-3 do not have the same phase of the transmitted frames.

However, each signal is supplied to the phase matching circuit 3
And the frame phase is adjusted to the signal with the most delayed phase. Then, as a result of this phase adjustment, the signals are output as signals 4-1 4-2 and 4-3 and signals 5-1 5-2 and 5-3.

At this time, the frame 1-1-1 corresponds to the frame 1-2 of the signal 1-2 input at the same timing.
-(N-1), frame 1-3 of signal 1-3 (n-
3), the frame 2-1-n of the signal 2-1; the frame 2-2 (n-2) of the signal 2-2; and the frame 2-3- (n-3) of the frame signal 2-3. The phase is adjusted to the frame 2-1-n of the signal 2-1 that is a signal whose phase is delayed. As a result, at time t1, the signal 4-
The frame of * (* is any number from 1 to 3, hereinafter the same) is frame 1-**-n, and the frame of signal 5- * is frame 2-**-n.

Further, each signal is converted into two signals by delay circuits 6 and 7.
Frame delayed. For this reason, at time t1, the signal 8- * is the frame 1-*-(n
-2), and the signal 9- * also becomes the frame 2-*-(n-2) two frames earlier.

With the above operation, a signal having the same frame phase is output from the selection circuit 10 in accordance with the switching instruction signal 17. The above-described phase matching operation is similarly performed in FIGS.

Here, it is assumed that the frame of the hatched portion in FIGS. 11 and 12 is abnormal. Such an abnormal state is detected by the monitoring circuits 12 and 13 as described above, and the control circuit 180 operates to control the selection circuit 10 according to the detection result. Under the control of the selection circuit 10, an abnormal signal is switched to a normal signal.

For example, frame 1-2 of signal 1-2
When (n-1) to frame 1-2-2 are abnormal, the monitoring circuit 12 first detects the abnormality of frame 1-2- (n-1). Thus, at time t1, monitoring circuit 1
2 changes from low level to high level. Then, in response to the change of the output signal 14-2, the switching instruction signal 17-2 to the selection circuit 10 changes from the low level to the high level. As a result, the signal 1-2 has been transmitted to the signal 11-2, but is switched to the signal 2-2 instead at time t2. Therefore, the signal 11-2 is changed from the frames 1-2- (n-7) to 1-2- (n-), which are frames on the signal 1-2 side, until time t2.
3) is the content, and after the same time, the frame on the signal 2-2 side is the content.

However, frames 2-2-5 to 2-2-7, which are frames on the signal 2-2 side, are abnormal. Therefore, the output signal 15−
2 changes from low level to high level at time t5 in FIG. 12, and changes from high level to low level at time t8.

On the other hand, the abnormal state of the signal 1-2 is the frame 1
Continue until -2-2, but then frame 1-2-3
Then, it has recovered to a normal state. Therefore, at time t4, the output signal 14-2 of the monitoring circuit 12 changes from the high level to the low level. Then, this output signal 14-
2 in response to the change in the switching instruction signal 17 to the selection circuit 10.
-2 changes from the high level to the low level. As a result, at time t6, the signal 11-2 is switched from the signal 2-2 to the signal 2-1. Therefore, the signal 11-2 is transmitted from the time t2 to the time t6, that is, during the abnormal state, the frame 2-2- (n-
The contents from 1) to 2-2-4 are set as the contents, and after time t6, the frame on the signal 2-1 side is set as the contents again.

Similarly, the signal 1-1 is transmitted to the frame 1-1-2.
To frame 1-1-5 are in an abnormal state, and the output signal 14-1 of the monitoring circuit 12 corresponds to this abnormal state.
Is at a high level from time t3 to time t6.
On the other hand, signal 2-1 is transmitted from frame 2-1-7 to frame 2
The output signal 15-1 of the monitoring circuit 13 is at a high level from time t7 to time t9 in FIG. 13 in response to the abnormal state.

Therefore, the switching instruction signal 17-1 to the selection circuit 10 is at the high level from time t4 to time t7, and the signal 11-2 is the frame 2-1 which is the signal 2-1 side only during that time. The contents are 1-2 to 2-1-5.

The signal 1-3 has an abnormal state from the frame 1-3-2 to the frame 1-3-4. In response to this abnormal state, the output signal 14-3 of the monitoring circuit 12 is changed to an abnormal state. ,
It is at a high level from time t3 to time t5. On the other hand, the signal 2-3 is always in a normal state, and the output signal 15-3 of the monitoring circuit 13 is always at a low level.

Therefore, the switching instruction signal 17-3 to the selection circuit 10 changes from the low level to the high level at time t4, and thereafter remains at the high level. Therefore, time t
After 4, the signal 1-3 has the contents of the frame on the 2-3 side.

[0035]

According to the above-mentioned prior art, even if the content of a signal from a transmission line is a signal obtained by multiplexing a plurality of path-unit signals, the phase of the path unit matches. By doing so, switching can be performed automatically without interruption. However, when switching is performed automatically, there is a disadvantage that it is uncertain which transmission line the output signal at a certain moment is from. On the other hand, a failure in a normal transmission line is not left for a long time, and a signal received from the transmission line rarely continues to be erroneous or remains abnormal.

Therefore, even if all paths are normal at the time of maintenance or the like, the selection state is likely to be different for each path. In some cases, both systems are in operation and cannot be removed or replaced as is.

For example, after the time t7 in FIG. 12, the switching instruction signals 17-1 and 17-2 are fixed at a low level, and the switching instruction signal 17-3 is fixed at a high level. 1 is the signal 1-1 side, the signal 11-2 is the signal 1-2 side, and the signal 11-3 is the signal 2-side.
The three sides are the contents. Therefore, even if maintenance is to be performed in a state where all signals are normal, the buffer memories of both systems are in operation and cannot be removed or replaced as they are. Operation will be interrupted if it is removed or replaced. Therefore, in such a case, it is necessary to confirm the selection status at that time by some method and to forcibly specify a transmission path to be selected.

In such a case, a method of notifying the maintenance operator of the selection status, such as displaying the operating buffer memory or the like by lighting a lamp or the like, is also conceivable. However, a package serving as a unit for removal and replacement usually includes a plurality of buffer memories, and even if such a display is performed, removal and replacement cannot be performed after all.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a signal switching circuit capable of facilitating maintenance such as removal and replacement of a package. .

[0040]

The signal switching circuit according to the present invention comprises first to Nth (N is a positive integer) signal sources which are respectively transmitted and input via circuit elements which can be inserted and removed. A selection circuit for selecting and transmitting an arbitrary signal from among the first to Mth (M is an integer of 2 or more) signals for each of the first to Nth signal generation sources, wherein the signal being transmitted is in an abnormal state A signal switching circuit that selects and sends another signal from the same signal source instead of when the signal becomes, and is selected from the first to Mth signals when the abnormal state is recovered. A control means for controlling the selection circuit so as to select and transmit the L-th signal (L is any number from 1 to M) having the largest number of signals for each of the first to N-th signal generation sources. It is characterized by including.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.

When recovering from the abnormal state, the L-th signal (L is 1) having the largest number of signals selected from the first to M-th signals
(The number of any one of .about.M) for each of the first to Nth signal generation sources and controls the selection circuit. Alternatively, when recovering from the abnormal state, a predetermined K-th signal (K is any number from 1 to M) is transmitted to the first to N-th signals.
Are selected and transmitted.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a signal switching circuit according to the present invention, and the same parts as those in FIG. 9 are denoted by the same reference numerals. In the figure, a signal switching circuit according to an embodiment of the present invention is different from the circuit of FIG. 9 in that a protection circuit 161 for confirming recovery from an abnormal state in the switching control circuit 16 and a switching instruction signal 17 The difference is that a majority circuit 162 for performing a majority decision and a control circuit 160 for transmitting the switching instruction signal 17 in accordance with the contents of these output signals are provided.

Here, as shown in FIG. 2, the protection circuit 161 receives the output signal of each monitoring circuit as an input, and the shift register 163 receives the output signal of each stage of the shift register 163 as an input. The shift register 163 performs a shift operation in accordance with a frame clock.

In such a configuration, the shift register 16
The output of the AND circuit 164 becomes high level only when the values of all the stages 3 become high level. For this reason,
When the shift register 163 performs a shift operation, the signal becomes abnormal, and then returns to a normal state, and if a clock corresponding to the monitoring cycle of the monitoring circuit is inputted by the same number as the number of stages of the shift register 163, the clock becomes Only when the normal state continues for a corresponding time, it is determined that the signal has recovered, and the output of the AND circuit 164 goes high.

The protection circuit 161 is provided corresponding to each output signal of the monitoring circuit.

As shown in FIG. 3, the majority decision circuit 162 includes AND circuits 165-1 to 165-1 for inputting two different switching instruction signals 17-1 to 17-3.
65-3 and these AND circuits 165-1 to 165-3
And an OR circuit 166 which receives the output of the switch as an input, and outputs a signal in accordance with the result of majority decision of three switching instruction signals 17-1 to 17-3.

In such a configuration, the switching instruction signal 17-
At least 2 of 1 to 17-3 (that is, majority)
Is high level, AND circuits 165-1 to 165
-3 at least one output signal becomes high level,
The output signal of the OR circuit 166 becomes high level. vice versa,
If at least two (that is, the majority) of the switching instruction signals 17-1 to 17-3 are at a low level, all the output signals of the AND circuits 165-1 to 165-3 are at a low level, and the output signal of the OR circuit 166 is output. Becomes low level.

In FIG. 3, the number of switching instruction signals, which are input signals of the majority circuit, is "3". However, if the number of switching instruction signals is more than 3, the majority circuit can be similarly configured. For example, when the number of switching instruction signals is "5", 10 AND circuits are provided, the number of inputs of each AND circuit is set to "3" (that is, the majority), and the outputs of all AND circuits are output to one OR circuit. If input, the output of the OR circuit will be the result of majority decision.

Next, the internal configuration of the control circuit 160 will be described with reference to FIG.

In the figure, a control circuit 160 is provided with a NAND circuit 17 having the output signal 14 of the monitoring circuit 12 as one of its inputs.
3, a NAND circuit 174 having one of the inputs of the output signal 15 of the monitoring circuit 13, an AND circuit 167 having the output signals of all the protection circuits as inputs, and monitoring of the monitoring circuit having the output signal of the AND circuit as an input. Clock CLK corresponding to cycle
Shift circuit 168 that performs a shift operation in accordance with the above, an AND circuit 169 that receives the output signal of each stage of the shift register 168 as an input, and a NAND circuit that receives the output signal of the AND circuit 169 and the output signal 1660 of the majority circuit 162 as inputs 170, the output of the AND circuit 169 and the majority circuit 16
And a NAND circuit 171 to which the inverted value of the output signal 1660 of the second circuit is input. 172 is an inverting circuit.

In this configuration, since the NAND circuit 173 and the NAND circuit 174 each use the output of the other as one of the inputs, these NAND circuits 173 and 174
Will constitute a well-known set-reset flip-flop. The output signal of the NAND circuit 170 is input to the NAND circuit 173, and the output signal of the NAND circuit 171 is input to the NAND circuit 174.

Therefore, the signals 14 and 15 from the monitoring circuit
In addition, the level of the switching instruction signal 17 changes according to the output signal of the protection circuit. That is, when the output signals of all the protection circuits become high level after the abnormal state, the output of the AND circuit 167 also becomes high level,
Further, the output of the AND circuit 169 goes high only when the output of the AND circuit 167 stays high for a certain period of time.

The output signal 16 of the majority circuit is output only when the output of the AND circuit 169 is at the high level.
The level of the switching instruction signal 17, which is the output signal of the reset flip-flop by the NAND circuits 173 and 174, changes according to the level of 60. In other words, if all signals in section units return to normal from the current selection state and the monitoring result of the signals, a majority decision of the selection state is taken, and among the signals in section units, the signals with more signals in the selected path unit are selected. The selection circuit is controlled so as to make a selection. As a result, a signal of one system can be selected, and a buffer memory of an unselected system can be removed and replaced.

It is apparent that a predetermined signal may be selected and transmitted for each of all signal generation sources when an abnormal state is recovered without providing a majority decision circuit. By predetermining in this way, not only is the majority circuit unnecessary, but also in the event that majority is not satisfied (when the number of signals is an even number and the number of selection circuits in different selection states is the same), one system is surely provided. Can be selected.

For example, when the current system and the standby system are composed,
If the working system is designated in advance, if all of the previously designated section-based signals are restored to normal, the designated section-based signal can be selected.

Returning to FIG. 1, the operation of the signal switching circuit having such a configuration will be described with reference to FIGS. 5 to 7 are time charts showing an operation example of the conventional signal switching circuit. FIG. 5 is a continuation of FIG. 5, and FIG. 7 is a continuation of FIG. In FIGS. 5 to 7, FIGS.
Are denoted by the same reference numerals. 5 to 7
13 differs from the operations shown in FIGS. 11 to 13 in that the switching instruction signal 17-3 changes from a high level to a low level at time t10 in FIG. . Due to the change of the switching instruction signal 17-3, the signal 11-3 has the content of the signal 1-3 after the time t10.

That is, in the conventional circuit, the level of the switching instruction signal does not change if the signal of the currently selected system does not become abnormal even if the normal state is restored from the abnormal state, and the current selected state is changed. Had been maintained. On the other hand, in the present circuit, when the system recovers from the abnormal state and returns to the normal state, the level of the switching instruction signal changes so as to select the system with the largest number of selected signals, and the same system is selected. is there.

That is, the result of the majority decision when the abnormal condition is recovered among the M signals of the first to M-th signals respectively transmitted from the N signal sources of the first to N-th signals The control is performed so that the L-th signal having a large number of selected signals among the M signals is selected and transmitted for each of the first to N-th signal generation sources. When the majority decision is not made, the control is performed so that a predetermined K-th signal is selected and transmitted for each of the first to N-th signal generation sources. Therefore, when a majority decision is made and a predetermined signal is selected, maintenance or the like of an unselected system can be performed, and a package or the like of the buffer memory can be removed and replaced. .

FIG. 8 is a block diagram showing the configuration of another embodiment of the signal switching circuit according to the present invention. The same parts as those in FIGS. 1 and 9 are denoted by the same reference numerals. In the figure, the signal switching circuit according to one embodiment of the present invention differs from the circuit of FIG. 1 in that monitoring circuits 12 and 13 are connected to the input side of the phase matching circuit 3 and no delay circuit is provided. is there.

That is, in the configuration of FIG. 1, since a monitoring circuit for monitoring the normality of the signal after the phase matching is provided, if the switching is performed while the signal is in a normal state, the monitoring circuit detects the abnormality of the signal. It is necessary to delay the signal by a time corresponding to the time required to perform the operation. On the other hand, in the configuration of FIG. 8, since the signal is monitored before executing the phase matching, the amount of delay can be adjusted by the buffer memory in the phase matching circuit, so that the delay circuit becomes unnecessary. However, in the case of FIG. 8, as in the case of FIG. 1, it is necessary to delay the monitoring circuit by a time that is longer than the time during which a signal abnormality can be detected.

Therefore, according to the circuit of this embodiment, a delay circuit is not required, and a signal switching circuit can be realized with a simpler configuration.

In each of FIGS. 1 and 8, the protection circuit 161 is provided in the switching control circuit 16 for judging the monitoring result. Can be prevented from becoming unstable.

Further, even when a signal is input via a circuit component which can be inserted and removed other than the package of the buffer memory, the circuit component can be easily maintained according to the present circuit. .

[0066]

[0067]

[0068]

As described above, the present invention selects a signal of one system by switching a signal according to the result of a majority decision or according to a content specified in advance when recovering from an abnormal state. Therefore, there is an effect that maintenance such as removal / replacement of a non-selected system package can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a signal switching circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a protection circuit in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of a majority circuit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a control circuit in FIG. 1;

FIG. 5 is a part of a time chart showing the operation of the signal switching circuit according to the embodiment of the present invention.

FIG. 6 is a part of a time chart illustrating an operation of the signal switching circuit according to the embodiment of the present invention.

FIG. 7 is a part of a time chart showing the operation of the signal switching circuit according to the embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a signal switching circuit according to another embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional signal switching circuit.

FIG. 10 is a block diagram illustrating an example of an internal configuration of a phase matching circuit.

FIG. 11 is a part of a time chart showing an operation of a conventional signal switching circuit.

FIG. 12 is a part of a time chart showing the operation of the conventional signal switching circuit.

FIG. 13 is a part of a time chart showing the operation of the conventional signal switching circuit.

[Explanation of symbols]

 3 phase matching circuit 6, 7 delay circuit 10 selection circuit 12, 13 monitoring circuit 160 control circuit 161 majority decision circuit 162 protection circuit

Continuation of the front page (72) Inventor Koichi Inoue 3-18-21 Shibaura, Minato-ku, Tokyo Nippon Electric Engineering Co., Ltd. (56) References JP-A-7-95186 (JP, A) JP-A-7-95 202857 (JP, A) JP-A-4-68932 (JP, A) JP-A-5-37424 (JP, A) JP-A-7-131525 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00 H04L 1/22 H04B 1/74 H04L 7/00

Claims (2)

(57) [Claims] 1. A first to an Mth (M is an integer of 2 or more) which are respectively transmitted from first to Nth (N is a positive integer) signal generation sources and input through circuit components which can be inserted and removed. And a selection circuit for selecting and transmitting any one of the signals from the first to Nth signal generation sources, and when the signal being transmitted becomes abnormal, the same signal generation source is used instead. And a signal switching circuit for selecting and transmitting another signal, wherein when the recovery from the abnormal state, the L-th signal having the largest number of selected signals among the first to M-th signals (L is 1 to A signal switching circuit for controlling the selection circuit so as to select and transmit the (M number of signals) signals for each of the first to Nth signal generation sources. 2. The signal switching circuit according to claim 1, wherein the control unit determines that the abnormal state has been recovered from the abnormal state only when the normal state continues for a predetermined time after the abnormal state has been entered.