JP3324946B2 - MIM capacitor and its manufacturing method, and semiconductor device and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MIM capacitor, a method of manufacturing the same, and a semiconductor device having the MIM capacitor mounted thereon, and more particularly, to a SrTiO as a dielectric layer.
_{The present} invention relates to a structure of an upper electrode of a MIM capacitor having _three layers and a method of forming the upper electrode.

[0002]

2. Description of the Related Art Conventionally, in a high-frequency device using GaAs as a semiconductor material, for example, a microwave monolithic IC (MMIC) or the like, a capacitor for cutting a DC component or a bypass for passing a signal to a ground line. A huge capacitor is required as the capacitor, and sometimes the area occupied by the capacitor on the substrate of such a high-frequency device is 30 to 5 times the chip area.
May be up to 0%.

On the other hand, metal oxides such as SrTiO ₃ have a higher relative dielectric constant than silicon oxide (hereinafter SiO ₂ ) or silicon nitride (hereinafter SiNx) used as a dielectric material in conventional semiconductor devices. It is known that the capacitor area can be reduced to 1/10 to 1/60.

For this reason, in the field related to the conventional high-frequency device, mounting a capacitor having a dielectric layer made of a metal oxide on a chip requires cost reduction such as reduction in chip cost. Was indispensable.

[0005] For example, as a capacitor using such a high dielectric material, IEICE technical report TECHNICAL REP
ORT OF IEICE. ED93-165, MW9
3-122, ICD93-180 (1994-01),
p55-p60 are those disclosed in "high dielectric SrTiO ₃ Application to GaAs-IC process of a thin film capacitor according to the low-temperature sputtering".

Here, in order to obtain a stable interface characteristic between the metal layer and the insulating layer in the capacitor in the temperature rising process after the formation of the capacitor, the upper electrode and the lower electrode constituting the capacitor are , SrTiO ₃ (hereinafter, S
Abbreviated as TO. ) And the electrode material of the capacitive element need to be selected, and the lower electrode is made of a thermally stable noble metal, Pt.
Also, as a constituent material of the upper electrode, WSi is used instead of Pt.
N is used, and the following points are cited as the reason.

One is Au / Ti used for IC wiring.
When Al, Ni, or the like is used as a constituent material of the upper electrode, heat generated during the p-CVD process for forming the SiN protective film or the like causes an increase in leakage current in the capacitor.

The other is that Pt which is thermally stable is
This is because the adhesion to the STO is poor, and the reliability is uneasy. More specifically, since the upper electrode is usually formed by forming a STO layer as a dielectric layer and then performing vapor deposition lift-off on the STO film, if the upper electrode is made of Pt, There is a risk that the electrode will peel off from the STO film.

[0009] The lower electrode does not have a problem of adhesion to a dielectric layer such as STO formed thereon. Because the dielectric layer formed on the lower electrode is selectively etched and patterned using an etching mask, when patterning the dielectric layer, a force is applied in a direction to peel the dielectric layer from the lower electrode. Because it does not work.

[0010] From the above, according to the technique described in the above-mentioned literature, the constituent material of the upper electrode is thermally stable,
Moreover, by using a material (WSiN) having good adhesion to STO, the leakage current due to the heat treatment is reduced and the reliability is improved.

[0011]

However, in particular, GaAs
In sMMIC, Pt-based electrodes are often used.
For this reason, if Pt is sufficient for the electrode material of the capacitor, the process of forming the electrode of the capacitor is G
Although the compatibility with the aAs-IC process is very good, when a capacitor electrode is formed using WSiN or the like, a new film forming apparatus is required and the number of electrode forming steps is increased. .

Even so, when the upper electrode of a capacitor using STO as a dielectric material is made of Pt, a thermally stable interface characteristic between the dielectric layer and the upper electrode is obtained. However, the adhesion between the upper electrode and the dielectric layer is degraded, which leads to the problem of the reliability of the capacitive element and the semiconductor device mounted with the capacitive element.

When the upper electrode of the capacitor is composed of only the Pt layer, the specific resistance of Pt itself is higher than that of a low-resistance metal such as Au. To reduce the power loss in the capacitor. Incidentally, when the upper electrode of the capacitor is composed of only the Pt layer, the thickness of the Pt layer needs to be about 3000 Å.

However, the upper electrode Pt of the capacitor
If the thickness of the layer is increased, the adhesion with the STO layer, which is a dielectric layer, is further deteriorated in exchange for a reduction in resistance, which is a great obstacle in securing the reliability of the element.

If Pt is deposited on the underlying member in the form of microcrystals, the adhesion between the Pt layer and the underlying member can be improved.
In the deposition of t, the energy is large and deposition in a microcrystalline state is impossible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to improve the adhesion between a dielectric layer made of STO and an upper electrode on the dielectric layer, and to improve the dielectric properties of the dielectric layer. An object of the present invention is to provide an MIM capacitor capable of suppressing an increase in leakage current due to a temperature raising process to a small amount, by making the interface characteristics between a layer and an upper electrode thermally stable, and a method of manufacturing the same.

According to the present invention, the area occupied by the MIM capacitor on the substrate can be reduced, and the adhesion between the dielectric layer constituting the capacitor and the upper electrode and the deterioration of the interface characteristics can be avoided. And maintain the consistency between the IC process and the capacitor formation process.
It is another object of the present invention to provide a semiconductor device capable of suppressing an increase in leakage current in a capacitor due to a heat treatment process.

[0018]

The MIM capacitor according to the present invention (claim 1) has a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode.

The dielectric layer is made of a high dielectric material S
It is composed of rTiO ₃ . An upper electrode provided on the dielectric layer in close contact therewith has a multilayer structure including a Pt layer formed on the surface of the dielectric layer and a Ti layer formed on the Pt layer. And the multilayer structure of gold
In the genus layer, heat treatment in air or nitrogen
Of Ti and Pt formed at the interface between the Ti layer and the Pt layer
Contains intermetallic compounds . Thereby, the above object is achieved.

According to a second aspect of the present invention, in the MIM capacitor according to the first aspect, the upper electrode is formed of the TiM.
It has an Au layer formed on the layer .

According to a third aspect of the present invention, in the MIM capacitor according to the first aspect, the upper electrode includes the Ti electrode.
A second Pt layer formed on the layer, and a second Pt layer formed on the second Pt layer.
And the formed Au layer .

[0022]

The present invention (claim 4 ) has a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode.

The dielectric layer is made of S, which is a high dielectric substance.
It is composed of rTiO ₃ . An upper electrode provided on the dielectric layer in close contact therewith has a multilayer structure including a Pt layer formed on the surface of the dielectric layer and an Au layer formed on the Pt layer. It has become. Thereby, the above object is achieved.

[0025]

The present invention (claim 5 ) is a method for manufacturing an MIM capacitor having a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode.

The step of forming the dielectric layer includes a step of depositing SrTiO ₃ on the lower electrode to form a metal oxide layer constituting the dielectric layer. The step of forming the upper electrode includes the steps of depositing Pt on the dielectric layer by electron beam evaporation to form a Pt layer constituting the upper electrode, and forming Ti on the Pt layer by electron beam evaporation. Depositing to form a Ti layer constituting the upper electrode ;
The Ti layer and the Ti layer are heat-treated in air or nitrogen.
An intermetallic compound of Ti and Pt is formed at the interface with the Pt layer.
The process . Thereby, the above object is achieved.

[0028]

According to a sixth aspect of the present invention, in the method of manufacturing an MIM capacitor according to the eighth aspect, the heat treatment after the formation of the upper electrode is performed at a temperature in the range of 200 ° C. to 500 ° C.

The present invention (claim 7 ) is a method for manufacturing an MIM capacitor having a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode.

The step of forming the dielectric layer includes a step of depositing SrTiO ₃ on the lower electrode to form a metal oxide layer constituting the dielectric layer. The step of forming the upper electrode includes the steps of depositing Pt on the dielectric layer by electron beam evaporation to form a Pt layer constituting the upper electrode, and forming Au on the Pt layer by electron beam evaporation. And forming an Au layer constituting the upper electrode.

A semiconductor device according to the present invention (claim 8 ) includes a plurality of MIM capacitors formed on a semiconductor substrate and having a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode. I have.

Then, the plurality of MIM capacitors are connected to one of the lower electrodes formed on the semiconductor substrate in the same step.
And the high dielectric layer made of SrTiO ₃ in Katanokami, first MI are sequentially formed and an upper electrode formed on the high dielectric layer
And M capacitor has a dielectric layer composed of SiN on the other of the lower electrode, and a second MIM capacitor are sequentially laminating a top electrode formed on the dielectric layer.

The method for manufacturing a semiconductor device according to the present invention comprises:
Formed on a semiconductor substrate, a method of manufacturing a semiconductor device in which a plurality have a MIM capacitor formed by sandwiching a dielectric layer structure between the lower electrode and the upper electrode, the first and second
Forming a lower electrode of the second MIM capacitors, respectively, one of the high dielectric layer was formed consisting of SrTiO ₃ on the lower electrode, a first of the upper electrode are sequentially formed on the high dielectric layer Forming a MIM capacitor; and forming a second MIM capacitor by forming a dielectric layer made of SiN on the other of the lower electrodes and forming an upper electrode on the dielectric layer. Inclusive.

Hereinafter, the operation of the present invention will be described.

In the present invention (claim 1), the MIM
Since the dielectric layer of the capacitor is made of STO (SrTiO ₃ ), which has a higher relative dielectric constant than silicon oxide or silicon nitride usually used in semiconductor devices, the area occupied by the MIM capacitor on the substrate is reduced. It can be dramatically reduced. Moreover, since the upper electrode on the dielectric layer has a multilayer structure including the Pt layer on the surface of the dielectric layer and the Ti layer thereon, the Pt layer is structurally supported by the Ti layer thereon. The Pt layer for obtaining a thermally stable interface characteristic between the upper electrode and the STO layer as a dielectric layer can be formed thin enough to obtain sufficient adhesion with the STO layer. it can. In other words, a Pt layer that is stable against heat suppresses an increase in leakage current due to heat treatment after the formation of the upper electrode, and improves the adhesion to the STO layer by thinning the Pt layer, thereby improving the reliability as an element. Can be enhanced. Further, the upper electrode is
Heat in air or nitrogen in a multi-layer metal layer
Formed at the interface between the Ti layer and the Pt layer by the treatment.
The structure containing the intermetallic compound of Ti and Pt
Due to the presence of the intermetallic compound, STO during heat treatment
Occurrence of oxygen atom defects in the layer will be suppressed,
To further suppress the increase in leakage current due to heat treatment
Can be.

In the present invention (claim 2), the above
The unit electrode has an Au layer formed on the Ti layer.
Since that, the suppression of the leakage current increases due to the heat treatment,
In addition to improving the adhesion between the upper electrode and the dielectric layer, it is possible to lower the resistance of the upper electrode, thereby reducing power loss in the capacitor.

Further, since the surface of the Ti layer is covered with the Au layer, depending on the thickness of the Ti layer, the surface of the Ti layer is oxidized by a trace amount of oxygen in the atmosphere when heat treatment is applied, and the wiring formed thereon is formed. Can be solved.

In the present invention (Claim 3), the upper electrode includes a second Pt layer formed on the Ti layer,
Having an Au layer formed on the second Pt layer , thereby suppressing an increase in leakage current due to the heat treatment, improving the adhesion between the upper electrode and the dielectric layer, Further, in addition to lowering the resistance of the upper electrode, the T that supports the thinned first Pt layer
The reaction in the thermal process between the i layer and the Au layer as the low resistance layer can be prevented by the second Pt layer between the Ti layer and the Au layer. Also, similar to the second aspect of the present invention,
The problem of adhesion to the overlying wiring due to oxidation of the surface of the Ti layer during heat treatment is also eliminated.

[0040]

In the present invention (claim 4 ), the MIM
Since the dielectric layer of the capacitor is made of STO (SrTiO ₃ ), which has a higher relative dielectric constant than silicon oxide or silicon nitride usually used in semiconductor devices, the area occupied by the MIM capacitor on the substrate is reduced. It can be dramatically reduced. In addition, since the upper electrode on the dielectric layer has a multilayer structure including the Pt layer on the dielectric layer surface and the Au layer thereon, the Pt layer is structurally supported by the Au layer thereon. The Pt layer for obtaining a thermally stable interface characteristic between the upper electrode and the STO layer as a dielectric layer can be formed thin enough to obtain sufficient adhesion with the STO layer. it can. In other words, a Pt layer that is stable against heat suppresses an increase in leakage current due to heat treatment after the formation of the upper electrode, and improves the adhesion to the STO layer by thinning the Pt layer, thereby improving the reliability as an element. Can be enhanced. In addition, since the low-resistance Au layer is formed on the Pt layer, the resistance of the upper electrode is reduced, whereby the power loss in the capacitor can be reduced.

When a Pt layer and an Au layer are laminated,
Adhesion to the STO layer is improved as compared with the stack of the Pt layer alone. This is because not only the thinning of the Pt layer, but also the directions of the stresses of the Pt layer and the Au layer are reversed, so that both stresses are offset and the stress of the entire upper electrode is alleviated. As a result, the upper electrode is less likely to peel off than when a single Pt layer is laminated.

Further, since the Au layer does not bond with oxygen,
At the time of the heat treatment, there is no concern that oxygen of the STO layer is adsorbed on the Au layer, and it is possible to expect to maintain low resistance of the upper electrode and further reduce leakage current at high temperatures.

[0044]

In the present invention (claim 5 ), after depositing SrTiO ₃ as a dielectric layer on the lower electrode, Pt
Since the Pt layer forming the upper electrode is formed by depositing the layer by electron beam evaporation, the Pt layer can be deposited in a microcrystalline state, and the adhesion between the upper electrode and the dielectric layer can be improved. Can be improved. Further, since the Ti layer is formed on the Pt layer, even if the Pt layer is thinned, the Pt layer is supported by the Ti layer. Adhesion with the body layer can be further improved. Further, since the Pt layer is interposed at the interface between the upper electrode and the dielectric layer, the interface between the two becomes thermally stable,
An increase in leakage current in the capacitor due to heat treatment after the formation of the upper electrode can be suppressed.

[0046] Further, after forming the upper electrode, the said Ti layer by a heat treatment in air or in a nitrogen P
Since an intermetallic compound of Ti and Pt is formed at the interface with the t layer, the presence of the intermetallic compound at the interface suppresses generation of defects of oxygen atoms in the STO layer during heat treatment.

In the present invention (claim 6 ), the heat treatment after the formation of the upper electrode is performed at a temperature in the range of 200 ° C. or more, so that the effect of suppressing the generation of oxygen atom defects in the STO layer is reduced. A certain intermetallic compound of Pt and Ti can be reliably formed. Further, since the temperature of the heat treatment performed after the formation of the upper electrode is set to 500 ° C. or less, it is possible to almost eliminate an increase in leakage current in the capacitor due to the heat treatment.

In the present invention (claim 7 ), after depositing SrTiO ₃ as a dielectric layer on the lower electrode,
Since the Pt layer forming the upper electrode is formed by depositing the layer by electron beam evaporation, the Pt layer can be deposited in a microcrystalline state, and the adhesion between the upper electrode and the dielectric layer can be improved. Can be improved. Further, since the Au layer is formed on the Pt layer, even if the Pt layer is thinned, the Pt layer is supported by the Au layer. Adhesion with the body layer can be further improved. Further, since the Pt layer is interposed at the interface between the upper electrode and the dielectric layer, the interface between the two becomes thermally stable,
An increase in leakage current in the capacitor due to heat treatment after the formation of the upper electrode can be suppressed. Furthermore, since the upper wiring includes the Au layer having a low resistance, the resistance of the upper electrode is reduced, thereby reducing the power loss in the capacitor.

[0049]

[0050]

[0051]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic principle of the present invention will be described together with a film forming technique by a sputtering method or an electron beam evaporation method.

ST which is a dielectric material of the MIM capacitor
For O (StTiO ₃ ), it is preferable to use a Pt-based material as the upper electrode of the MIM capacitor. This is because the contact interface between Pt and STO is thermally stable, so that an increase in leakage current in the capacitor due to heat treatment can be prevented, and Pt is a material having good compatibility with the IC process. Because.

As described in the above-mentioned document, Pt has a problem of adhesion with STO. This adhesion problem is solved by optimizing a method of forming a thin film of Pt. This can be solved by forming a thin Pt layer.
However, the thin Pt layer is structurally weak, and it is difficult to perform processing such as patterning, and the resistance value of the upper electrode becomes high, which causes power loss in the capacitor.

As a method of forming the Pt layer, a sputtering method, an electron beam evaporation method, and the like are known. A Pt layer formed by a sputtering method (hereinafter, also referred to as a sputtered Pt layer) is formed by a lift-off method. Difficulty forming patterns.
In other words, the sputtered Pt layer has high adhesion to the dielectric layer, but empirically increases the possibility of peeling when deposited thick. This is because the sputtering method uses Pt
It is considered that Pt crystal growth occurs due to the high energy of the plasma during the formation of the layer, so that the sputtered Pt layer has high stress. Therefore, Pt
When a sputtering method is used to form the layer, after forming a Pt layer on the entire surface, the Pt layer is etched by a method such as ion milling using a selectively formed resist film or the like as a mask. It is necessary to perform patterning.

As a method for forming a metal layer as an electrode other than the above-mentioned sputtering method, there is an electron beam evaporation method. In this method, when a substrate is kept at room temperature at the time of film formation, a microcrystalline state is formed on the substrate. This facilitates the formation of a thin film. The metal film in which the crystal is microcrystal has low stress and can exist in a low stress state as long as a large grain metal crystal does not grow.

The present inventors independently examined the relationship between the thickness of the Pt layer and the adhesion, and found that the Pt film formed by the electron beam evaporation method had a thickness of 2,000 Å on the high dielectric layer. There is no problem if
If the thickness of the upper electrode made of a single t-layer is less than 1000 Å, the thickness of the Pt layer is too small to have sufficient strength of the Pt layer, and the Pt layer is damaged due to external factors during the process. It was found that the electrode was damaged.

In view of this, the inventors of the present invention proposed a multi-layer structure of Pt and Ti as a high heat-resistant metal layer structure for a high dielectric material, which constitutes an upper electrode, instead of a Pt single layer, and Pt formed by heat treatment in this multi-layer structure. When an intermetallic compound of Ti and Ti was formed, very good results were obtained.

It is known that Pt and Ti form various intermetallic compounds depending on the composition, but the intermetallic compound is a material having a stable composition from a low temperature region to a high temperature region.

FIG. 8 is a graph showing the results of a study by the present inventors on the relationship between the structure of the upper electrode of the MIM capacitor and the leakage current in the capacitor caused by the heat treatment.

Here, the lower electrode of the MIM capacitor has a two-layer structure of a lower Ti layer having a thickness of 1000 Å and an upper Pt layer having a thickness of 2,000 Å, and a dielectric film is formed on the lower electrode. It is an STO film formed to a thickness of 2500 Å by a sputtering method at 350 ° C. The upper electrode uses a metal layer formed by electron beam evaporation.

In the graph of FIG. 8, the horizontal axis represents the temperature of the processing performed after the formation of the upper electrode, and the vertical axis represents the magnitude of the leak current in the MIM capacitor.

As reported in the above-mentioned document, the upper electrode has a thickness of 1000 angstroms on the STO layer.
In the case of an Au / Ti structure in which an i-layer and a 5000 Å-thick Au layer are sequentially laminated, an increase in leakage current starts at 300 ° C. after forming the upper electrode (graph A).
reference).

The upper electrode has a thickness of 50
An Angstrom Ti layer, a 1000 Angstrom thick Pt layer, a 500 Angstrom Ti layer,
In the case of an Au / Ti / Pt / Ti structure in which Au layers having a thickness of 5,000 Å are sequentially stacked, even if the Ti layer existing at the interface between the STO layer and the upper metal layer is as thin as 50 Å, , At 350 ° C., increase significantly (see graph B).

On the other hand, the upper electrode is placed on the STO layer,
Au / Ti / in which a Pt layer, a Ti layer, and Au are sequentially stacked
In the MIM capacitor having the Pt structure, the Pt layer has a thickness of 5 mm.
In the case of 0 Å, even if a predetermined heat treatment is performed as it is after the deposition of the upper electrode, the heat treatment temperature is 35 ° C.
If the temperature is 0 ° C. or lower, no increase in leak current is observed.
However, if the heat treatment temperature is 350 ° C. or higher, an increase in leakage current is observed (see graph C).

After forming the upper electrode having the same structure as that of the graph C, the upper electrode
Preliminary heat treatment at 0 ° C. was applied for 1 hour, and heat treatment was further performed to measure leak characteristics. In this case, when the temperature of the heat treatment performed after the formation of the upper electrode is up to 400 ° C., there is no increase in the leak current, and the heat resistance is remarkably improved (see graph D). The preliminary heat treatment has no effect when the temperature is around 150 ° C., and shows the same heat resistance as when no preliminary heat treatment is performed.

Here, in the sample in which the thickness of the Pt layer constituting the upper electrode is 50 Å, when a preliminary heat treatment at 200 ° C. is applied after the formation of the upper electrode,
Compared with the case where the heat treatment at 350 ° C. or higher is performed without the preliminary heat treatment, an improvement in the leak current characteristics affected by the heat treatment is observed. Regarding this point, the upper electrode of the Au / Ti / Pt structure to which the preliminary heat treatment has been applied has a barrier effect between the Ti layer and the STO layer by a thin layer of Pt alone and a heat treatment after the formation of the upper electrode. Thus, it is considered that the electrode structure has a barrier effect due to a substance produced by any reaction.

That is, when the thickness of the Pt layer is 100 Å or less, it is generally considered that the Pt layer is scattered in an island shape.
Despite being presumed to be in contact with the O layer, the fact that the heat treatment at 200 ° C. after the formation of the upper electrode of the metal multilayer structure has been observed to improve the leakage characteristics means that
The Pt layer reacts with the overlying Ti layer to produce an intermetallic compound, TixPty, that does not react to STO, which means that the leakage current is kept low.

As described above, the above intermetallic compound is heated at 200 ° C.
It is considered that the film is formed by the above heat treatment.
/ Ti / Pt structure or a heat treatment performed after forming the upper electrode of the Ti / Pt structure, for example, heat applied to the substrate when forming a SiN layer by p-CVD, or applying or baking a resist or the like. 200 ° C given to the substrate
The above-mentioned heat also produces the intermetallic compound.

Such an intermetallic compound is generated even in a low-temperature treatment when both Pt and Ti metals are deposited in a layered state in the form of microcrystals, and the barrier at the interface between the upper electrode and the dielectric layer is formed. Produces an effect. For this reason, it is effective to form the metal layer constituting the upper electrode by depositing a metal material in a microcrystalline state.For example, an electron beam evaporation method for depositing a metal material while keeping the substrate at room temperature is effective. It is valid. On the other hand, when a metal material is deposited by a sputtering method, crystallization of the deposited metal is promoted depending on the substrate temperature, and it is considered that a reaction for dislocation to an intermetallic compound hardly occurs.

In an experiment for examining a change in leakage current due to heat treatment for a sample having a different thickness of the Pt layer constituting the upper electrode, the thickness of the Ti layer of the upper electrode was 5%.
When the thickness is 00 Å, as shown in graphs C to G, the thickness of the Pt layer increases and the increase in the leak current due to the heat treatment disappears. However, the above P
As the thickness of the t layer increases from 1000 to 2000 angstroms, a reaction occurs in the Au / Ti / Pt structure constituting the upper electrode, and a large ball-up is observed on the surface. This indicates that when the ratio of the thickness of the Pt layer and the thickness of the Ti layer constituting the upper electrode exceeds a certain value and becomes Pt-rich, a surface reaction occurs at the upper electrode.

On the other hand, the upper electrode has a thickness of 50 on the STO layer.
In the case of a Pt / Au structure in which a Pt layer having a thickness of 0 Å and an Au layer having a thickness of 5,000 Å are sequentially laminated, even if a predetermined heat treatment is performed, the heat treatment temperature is 4 ° C.
If it is 50 ° or less, no increase in the leakage current is observed (see graph H).

Further, an upper electrode having a thickness of 10
In the case of a Pt / Au structure in which a Pt layer of 00 Å and an Au layer of 5000 Å in thickness are sequentially laminated, no increase in leak current is observed if the heat treatment temperature is 500 ° C. or lower (see graph I).

Here, as is apparent from the graphs F to I, the Pt / A / Pt / Ti / Au structure is more Pt / Au.
The leakage current of the u structure is slightly lower.

Further, the conventional Pt simple structure, the Pt of the present invention
For the / Au structure and the Pt / Ti / Au structure, the temperature characteristics of the leak current were measured 10 minutes after the heat treatment (350 ° C.), and the results are shown in FIG.

As is apparent from FIG. 9, the temperature characteristics of the Pt / Au structure are substantially the same as those of the Pt single structure.
At room temperature RT and 100 ° C., the leak current increases by about one digit, whereas only the temperature characteristics of the Pt / Ti / Au structure are separated, and an increase in the leak current of two digits or more is observed.

This is because in the case of the Pt / Ti / Au structure, S
Oxygen in the TO layer passes through the Pt layer to the Ti layer,
Combined with the i-layer, oxygen is lost in the STO layer (carriers are generated), and this STO layer is separated from the insulator by n
This is because it changes to a semiconductor of a type.

On the other hand, in the case of the Pt / Au structure, A
Since the u layer does not bond with oxygen, oxygen is not released from the STO layer, and the insulation of the STO layer is maintained. Moreover, A
The low resistance of the u layer is also maintained.

In the case of the Pt / Au structure, the adhesion to the STO layer is improved as compared with a single Pt layer. This is probably because not only the Pt layer is made thinner, but also the stress directions of the Pt layer and the Au layer are reversed, and the stresses of both are canceled out, and the stress of the entire upper electrode is reduced. This makes it difficult for the upper electrode to peel off.

Hereinafter, embodiments of the present invention will be described.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
2 to 4 are cross-sectional views for explaining a method of manufacturing the semiconductor device in the order of main steps.

In the figure, reference numeral 100 denotes a Schottky gate field effect transistor (hereinafter referred to as M
Abbreviated as ESFET. ) 110, and an MMIC on which a high dielectric capacitor 120 as a passive element and the like are mounted. Here, source / drain regions 111a and 111b constituting the MESFET 110 are formed on the semi-insulating GaAs substrate 101 of the MMIC 100, and a channel region 112 is formed between the two regions. Ohmic electrodes 113a and 113b are disposed on the source / drain regions 111a and 111b, respectively, and a Schottky gate electrode 114 is disposed on the channel region 112. Here, the ohmic electrodes 113a and 113b are connected to the AuGe, N
The gate electrode 114 has a multilayer structure in which Al, Ti, Pt, and Au are sequentially laminated.

A first SiN film 102 is formed on the surface of the substrate 101, and the MESFET 11
0 is covered with the SiN film 102. This SiN
In portions of the film 102 corresponding to the ohmic electrodes 113a and 113b, SiN film openings 102a and 102b are formed as contact holes, and the ohmic electrodes 113a and 113b are formed in the contact holes 102a and 113b.
a and 102b are connected to a lower wiring 103 formed on the SiN film 102.

The lower wiring 103 is made of Ti, Au, Pt
Are connected in sequence to form a multi-layer structure.
The vicinity is the lower electrode 12 of the MIM capacitor 120.
It is 2. The lower electrode 122 and the lower wiring 1
03 is insulated from the lower electrode 122.
As the dielectric layer of the IM capacitor, STO (SrTi
An O ₃ ) layer 121 is formed, on which an upper electrode 123 of the MIM capacitor 120 is formed. The upper electrode has a multilayer structure in which Pt, Ti, and Au are sequentially laminated.

The surfaces of the MIM capacitor 120 and the lower wiring 103 are covered with a second SiN film 106, and a portion of the SiN film 106 corresponding to a required portion of the lower wiring 103, and a SiN film. In portions of the capacitor 106 corresponding to the upper electrode 123 of the capacitor 120, SiN film openings 106a and 106a are formed as contact holes, respectively.
106b is formed. Then, the lower wiring 10
3 and the upper electrode 123 of the MIM capacitor
Are electrically connected via the above-mentioned contact holes 106a and 106b by an upper wiring 108 formed on the SiN film 106 of FIG.

Next, the manufacturing method will be described.

First, an n ⁺ -type source / electrode is implanted into a desired region of the semi-insulating GaAs substrate 101 by ion implantation of Si.
Activation regions 111a and 111b serving as drain regions;
An activation region 112 serving as an n-type channel region is formed, and an annealing process is performed at a temperature of 900 ° C. Here, the ion implantation concentration at the time of forming the activation region 112 is 1.5 × 10
¹² / cm ^2, the active region 111a, ion implantation concentration at the time of forming the 111b is set to ² × 10 ¹³ / cm 2.

Subsequently, a mask layer having an opening corresponding to the ohmic electrode pattern is formed by photolithography, AuGe, Ni, and Au are sequentially deposited on the mask layer, and the metal layer on the mask layer is lifted off. Then, a heat treatment is applied to the source / drain region 111.
Ohmic electrodes 113a and 113b are formed on a and 111b.

Further, a mask layer having an opening corresponding to the gate electrode pattern is formed by photolithography, Al, Ti, Pt, and Au are sequentially deposited, and the metal layer on the mask layer is lifted off to form the channel. Region 112
A Schottky gate electrode 114 is formed thereon (FIG. 2)
(A)).

After the gate electrode 114 is formed in this manner, the first SiN film 102 is deposited on the entire surface of the wafer by p-CVD so that the thickness thereof becomes 2000 Å. Then, buffered hydrofluoric acid (corresponding to 5% hydrofluoric acid) is used as a mask with the etching resistant film formed using photolithography technology as a mask.
The SiN film 102 is selectively etched to form the SiN
Contact holes 102a and 102b are formed in portions of the film corresponding to ohmic electrodes 113a and 113b, and a contact hole (not shown) is formed in a portion of the SiN film corresponding to a lead portion of the gate electrode (FIG. 2 (b)).

Next, the lower wiring 103 and the lower electrode 12 of the MIM capacitor are formed by photolithography.
Forming a mask layer having an opening pattern corresponding to 2;
On the mask layer, 100 .ANG. Of Ti, 5000 .ANG. Of Au, and 1000 .ANG. Of Pt are sequentially deposited on the mask layer by electron beam evaporation. Thereafter, the metal layer on the mask layer is lifted off, and the Au / Ti
/ Pt lower wiring 103 and lower electrode 1 having a multilayer structure
22 are formed (FIG. 2C).

Next, STO is deposited on the substrate by RF sputtering so as to have a thickness of 2500 angstroms. The deposition of the STO layer by this RF sputtering is performed by Ar:
Using a mixed gas having a ratio of O ₂ = 5: 5, the substrate temperature is maintained at 350 ° C. under the condition that the atmosphere of the mixed gas is 2 Pa.

Then, a resist mask 107 is formed by photolithography in a region where the STO film is to be left on the substrate, and the unmasked portion of the STO film is etched by a mixed etchant composed of buffered hydrofluoric acid, hydrochloric acid, and water. Etching, dielectric layer 1 of MIM capacitor
21 are formed (FIG. 3A).

Next, a mask layer having a predetermined opening pattern is formed on the substrate by a photolithographic technique, and 100 Å of Pt, 500 Å of Ti, and 100 Å of Au are entirely formed by electron beam evaporation.
Deposition is sequentially performed to a thickness of 0 Å. Thereafter, the metal layer on the mask layer is lifted off, and an upper electrode 123 of the MIM capacitor is formed on the STO film 121 as the dielectric layer (FIG. 3B).

Then, an SiN layer 106 is deposited on the entire surface of the substrate by p-CVD so as to have a thickness of 2000 angstroms. At this time, the substrate temperature is set to 300 ° C. (FIG. 3C).

Next, a photoresist film 109 having resist openings 109a and 109b at predetermined portions on the substrate.
Is formed, and using the photoresist film 109 as a mask,
The second SiN film 106 is formed by buffered hydrofluoric acid.
Is selectively etched. Thereby, the SiN film 1 is formed.
06, a contact hole 106a is formed in a portion of the lower wiring 103 near the capacitor, and the SiN film 10 is formed.
6, a contact hole 106b is formed in a portion corresponding to the upper electrode 123 of the capacitor 120.
(A)).

Then, a mask layer having an opening corresponding to the pattern of the upper wiring 108 is formed on the substrate by a photolithography technique, and further, 500 Å of Ti and 1 μm of Au are deposited on the entire surface by electron beam evaporation. Then, the metal layer on the mask layer is lifted off to form the upper wiring 108 of the Au / Ti structure (FIG. 4B). As a result, the MMIC 10
Complete 0.

Next, the function and effect will be described.

The MMIC 100 created as described above
Has both a MIM capacitor using SiN as a dielectric and a MIM capacitor using a high dielectric (STO) as a dielectric. The MIM capacitor using SiN as a dielectric has an area of 1 × 10 ^4. μm ² exhibited a capacitance of 2.8 pF, and the MIM capacitor using STO as a dielectric exhibited a capacitance of 2.1 pF at an area of 400 μm ² . This MI
STO in the M capacitor is equivalent to 131 in relative dielectric constant.

Further, the leakage current of the STO capacitor is
When 10 V is applied to both ends of the capacitor, 1.2 × 10 ⁻⁷ A /
It showed a value of m ² and showed good insulating properties.

When mounting the MMIC chip of the first embodiment in a ceramic package, die bonding was performed with an AuSn alloy, and the package was hermetically sealed. The processing temperature for this mounting is 320 to 350 ° C.
However, even after mounting, the characteristics of the MMIC are good.
No deterioration was observed in the leak characteristics of the high dielectric capacitor, and it was demonstrated in the first embodiment that the upper electrode of the MIM capacitor exhibited sufficient heat resistance.

Next, an experiment regarding the maximum value of the thickness of the Pt layer constituting the upper electrode will be described.

First, a method of preparing a sample of the MIM capacitor will be described.

On a semi-insulating GaAs substrate on which SiN was deposited, Ti was deposited to a thickness of 50 Å by electron beam evaporation.
Au is successively formed to a thickness of 5000 angstrom and Pt to a thickness of 500 angstrom to form a lower electrode having a multilayer structure. Next, STO was applied on the lower electrode at a substrate temperature of 3.
It is formed to a thickness of 2500 Å by sputtering at 00 ° C. Then, the STO layer on the substrate is selectively etched by a mixed etchant of buffered hydrofluoric acid, hydrochloric acid, and water using a resist mask to form a dielectric layer.

Further, a Pt layer having a thickness of 2000 Å, a Ti layer having a thickness of 500 Å, and a 5,000 Å thickness were formed on the dielectric layer made of STO by vapor deposition and lift-off of a metal layer by electron beam vapor deposition on the substrate. A capacitor upper electrode made of an Au layer was formed.

In the sample of the MIM capacitor thus formed, a part of the upper electrode was lifted off the substrate during lift-off.

In the sample constituting the upper electrode and having a Pt layer formed by the sputtering method with a thickness of 1000 angstroms, the upper electrode did not peel off at the time of lift-off as described above.

In FIG. 5, the thickness of the Pt layer is changed from 0 to 2
The peeling rate of the upper electrode is shown for the samples varied between 000 Å. However, in FIG.
The case where each metal layer constituting the upper electrode is formed by an electron beam evaporation method is shown.

Therefore, it can be said that the upper limit of the Pt thickness of the upper electrode in the process is 1000 angstroms even when the sputtering method is used.

Next, a description will be given of an experiment on a substantial minimum value of the thickness of the Pt layer constituting the upper electrode.

First, a method of preparing a sample of the MIM capacitor will be described.

On a semi-insulating GaAs substrate on which SiN is deposited, Ti is sequentially formed to a thickness of 1000 Å and Pt to a thickness of 2000 Å by electron beam evaporation to form a lower electrode, and an STO is formed on the lower electrode. The film is formed at a temperature of 350 ° C. by sputtering to a thickness of 2500 Å. Then, the STO layer on the substrate is selectively etched using a resist mask with a mixed etchant composed of buffered hydrofluoric acid, hydrochloric acid, and water to form a dielectric layer.

Then, the surface of the substrate is divided into four regions, and an upper electrode having a multilayer structure of Pt, Ti, and Au is formed in each region by changing the thickness of the Pt layer.

In each of the above regions, the Ti layer has a thickness of 50 angstroms, the Au layer has a thickness of 5000 angstroms, the first region has a Pt layer of 50 angstroms, the second region has a Pt layer of 100 angstroms, and the third region has a thickness of 100 angstroms. The Pt layer has a thickness of 500 Å and the fourth region has a thickness of 1000 Å.

Each metal constituting the upper electrode in each region is formed by an electron beam evaporation method, and is patterned by lift-off.

As described above, Pt is added to the four regions on the surface.
For a substrate on which upper electrodes having different layer thicknesses were formed, 3
The increase in the leak current was measured for those subjected to heat treatment in the air from 00 ° C to 500 ° C.

Further, the same substrate as above was subjected to a preliminary heat treatment at 200 ° C. for 1 hour, and then a heat treatment at 300 to 500 ° C. was also prepared as a sample.

FIG. 6 shows the relationship between the leakage current and the processing temperature when a voltage of 10 V is applied to the upper electrode and the lower electrode of each capacitor of each sample.

In the case of a capacitor having a Pt layer thickness of 50 angstroms, the case where a preliminary heat treatment is applied is as follows:
When compared with the case without the preliminary heat treatment, there is a difference in the increase of the leak current due to the heat treatment at 400 ° C. or more, and when the Pt thickness is small, the intermetallic compound formed by the preliminary heat treatment at 200 ° C. improves the leakage characteristics. Is effective. When the thickness of Pt is increased, the leakage characteristics are improved regardless of the presence or absence of the preliminary heat treatment.

Therefore, if the thickness of the Pt layer constituting the upper electrode of the Au / Ti / Pt structure is 50 Å or more, the St caused by the heat treatment in the normal IC process is not required.
It can be seen that this is effective for increasing the leakage current in the TO capacitor.

Therefore, in the first embodiment, the Pt layer constituting the upper electrode has a thickness of 100 Å, but the present invention is not limited to this thickness, and the Pt layer is not limited to this thickness.
It can be said that the thickness of the t layer may be in the range of 50 Å to 1000 Å.

As described above, in the present embodiment, the dielectric layer 121 of the MIM capacitor 120 is made of STO (SrTiO ₃ ) having a higher relative dielectric constant than silicon oxide, silicon nitride, or the like usually used in a semiconductor device. Therefore, the MIM capacitor 120 is connected to the MMIC substrate 10.
1 can be dramatically reduced. In addition, the upper electrode 123 includes a Pt layer formed on the surface of the dielectric layer, a Ti layer formed on the Pt layer,
Since the Pt layer has a three-layer structure including the Au layer formed on the Ti layer, the Pt layer is structurally supported by the Ti layer and the Au layer thereon, and the STO as the upper electrode and the dielectric layer is formed. A Pt layer for obtaining thermally stable interface characteristics between the PTO layer and the PTO layer can be formed thin enough to obtain sufficient adhesion to the STO layer. In other words, the heat-resistant Pt layer suppresses an increase in leakage current due to heat treatment after the formation of the upper electrode, and the thinning of the Pt layer results in a decrease in the ST.
By improving the adhesion to the O layer, the reliability as an element can be increased.

Further, since the multilayer metal layer forming the upper electrode 123 contains a low-resistance Au layer, the resistance of the upper electrode can be reduced, thereby reducing the power loss in the capacitor. Can be reduced.

In the upper electrode 123, since the surface of the Ti layer is covered with the Au layer, depending on the thickness of the Ti layer, the surface of the Ti layer is oxidized by a trace amount of oxygen in the atmosphere when heat treatment is applied. The problem that the adhesion of the wiring formed thereon is deteriorated can also be solved.

Since the upper electrode 123 has a structure including an intermetallic compound of Ti and Pt formed at the interface between the Ti layer and the Pt layer by heat treatment in the metal layer having a multilayer structure, Due to the presence of the intermetallic compound, the generation of defects of oxygen atoms in the STO layer during the heat treatment is suppressed, and the increase in leakage current due to the heat treatment can be further suppressed.

Further, the dielectric layer 121 is formed on the lower electrode 122.
After depositing SrTiO ₃ , a Pt layer is deposited by electron beam evaporation to form a Pt layer constituting the upper electrode 123, so that the Pt layer can be deposited in a microcrystalline state. The adhesion between the electrode 123 and the dielectric layer 121 can be improved.

In the first embodiment, the upper electrode 1
23 has a three-layer structure.
With a four-layer structure in which a second Pt layer is interposed between the first Pt layer and the u layer, a heat treatment is performed on the Ti layer supporting the thinned first Pt layer and the Au layer as a low resistance layer. Can be prevented by the second Pt layer between the Ti layer and the Au layer.

(Embodiment 2) Next, a semiconductor device according to Embodiment 2 of the present invention will be described.

In the semiconductor device of this embodiment, the upper electrode of the MIM capacitor mounted on the MMIC of the first embodiment has a two-layer structure of a lower Pt layer and an upper Ti layer. Are the same as those in the first embodiment.

Next, the function and effect will be described.

An experiment on a substantial minimum value of the thickness of the Pt layer constituting the upper electrode of the MIM capacitor according to the second embodiment will be described.

First, a method of preparing a sample of the MIM capacitor will be described.

On a semi-insulating GaAs substrate on which SiN was deposited, Ti was sequentially formed to a thickness of 1000 Å and Pt to a thickness of 2000 Å by electron beam evaporation to form a lower electrode, and an STO was formed on the lower electrode. The film is formed at a temperature of 350 ° C. by sputtering to a thickness of 2500 Å. Then, the STO layer on the substrate is selectively etched using a resist mask with a mixed etchant composed of buffered hydrofluoric acid, hydrochloric acid, and water to form a dielectric layer.

The surface of the substrate is divided into four regions, and an upper electrode having a multilayer structure of Pt and Ti is formed in each region by changing the thickness of the Pt layer.

In each of the above regions, the thickness of the Ti layer is 500 Å, the thickness of the Pt layer is 50 Å in the first region, the thickness of the Pt layer is 100 Å in the second region, and the thickness of the Pt layer is 500 Å in the third region. In the fourth region, the Pt layer has a thickness of 1000 Å.

Each metal layer constituting the upper electrode in each region is formed by electron beam evaporation, and is patterned by lift-off.

As described above, Pt is added to the four regions on the surface.
For a substrate on which upper electrodes having different layer thicknesses were formed, 3
The increase in leak current was measured for those subjected to heat treatment in nitrogen from 00 ° C to 500 ° C.

FIG. 7 shows the relationship between the leakage current and the processing temperature when a voltage of 10 V is applied to the upper and lower electrodes of the capacitors in each of the above regions. From this figure, it can be seen that when the heat treatment temperature after the formation of the upper electrode is up to about 500 ° C., the increase in the leak current due to the heat treatment can be suppressed to a small value.

In the second embodiment, the upper electrode having a two-layer structure of Pt / Ti is disadvantageous in terms of lowering resistance as compared with the first embodiment, but is otherwise disadvantageous. The same effects as those of the first embodiment can be obtained.

However, in the first embodiment, the heat treatment for forming the intermetallic compound after the formation of the upper electrode may be oxidized on the surface of the Ti layer if performed in air.
It must be performed in a nitrogen atmosphere.

Also in the second embodiment, the power loss in the capacitor can be reduced by forming the extraction electrode and the wiring made of low-resistance metal on the upper electrode.

(Embodiment 3) A semiconductor device according to Embodiment 3 of the present invention will be described.

In the semiconductor device of this embodiment, the upper electrode of the MIM capacitor mounted on the MMIC of the first embodiment has a two-layer structure of a lower Pt layer and an upper Au layer. Are the same as those in the first embodiment.

The thickness of the Pt layer is set to 50 to 1000 Å. The reason is that, as in the first and second embodiments, if the thickness is 50 angstroms or more, sufficient adhesion can be ensured, and if it exceeds 1000 angstroms, a problem of peeling occurs.

The thickness of the Au layer is 200-5000.
Angstrom. This means that the resistance of the upper electrode cannot be effectively reduced if the thickness is 200 Å or less, and if the resistance exceeds 5000 Å,
This is because a problem of peeling occurs.

Preferably, the thickness of the Pt layer is from 250 to 10
00 Å and the thickness of the Au layer is 100
0 to 3000 angstroms.

In this embodiment having such a configuration, the MIM
Since the dielectric layer of the capacitor is made of STO (SrTiO ₃ ), which has a higher relative dielectric constant than silicon oxide or silicon nitride usually used in semiconductor devices, the area occupied by the MIM capacitor on the substrate is reduced. It can be dramatically reduced. In addition, since the upper electrode on the dielectric layer has a multilayer structure including the Pt layer on the dielectric layer surface and the Au layer thereon, the Pt layer is structurally supported by the Au layer thereon. The Pt layer for obtaining a thermally stable interface characteristic between the upper electrode and the STO layer as a dielectric layer can be formed thin enough to obtain sufficient adhesion with the STO layer. it can. In other words, a Pt layer that is stable against heat suppresses an increase in leakage current due to heat treatment after the formation of the upper electrode, and improves the adhesion to the STO layer by thinning the Pt layer, thereby improving the reliability as an element. Can be enhanced. In addition, since the low-resistance Au layer is formed on the Pt layer, the resistance of the upper electrode is reduced, whereby the power loss in the capacitor can be reduced.

In the case of a two-layer structure of a Pt layer and an Au layer, the directions of stress of the Pt layer and the Au layer are opposite, and
Since both stresses are offset and the stress on the entire upper electrode is reduced, the adhesion to the STO layer is further improved, and the upper electrode is less likely to be peeled off.

Further, since the Au layer does not bond with oxygen,
During the heat treatment, there is no concern that oxygen in the STO layer is adsorbed on the Au layer, and it is possible to maintain low resistance of the upper electrode and further reduce leakage current at high temperatures.

[0149]

As described above, according to the MIM capacitor according to the present invention (claim 1), the area occupied by the MIM capacitor on the substrate can be significantly reduced, and the Pt layer of the upper electrode can be reduced. The Pt layer, which is structurally supported by the upper Ti layer and constitutes the upper electrode and is thermally stable with respect to the STO layer, is formed thin enough to obtain sufficient adhesion to the STO layer. can do. In other words, the Pt layer that is stable against heat suppresses an increase in leakage current due to heat treatment after the formation of the upper electrode, and improves the adhesion to the STO layer by thinning the Pt layer, thereby improving the reliability of the device. There is an effect that can be increased. Also before
The upper electrode is formed by heat-treating the Ti layer and the Pt layer.
Contains an intermetallic compound of Ti and Pt formed at the interface with
Structure, the presence of the intermetallic compound
Can further suppress the increase in leakage current due to
There is a clear effect.

According to the present invention (claim 2), in the MIM capacitor according to claim 1, the upper electrode is provided in the MIM capacitor.
Since it has the Au layer formed on the Ti layer, it is possible to suppress the increase in the leak current due to the heat treatment, to improve the adhesion between the upper electrode and the dielectric layer, and to reduce the resistance of the upper electrode. Power loss in the capacitor can be reduced. Further, the Au layer on the surface of the Ti layer can also solve the problem that the surface of the Ti layer is oxidized by a trace amount of oxygen in the atmosphere when heat treatment is performed and the adhesion of the wiring formed thereon is deteriorated.

According to the present invention (claim 3), in the MIM capacitor according to claim 1, the upper electrode is provided in the MIM capacitor.
A second Pt layer formed on the Ti layer, and the second Pt layer
Since it has an Au layer formed thereon , in addition to suppressing the increase in leakage current due to the heat treatment, improving the adhesion between the upper electrode and the dielectric layer, and further reducing the resistance of the upper electrode, The reaction in the thermal process between the Ti layer supporting the thinned first Pt layer and the Au layer as the low resistance layer is prevented by the second Pt layer between the Ti layer and the Au layer. There is an effect that can be done.

[0152]

According to the MIM capacitor of the present invention (claim 4 ), the dielectric layer of the MIM capacitor is made of STO (SrTiO ₃ ) having a high relative permittivity, and
Since the upper electrode on the dielectric layer has a multilayer structure including a Pt layer on the dielectric layer surface and an Au layer thereon,
The area occupied by the capacitor on the substrate is drastically reduced, and a heat-stable Pt layer suppresses an increase in leak current due to heat treatment after the formation of the upper electrode. The adhesion can be improved, and the reliability as an element can be increased. Furthermore, Pt
Since the Au layer having a low resistance is formed on the layer, the resistance of the upper electrode is reduced, which has the effect of reducing power loss in the capacitor.

Further, when a Pt layer and an Au layer are laminated,
Since the stress directions of the Pt layer and the Au layer are opposite to each other, the stresses of the two are offset, and the stress of the entire upper electrode is alleviated. Therefore, the adhesion to the STO layer is further improved, and the upper electrode is hardly peeled off. .

Further, since the Au layer does not bond with oxygen,
At the time of the heat treatment, there is no concern that oxygen of the STO layer is adsorbed on the Au layer, and it is possible to expect to maintain low resistance of the upper electrode and further reduce leakage current at high temperatures.

[0156]

According to the method of manufacturing the MIM capacitor according to the present invention (claim 5 ), the Pt layer is deposited by electron beam evaporation to form the Pt layer constituting the upper electrode. Can be deposited in a microcrystalline state, and the adhesion between the upper electrode and the dielectric layer can be improved. Also, Pt
Since the Ti layer is formed on the layer, even if the Pt layer is thinned, the Pt layer will be supported by the Ti layer.
By reducing the thickness of the Pt layer, the adhesion between the upper electrode and the dielectric layer can be further improved. Further, since the Pt layer is interposed at the interface between the upper electrode and the dielectric layer, the interface between the two is thermally stable, and the increase in leakage current in the capacitor due to the heat treatment after the formation of the upper electrode is suppressed. be able to.

[0158] Further, after forming the upper electrode, the T
Since an intermetallic compound of Ti and Pt is formed at the interface between the i layer and the Pt layer, the occurrence of oxygen atom defects in the STO layer during heat treatment is suppressed by the presence of the intermetallic compound at the interface. You.

According to the present invention (claim 6 ), in the method of manufacturing an MIM capacitor according to claim 8, the heat treatment after the formation of the upper electrode is performed at a temperature in the range of 200 ° C. to 500 ° C. Pt and T by heat treatment over ℃
i can reliably form an intermetallic compound, and
Since the heat treatment after the formation of the upper electrode is performed at a temperature of 500 ° C. or lower, an increase in leakage current due to the heat treatment can be suppressed to a small value.

According to the method for manufacturing the MIM capacitor according to the present invention (claim 7 ), the dielectric layer is formed on the lower electrode as a dielectric layer.
After depositing rTiO ₃ , a Pt layer and an Au layer are sequentially deposited by electron beam evaporation to form an upper electrode having an Au / Pt structure. Of the capacitor, the increase in leakage current in the capacitor due to the heat treatment can be suppressed, and since the upper wiring includes a low-resistance Au layer, the power loss in the capacitor is reduced by reducing the resistance of the upper electrode. There is also an effect that the reduction can be achieved.

[0161]

[0162]

[0163]

As described above, according to the present invention, it is possible to provide an upper electrode of a high dielectric capacitor having low resistance, high heat resistance and no problem of adhesion, etc., so that the reliability of the high dielectric capacitor can be improved. And the characteristics of the MMIC having the high dielectric capacitor mounted thereon can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a structure of an MMIC as a semiconductor device according to a first embodiment of the present invention.

2A and 2B are views for explaining a method of manufacturing the MMIC, and FIG. 2A shows a process of forming a MESFET;
2B shows a step of forming a contact hole, and FIG. 2C shows a step of forming a lower wiring.

3A and 3B are views for explaining a method for manufacturing the MMIC, wherein FIG. 3A shows a step of forming a dielectric layer of the MIM capacitor, and FIG. 3B shows a step of forming an upper electrode of the MIM capacitor; FIG. 3C shows a step of forming an insulating layer.

4A to 4C are views for explaining a method of manufacturing the MMIC. FIG. 4A is a step of forming a contact hole in an insulating layer shown in FIG. 3C, and FIG. MMI
3C shows a step of forming an upper layer wiring of C.

FIG. 5 shows P constituting an upper electrode of the MIM capacitor.
It is a figure showing an experimental result about the maximum value of layer thickness of t layer.

FIG. 6 shows P constituting an upper electrode of the MIM capacitor.
It is a figure showing an experimental result about a minimum value of layer thickness of t layer.

FIG. 7 is a diagram for explaining the operation and effect of the MMIC according to the second embodiment of the present invention, and illustrates an MMIC mounted on the MMIC;
9 shows an experimental result regarding a minimum value of a Pt layer constituting an upper electrode of an IM capacitor.

FIG. 8 is a diagram for explaining a basic function and effect of the present invention in comparison with a conventional technique.

FIG. 9 is a diagram showing the temperature characteristics of the leak current after heat treatment for each structure of the upper electrode of the present invention and the prior art.

[Explanation of symbols]

Reference Signs List 100 MMIC 101 Semi-insulating GaAs substrate 102, 106 First and second SiN films 102a, 102b, 106a, 106b Contact hole 103 Lower wiring 108 Upper wiring 110 MESFET 111a, 111b Source / drain region 112 Channel region 113a, 113b Ohmic Electrode 114 Schottky gate electrode 120 MIM capacitor 121 Dielectric layer 122 Lower electrode 123 Upper electrode

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/822 H01L 27/04

Claims (9)

(57) [Claims] 1. An MIM capacitor having a dielectric layer sandwiched between a lower electrode and an upper electrode, wherein the dielectric layer is made of SrTiO ₃ which is a high dielectric substance. The upper electrode provided in close contact with the layer has a multilayer structure including a Pt layer formed on the surface of the dielectric layer and a Ti layer formed on the Pt layer, In the metal layer having the multilayer structure, the T layer formed at the interface between the Ti layer and the Pt layer by a heat treatment in air or nitrogen.
An MIM capacitor containing an intermetallic compound of i and Pt. 2. The MIM capacitor according to claim 1, wherein said upper electrode has an Au layer formed on said Ti layer. 3. The MIM capacitor according to claim 1, wherein the upper electrode is a second Pt formed on the Ti layer.
A MIM capacitor having a layer and an Au layer formed on the second Pt layer. 4. An MIM capacitor having a dielectric layer sandwiched between a lower electrode and an upper electrode, wherein the dielectric layer is made of SrTiO ₃ which is a high dielectric substance. An upper electrode provided in close contact with the layer has a multilayer structure including a Pt layer formed on the surface of the dielectric layer and an Au layer formed on the Pt layer.
Capacitors. 5. A method for manufacturing an MIM capacitor having a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode, wherein the step of forming the dielectric layer comprises the step of forming SrTiO ₃ on the lower electrode.
And forming a metal oxide layer constituting the dielectric layer. The step of forming the upper electrode includes: depositing Pt on the dielectric layer by electron beam evaporation; A step of forming a Pt layer constituting the upper electrode; a step of depositing Ti on the Pt layer by electron beam evaporation to form a Ti layer constituting the upper electrode; Forming an intermetallic compound of Ti and Pt at the interface between the Ti layer and the Pt layer by heat treatment. 6. The method for manufacturing a MIM capacitor according to claim 5, wherein the heat treatment after the formation of the upper electrode is performed at 200 ° C. to 500 ° C.
A method for manufacturing a MIM capacitor performed at a temperature in the range of ° C. 7. A method for manufacturing an MIM capacitor having a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode, wherein the step of forming the dielectric layer comprises the step of forming SrTiO ₃ on the lower electrode.
And forming a metal oxide layer constituting the dielectric layer. The step of forming the upper electrode includes: depositing Pt on the dielectric layer by electron beam evaporation; A method of manufacturing an MIM capacitor, comprising: forming a Pt layer forming the upper electrode; and depositing Au on the Pt layer by electron beam evaporation to form an Au layer forming the upper electrode. . 8. An MIM having a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode formed on a semiconductor substrate.
A semiconductor device having a plurality of capacitors, the plurality of MIM capacitor, a high dielectric layer on one of the same process at the lower electrode which is formed on the semiconductor substrate made of SrTiO _3, the high dielectric a first MIM capacitor are sequentially formed and an upper electrode formed on the layer, the under
A second M in which a dielectric layer made of SiN and the upper electrode formed on the dielectric layer are sequentially laminated on the other of the lower electrodes
A semiconductor device comprising: an IM capacitor. 9. An MIM having a structure in which a dielectric layer is sandwiched between a lower electrode and an upper electrode formed on a semiconductor substrate.
A method of manufacturing a semiconductor device having a plurality of capacitors, the lower electrode of the first and second MIM capacitors which
A step of being formed, the steps of one of the high-dielectric layer is formed consisting of SrTiO ₃ on the lower electrode, to form a first MIM capacitor upper electrode are sequentially formed on the high dielectric layer, Forming a dielectric layer made of SiN on the other of the lower electrodes , and forming an upper electrode on the dielectric layer to form a second MIM capacitor. Device manufacturing method.