JP3327977B2 - Semiconductor substrate manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device, and more particularly to a method of manufacturing a semiconductor substrate used for manufacturing a high breakdown voltage semiconductor element.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated device, a number of semiconductor elements such as transistors are formed on a common substrate. At this time, the semiconductor elements are not affected so that these semiconductor elements do not influence each other. A semiconductor substrate having a configuration in which the spaces are electrically insulated and separated is required.

Many methods for manufacturing the above-mentioned semiconductor substrate have been proposed in the past. Some of these manufacturing methods require a step of forming a thick polycrystalline silicon layer.

As a semiconductor substrate formed by a manufacturing method having a step of forming a thick polycrystalline silicon layer, for example, a dielectric isolation substrate as shown in FIG. 6 or an SOI (Silicon On Silicon) as shown in FIG. Insulator) substrate,
These are a single crystal silicon island 11 serving as an active region and a support layer 12, 2 which mechanically supports the single crystal silicon layer 21.
When a polycrystalline silicon layer is used as 2, the insulating film 13
23, it is necessary to form this thick polycrystalline silicon layer.

[0005] In addition, as shown in FIG.
(Isolation by Oxide and Polysilicon) When a polycrystalline silicon 32 is buried in a trench 31 for electrical isolation via an insulating film 33 like a substrate or the like, it is necessary to form this thick polycrystalline silicon layer. Become.

Referring to FIGS. 4A to 4C, a conventional method of manufacturing this type of semiconductor substrate will be described with reference to a dielectric isolation substrate shown in FIG. 6 as an example.

First, as shown in FIG. 4A, a single crystal silicon substrate 41 is anisotropically etched to form a V-shaped groove 42, and impurities of the same conductivity type as the polycrystalline silicon substrate are diffused over the entire surface. The buried layer 46 is formed.

Next, as shown in FIG. 4B, the single-crystal silicon substrate 41 is oxidized, and an oxide film 43 for electrical insulation separation is formed on the surface of the substrate including the V-shaped groove 42. Polycrystalline silicon 44 serving as a support layer is deposited on the film 43 to a desired thickness. In this deposition method, the silicon is heated to about 1440 ° C., which is the melting point of silicon, thereby melting the silicon to form a spray.
The melted silicon is deposited on the silicon substrate 41 kept at about 75 ° C. and solidified, so that polycrystalline silicon 44 is deposited on the silicon substrate 41.

Thereafter, the surface of the polycrystalline silicon 44 is ground to a flat processing reference surface 45, and thereafter, the back surface of the single crystal silicon substrate 41 is ground and polished until the tip of the V-shaped groove 42 is exposed. Thus, a dielectric isolation substrate having a single crystal silicon island 47 shown in FIG.

[0010]

However, in the above-described conventional manufacturing method, in the step of depositing thick polycrystalline silicon serving as a support layer, a temperature difference between the deposited molten silicon and the single-crystal silicon substrate causes. The single crystal silicon substrate is warped due to thermal stress.

The warpage of the single-crystal silicon substrate causes a variation in the thickness of the single-crystal silicon substrate and a variation in the thickness of the single-crystal silicon island in the subsequent grinding and polishing process, and therefore, it is desirable that the warpage is small.

Reference: ISSP (ISPSD
(Proceedings of 1990 International Symposium on Po
wer Semicondutor Devices IC's, April 4-6, 1990, pp. 17
4-179) shows the relationship between the temperature of a single crystal silicon substrate and the warpage of this substrate as shown in FIG.
From this relationship, it can be seen that lowering the temperature of the single crystal silicon substrate increases the warpage of the substrate. In order to avoid a problem in later steps, the warpage of the single crystal silicon substrate is 2
From FIG. 5, it can be seen that the temperature of the single crystal silicon substrate needs to be 1350 ° C. or higher in order to suppress the warpage of the single crystal silicon substrate to 200 μm or less.

The warpage of the single crystal silicon substrate is reduced by 200
μm or less, the temperature of the single crystal silicon substrate is set to 13
When the temperature is set to 50 ° C. or higher, the amount of re-diffusion of the buried layer increases, and the single crystal silicon island must be enlarged in order to secure a necessary active region in the single crystal silicon island.

Therefore, as a result of the increase in the semiconductor element area, there is a problem that the chip size is increased as a whole.

The present invention eliminates the above-described problem of requiring high-temperature processing to obtain a dielectric isolation substrate having a small warpage. It is an object of the present invention to provide an excellent method of manufacturing a semiconductor substrate which can obtain a dielectric isolation substrate having a small warpage of a silicon substrate.

[0016]

To SUMMARY OF THE INVENTION To achieve the above object, a method of manufacturing a semiconductor substrate of the present invention, a silicon group
A groove is formed in the plate, and an insulating film is formed in the groove.
Heated to 0 ° C., 4.5-5.0 at. % Molten silicon containing germanium concentration - isolation groove in the silicon substrate heated germanium alloy at about 1200 ° C.
Table of Write solidified germanium alloy, in the silicon substrate, the grooves are formed - supplied onto the film, the molten silicon
The surface opposite to the surface was polished .

[0017]

According to the method of manufacturing a semiconductor substrate of the present invention described above,
Since the thermal stress caused by the temperature difference between the molten silicon-germanium alloy and the silicon substrate and the stress due to the body expansion during the solidification of the molten silicon-germanium alloy cancel each other, the warpage of the silicon substrate is suppressed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (d), taking a dielectric isolation substrate as an example.

First, as shown in FIG. 1A, a single crystal silicon substrate 51 is oxidized, and a first oxide film 52 having a thickness of about 1 μm is formed on the surface thereof.

Next, as shown in FIG. 1B, the first oxide film 52 is partially opened by photolitho etching, and a single-crystal silicon substrate is formed using the remaining first oxide film 52 as a protective mask. By anisotropically etching 51,
A V-shaped groove 53 having a depth of about 50 μm is formed. Next, as shown in FIG. 1C, after removing the first oxide film 52, the single-crystal silicon substrate 51 is oxidized again, and an insulating film having a thickness of about 2 μm is formed on the surface of the substrate including the V-shaped groove 53. A second oxide film 54 is formed.

[0021] Next, the single crystal silicon substrate 51 is placed on the stage 61 of the spray apparatus shown schematically in Figure 2, heated by a heater 62 and kept at a temperature of about 1200 ° C..
Thereafter, the silicon-germanium alloy 64 is heated to about 1400 ° C. by the heater 65 and melted in the quartz tube 63 of the spray device, and the Ar (argon) gas outlet 6 is heated.
6 is atomized by Ar gas ejected from 6 and solidified on the second oxide film 54 on the rotating single-crystal silicon substrate 51 to form a silicon-germanium alloy having a thickness of about 500 to 600 μm. The layer 55 is formed.

FIG. 3 shows the experimental results as a relationship between the germanium concentration of the silicon-germanium alloy 64 and the warpage of the dielectric isolation substrate.

From this experimental result, when the temperature of the single crystal silicon substrate is set to 1200 ° C., the germanium concentration is set to 4.5.
~ 5.0 at. %, It was found that the warpage of the silicon substrate was reduced.

This is because the thermal stress caused by the temperature difference between the molten silicon-germanium alloy and the silicon substrate and the stress due to the body expansion during the solidification of the molten silicon-germanium alloy cancel each other, so that the warpage of the silicon substrate is suppressed. It is considered that such dependence of the germanium concentration occurs.

Here, for example, a germanium concentration of 4.3 at. % Of the silicon-germanium alloy is used so that the warpage of the substrate is about 100 μm.

After the above steps, as shown in FIG.
By grinding the surface of the silicon-germanium alloy layer 55 to a flat processing reference surface 56 and removing the back surface of the single crystal silicon substrate 51 by grinding and polishing until the tip of the V-shaped groove 53 is exposed, the single crystal silicon island is removed. Reference numeral 57 denotes a second oxide film 54 for insulation isolation and silicon as a support layer.
Through the germanium alloy layer 55, a dielectric isolation substrate electrically isolated from each other is obtained.

In the above embodiment, the dielectric isolation substrate was taken up, but the V-shaped groove 53 shown in FIG. 1B was not formed, and the single crystal silicon substrate 51 shown in FIG. When a SOI substrate is obtained by removing a single crystal silicon layer having a thickness of several μm by grinding and polishing, a V-shaped groove 53 or a U-shaped groove is formed in a single crystal silicon substrate 51 as shown in FIG. After the formation, a second oxide film 54 is formed, the alloy layer 55 of the silicon base material shown in FIG. 1C is formed to a thickness enough to fill the groove, and the alloy layer 55 of the silicon base material is formed of a single crystal. The present invention can be applied to the case where the trench is filled with an alloy layer 55 of a silicon base material by removing the second oxide film 54 formed on the surface of the silicon substrate 51 until the second oxide film 54 is exposed.

In the above-described embodiment, silicon-germanium having a predetermined concentration is prepared in advance. However, silicon and germanium are separately prepared, and these are melted and mixed in a quartz tube 63 to form silicon-germanium having a predetermined concentration. In this case, the present invention can be applied.

[0029]

As described above, according to the method of manufacturing a semiconductor substrate of the present invention, a method of manufacturing a semiconductor substrate of 4.5 to 5.0 at. % Of silicon-germanium alloy containing germanium at a concentration of 0.1%, and the molten silicon-germanium alloy is atomized.
To form a mist-like molten silicon-germanium alloy on the silicon substrate, and solidify the molten silicon-germanium alloy, so that when the molten silicon-germanium alloy is deposited on the silicon substrate, Furthermore, even if the substrate temperature is set to about 1200 ° C. where the re-diffusion amount of the buried layer is small, that is, the temperature of the silicon substrate is reduced, the warpage of the silicon substrate can be reduced.

Therefore, in a semiconductor integrated device using a semiconductor substrate manufactured by the method of the present invention, the amount of re-diffusion of the buried layer is small, and a reduction in chip area can be expected.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a manufacturing process of a semiconductor substrate according to the present invention.

FIG. 2 is a diagram for explaining a spray device used in the present invention.

FIG. 3 is a graph showing dependence of substrate warpage on germanium concentration.

FIG. 4 is a view for explaining a manufacturing process of a conventional dielectric isolation substrate.

FIG. 5 is a graph showing dependency of substrate warpage on single-crystal silicon substrate temperature.

FIG. 6 is a sectional view of a dielectric isolation substrate.

FIG. 7 is a cross-sectional view of an SOI substrate.

FIG. 8 is a sectional view of an IOP substrate.

[Explanation of symbols]

 Reference Signs List 51 single crystal silicon substrate 52 first oxide film 53 V-shaped groove 54 second oxide film 55 silicon-germanium alloy layer 56 processing reference surface 57 ... Single-crystal silicon island 58 ... Buried layer

Claims (2)

(57) [Claims] 1. A step of forming a groove in a silicon substrate, a step of forming an insulating film in the groove, and containing germanium at a concentration of 4.5 to 5.0 at.% Heated to about 1400 ° C. Molten silicon-germanium alloy to be heated to about 1200 ° C. before the silicon substrate
A step of supplying the insulating film in the groove , the step of solidifying the molten silicon-germanium alloy, and a table of the silicon substrate on which the groove is formed.
Polishing the surface opposite to the surface . 2. The method according to claim 1, wherein the molten silicon-germanium alloy is atomized by an inert gas and supplied onto the insulating film . Production method.