JP3329035B2 - Imaging signal defect detection and correction apparatus and video camera for detecting and correcting imaging signal defect - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device which is included in an image pickup signal obtained from a solid-state image pickup section provided with an image pickup surface section in which a plurality of pixels are arranged and arranged based on output signals from each of a plurality of pixels. An image signal defect detection and correction device for detecting a defect portion based on an output signal from a defective pixel in a surface portion and performing defect correction on an image signal including the defect portion, and a video camera for performing image signal defect detection and correction.
About Mela .

[0002]

2. Description of the Related Art A solid-state image pickup unit used to constitute a video camera or the like for forming a video signal has a semiconductor substrate in which a number of pixels for performing photoelectric conversion are formed and arranged in a number of parallel columns. It has an imaging surface portion provided with a charge transfer region formed by a charge-coupled device (CCD) or the like that transfers signal charges obtained in each pixel. It is not easy for the imaging surface section in such a solid-state imaging section to make all of an extremely large number of pixels properly function during the manufacturing process. It is likely to include defective pixels that cause abnormal operations due to the defective pixels. In addition, even after the solid-state imaging unit is actually used, there is a possibility that a defective pixel is partially included due to electrostatic breakdown or the like.

[0003] When a solid-state image pickup unit whose image pickup surface section includes a defective pixel is used, an output signal from each of the pixels on the image pickup surface unit is output from a large number of parallel columns formed by the pixels. Sampling readout is performed in accordance with the selected readout column, and an output signal from a defective pixel is mixed as a noise component into an image signal sequentially obtained, and a defective portion of the image signal is detected. Therefore, in a signal processing circuit unit to which an imaging signal from the solid-state imaging unit is supplied and forms an imaging output signal based on the imaging signal, a measure for a defective portion of the imaging signal caused by such a defective pixel, that is, a defect It is required that a correction be made.

Therefore, in the solid-state image pickup unit, when each pixel is brought into a state in which it should operate properly during the manufacturing process, a defective pixel included in the image pickup surface is detected and its position is specified. Test is performed, and the position of the defective pixel found in the test on the imaging surface is
For example, it is assumed that vertical address data specifying each of the parallel columns formed by a large number of pixels on the imaging surface portion and horizontal address data specifying each of the pixels in each of the parallel columns are stored and represented. Read-only memory (ROM) is provided,
It has been proposed that a ROM containing the defective pixel data be attached to a solid-state imaging unit. As described above, when the solid-state imaging unit having the ROM containing the defective pixel data attached thereto is used for actual use, a defective pixel obtained based on an output signal from each of the pixels on the imaging surface unit is used. The defect correction according to the defective pixel data read from the ROM is performed on the imaging signal including the defective portion due to the above, thereby removing or reducing the defective portion in the imaging signal. .

[0005]

However, as described above, the solid-state imaging unit has a ROM in which defective pixel data is stored.
It is extremely complicated to carry out a test for detecting defective pixels and locating the defective pixels at the stage when each pixel is put into a state where it should operate properly during the manufacturing process. Expensive test
It will be performed after the system is built. As a result, a large amount of cost is required to construct a test system, and a relatively large number of man-hours are allocated to a test using the test system, thereby increasing the manufacturing cost of the solid-state imaging unit. There is.

Further, a defective portion caused by a defective pixel included in an image signal obtained based on an output signal from each of the pixels on the image pickup surface of the solid-state image pickup unit is stored in a ROM.
Is effective for defective pixels generated in the manufacturing process of the solid-state imaging unit, but the solid-state imaging unit is used for actual use. Later, for example, the effect cannot be exerted on a defective pixel caused by electrostatic breakdown or the like.

In view of the above, according to the present invention, a large number of pixels performing photoelectric conversion are formed and arranged in a large number of parallel columns, and a charge transfer region for transferring signal charges obtained in each pixel is provided. A complex and expensive test system for detecting a defective pixel and specifying its position on the imaging surface of the solid-state imaging unit based on an imaging signal obtained from the solid-state imaging unit having the imaging surface unit configured as described above. And the like, and the defect including the defective pixel generated after the solid-state imaging unit is actually used is easily and reliably performed, and furthermore, the defect of the imaging signal caused by the detected defective pixel so that part of the correction is made just suitable, and an object thereof is to provide a video camera for image pickup signal defect detection and correction apparatus or image signal defect detection and correction.

[0008]

In order to achieve the above object, an image signal defect detecting and correcting apparatus according to a first aspect of the present invention comprises a plurality of horizontal rows of pixels and a plurality of vertical rows of pixels. A plurality of vertical charge transfer units along the vertical column of pixels; a first and a second horizontal charge transfer unit connected to the plurality of the vertical charge transfer units; and a first and a second horizontal charge transfer unit. has an imaging surface having a first and second charge output portion, in the odd field period, charges from people each of the odd-numbered pixels belonging to those in a plurality of horizontal pixel rows is more
Through the vertical charge transfer section and the first horizontal charge transfer section.
And the charge from each of the pixels belonging to the even-numbered pixels in the plurality of pixel horizontal columns is transferred to the plurality of vertical charge transfer units and the second horizontal charge transfer unit.
Through the second charge output unit, and supplies the first and second charge output units with odd-numbered pixels in the plurality of pixel horizontal columns.
The first imaging signal based on the charge from each of the pixels belonging to
Belongs to the even number in the horizontal row of pixels
The second imaging signal based on the charge from each of the pixels
And within the even field period, multiple pixel water
From each of the pixels belonging to the even-numbered
A plurality of vertical charge transfer units and a first horizontal charge transfer unit
To the first charge output unit through
Of pixels belonging to odd-numbered pixels in the horizontal row of pixels
The charge from each of the plurality of vertical charge transfer units and the second horizontal charge
Delivered to the second charge output unit through the load transfer unit,
And the second charge output unit is provided with even pixels in a plurality of pixel horizontal columns.
Based on the charge from each of the pixels belonging to the number one
Odd number in one image signal and a plurality of pixel horizontal rows
Imaging included in the first and second imaging signals with respect to the first and second imaging signals from the solid-state imaging unit that respectively obtain the second imaging signals based on the charges from the pixels belonging to each of the pixels. A defect correction unit that corrects a defective portion based on a defective pixel in the surface unit, a signal defect detection unit that detects a defective portion included in the first and second imaging signals, and a second unit that represents each of a plurality of horizontal rows of pixels. 1 address data and second address data representing each of the pixels in each horizontal row of pixels on the imaging surface portion. When a defective portion is detected by the signal defect detecting section, the first address data is replaced with the defective portion. The first address data is obtained as the first defective address data specifying the pixel horizontal row to which the defective pixel causing the problem belongs, and the second address data is obtained as the pixel data specified by the first defective address data. In addition to an address data generation unit that obtains the second defective address data for specifying the position of the defective pixel in the column, the defect data included in the first imaging signal is caused based on the first defective address data. First storage defect address data for specifying a pixel horizontal row to which a defective pixel belongs, and a second storage defect address data for specifying a pixel horizontal row to which a defective pixel causing a defective portion included in the second imaging signal belongs. A storage address data forming unit for obtaining defective address data; and a storage address data forming unit when the signal defect detecting unit detects a defective portion included in the first imaging signal or the second imaging signal. Writing of the first storage defect address data and the second defect address data from the storage device, and the second storage defect address data from the storage address data forming section. Less data and the second
A first imaging signal is sent to a defect correction unit based on a memory unit in which writing with the first defect address data is performed and the first storage defect address data and the second defect address data read from the memory unit. And a signal for causing the defect correction unit to perform a second image pickup signal based on the second storage defect address data and the second defect address data read from the memory unit. And a signal transmitting unit for transmitting a signal for causing a defect correction to be performed. A video camera for performing image signal defect detection and correction according to the second aspect of the present invention includes a plurality of pixel horizontal columns and a plurality of pixel vertical columns, and a plurality of vertical charge transfer units along the pixel vertical columns. ,
Imaging apparatus having first and second horizontal charge transfer units connected to a plurality of vertical charge transfer units, and first and second charge output units provided in the first and second horizontal charge transfer units Surface portion, and charges from each of pixels belonging to an odd-numbered pixel in a plurality of pixel horizontal columns are duplicated within an odd-numbered field period.
Through a number of vertical charge transfer units and a first horizontal charge transfer unit
The electric charge from each of the pixels belonging to the even-numbered pixels in the plurality of pixel horizontal columns is transferred to the first electric charge output unit and the plurality of vertical electric charge transfer units and the second horizontal electric charge transfer unit.
To the second charge output unit through the first and second charge output units .
Of the odd-numbered pixel horizontal rows
Imaging based on the charge from each of the pixels belonging to the first
Belongs to the even numbered signal and horizontal rows of pixels
Second image pickup signal husband based on charge from the respective pixels
And even more pixels within the even field period
From each of the pixels belonging to the even-numbered ones in the horizontal column
Charge is transferred to the plurality of vertical charge transfer units and the first horizontal charge transfer.
Out to the first charge output unit through the
Of pixels belonging to the odd-numbered
The charge from each of the plurality of vertical charge transfer units and the second horizontal charge transfer unit
The charge is transferred to the second charge output unit through the charge transfer unit,
In the first and second charge output units, a plurality of pixel horizontal columns
Based on the charge from each of the even-numbered pixels
Odd number in the first imaging signal and the plurality of pixel horizontal columns
And a first and second imaging signals for the first and second imaging signals from the solid-state imaging unit, from which a second imaging signal based on the charge from each of the pixels belonging to the solid-state imaging unit is obtained. A defect correction unit that corrects a defective portion based on a defective pixel in the imaging surface portion included in the imaging signal; a signal defect detection unit that detects a defect portion included in the first and second imaging signals; The first address data representing each of the columns and the second address data representing each of the pixels in each horizontal row of pixels on the imaging surface section are generated. When a defective portion is detected by the signal defect detection section, the first address data is generated. The address data is obtained as first defective address data for specifying a pixel horizontal row to which a defective pixel causing a defective portion belongs, and the second address data is obtained by the first defective address data. An address data generator for obtaining second defective address data for specifying a position of a defective pixel in a pixel horizontal row to be determined; and a cause of a defective portion included in the first image signal based on the first defective address data. The first storage defect address data for specifying the pixel horizontal column to which the defective pixel belongs, and the second storage pixel address for specifying the pixel horizontal column to which the defective pixel causing the defective portion included in the second imaging signal belongs. A storage address data forming unit for obtaining storage defect address data, and a signal defect detection unit,
When a defective portion included in the first imaging signal or the second imaging signal is detected, writing of the first storage defect address data and the second defect address data from the storage address data forming unit and storage are performed. For writing the second storage defect address data and the second defect address data from the storage address data forming unit, the first storage defect address data read from the memory unit, and the second storage defect address data. A signal for causing the defect correction unit to perform the defect correction on the first image pickup signal based on the defect address data of the second and the second address read from the memory unit.
And a signal transmission unit for transmitting a signal for causing the defect correction unit to perform defect correction on the second imaging signal based on the storage defect address data and the second defect address data. .

[0009]

In any of the imaging signal defect detection and correction device according to the first aspect of the present invention and the video signal defect detection and correction according to the second aspect of the present invention configured as described above. Also, in each field period, a first imaging signal formed based on an output signal from each of pixels belonging to an odd-numbered pixel in a plurality of pixel horizontal rows formed on the imaging surface portion, and an even-numbered In the case where there is a defective pixel on the imaging surface portion of the solid-state imaging portion that obtains the second imaging signal formed based on the output signal from each of the pixels belonging to Through detection of a defective portion caused by a defective pixel included in the first or second imaging signal, address data accurately representing the position of the defective pixel on the imaging surface portion is obtained, and the obtained address data is obtained. Operation data is stored in the memory unit,
This is performed as appropriate under the condition that the solid-state imaging unit is put into a state where it is actually used. Then, after the address data indicating the position of the defective pixel on the imaging surface portion is stored in the memory portion, the defective portion caused by the defective pixel included in the first or second imaging signal is removed from the memory portion. Correction is properly made under the timing setting based on the read address data.

Therefore, the image signal defect detecting and correcting apparatus according to the first aspect of the present invention, or the second aspect of the present invention.
According to the video camera that performs the image signal defect detection and correction according to the above, based on the first and second image signals obtained from the solid-state image pickup unit, detection of a defective pixel in an image pickup surface of the solid-state image pickup unit And its location can be determined easily and reliably as appropriate without any complicated and expensive test system, etc., and also including defective pixels generated after the solid-state imaging unit is put into actual use. And the result is stored. After that, the correction of the defective portion of the first or second image pickup signal caused by the detected defective pixel is performed based on the timing based on the specified result of the position of the stored defective pixel. With the setting made, it will be performed properly.

[0011]

FIG. 1 shows an example of an imaging signal defect detection and correction device according to the present invention and an imaging signal defect detection and correction device provided with the same according to the present invention.
1 shows an example of a video camera that performs signal defect detection and correction .

In FIG. 1, a number of pixels for performing photoelectric conversion are arranged and formed in a number of parallel columns.
A solid-state imaging unit 11 having an imaging surface portion provided with a charge transfer region formed by a CCD for transferring signal charges obtained in each pixel is provided. Also,
An optical system including a stop mechanism 12, a lens system 10, and the like is disposed in front of the solid-state imaging unit 11. This optical system allows external light to enter an imaging surface of the solid-state imaging unit 11. And project the subject image.

The solid-state image pickup unit 11 is, for example, an interline transfer type having an image pickup surface as shown in FIG. In the imaging surface section shown in FIG. 2, a large number of photoelectric conversion element sections 15 each constituting an individual pixel are provided on a semiconductor base 13 in a large number of horizontal directions (directions of arrows h).
Are arranged and arranged to form parallel rows (horizontal rows of pixels). The photoelectric conversion element unit 15 forming each of a large number of pixel horizontal columns also forms a large number of parallel columns (pixel vertical columns) extending in a vertical direction (direction of arrow v). A vertical charge transfer section 16 formed by a CCD group is arranged along each pixel vertical column formed by the element section 15. Each of the vertical charge transfer units 16 is driven by, for example, two-phase vertical transfer drive signals φV1 and φV2 to perform a charge transfer operation. Then, a charge readout gate 17 is provided between each of the plurality of photoelectric conversion element units 15 forming each pixel vertical column and the vertical charge transfer unit 16 corresponding to the vertical column.

One end of each of the plurality of vertical charge transfer sections 16 is connected to a CCD at an edge of the semiconductor substrate 13.
A first group formed by the group and extending in the horizontal direction;
Are formed by a CCD group and extend in the horizontal direction in the same manner as the first horizontal charge transfer unit 18 via a vertical transfer gate unit 19 extending in the horizontal direction. , And the second horizontal charge transfer unit 20. The vertical transfer gate unit 19 is driven by a transfer gate drive signal φVH, and each of the first and second horizontal charge transfer units 18 and 20 is driven by, for example, two-phase horizontal transfer drive signals φH1 and φH2. To perform a charge transfer operation. The first and second horizontal charge transfer units 18 and 20 are provided with charge output units 21 and 22, respectively, and output terminals 23 and 24 are led out of the charge output units 21 and 22, respectively.

When an imaging operation is performed in the solid-state imaging unit 11 having the imaging surface unit shown in FIG.
First, a predetermined light receiving period is set, and in the light receiving period, light from an object to be imaged is made to enter the imaging surface portion through an optical system including the lens system 10, the aperture mechanism 12, and the like. Accordingly, in the light receiving period, each of the plurality of photoelectric conversion element units 15 each forming a pixel receives light from the imaging target, performs photoelectric conversion, and accumulates electric charges.

Thereafter, during the charge readout period, each of the plurality of charge readout gates 17 takes a state in which the charge accumulated in the corresponding photoelectric conversion element 15 is read out to the corresponding vertical charge transfer unit 16. Is done. Subsequently, the charges read to the respective vertical charge transfer units 16 are transferred to the respective vertical charge transfer units driven by the two-phase vertical transfer drive signals φV1 and φV2 supplied to the solid-state imaging unit 11 from the drive signal forming unit 25. By the 16 charge transfer operations, the charge obtained by the plurality of photoelectric conversion element units 15 forming each pixel horizontal column is sequentially transferred to the first and second horizontal charge transfer units 18 and 20. . At this time, the vertical transfer gate unit 19 driven by the transfer gate drive signal φVH supplied from the drive signal forming unit 25 to the solid-state imaging unit 11 also includes a plurality of photoelectric conversion element units 15 forming one pixel horizontal column. The obtained charge contributes to the transfer to the second horizontal charge transfer unit 20, and the charge obtained by the plurality of photoelectric conversion element units 15 forming each pixel horizontal row alternately becomes the first charge. The horizontal charge transfer unit 18 and the second horizontal charge transfer unit 20 of FIG.

Further, the first and second horizontal charge transfer units 1
8 and 20, the two-phase horizontal transfer drive signal φ supplied from the drive signal forming unit 25 to the solid-state imaging unit 11
The first and second horizontal charge transfer units 1 are driven by the charge transfer operation performed by being driven by H1 and φH2.
The charges obtained by the plurality of photoelectric conversion element units 15 forming one horizontal row of pixels, which are sequentially transferred to 8 and 20, respectively, are transferred to the charge output units 21 and 22. In the charge output unit 21, the charges transferred by the first horizontal charge transfer unit 18 are sequentially converted into a signal, led out to the output terminal 23, and stored in the output terminal 23 in the plurality of photoelectric conversion element units 15. An imaging signal I corresponding to an imaging target based on electric charge
P1 is obtained. Similarly, in the charge output unit 22,
The charge transferred by the second horizontal charge transfer unit 20 is sequentially converted into a signal and led out to the output terminal 24.
4, an imaging signal IP <b> 2 corresponding to an imaging target is obtained based on the charges accumulated in the plurality of photoelectric conversion element units 15.

In such a case, each of the vertical charge transfer units 16 and the vertical transfer units for the one pixel horizontal column of the charges obtained by the plurality of photoelectric conversion element units 15 forming each of the all pixel horizontal columns on the imaging surface unit. First and second gates 19
Transfer to the horizontal charge transfer units 18 and 20 is completed within each field period, and one pixel horizontal column is sequentially transferred to the first and second horizontal charge transfer units 18 and 20, respectively. First and second horizontal charge transfer units 18 and 20 of the charges obtained by the plurality of photoelectric conversion element units 15
Are supplied to the charge output units 21 and 22 in such a manner as to end within each line period.
The phase vertical transfer drive signals φV1 and φV2 and the two-phase horizontal transfer drive signals φH1 and φH2 are set, respectively. Therefore, each of the imaging signal IP1 derived to the output terminal 23 and the imaging signal IP2 derived to the output terminal 24 has a repetition of a field period formed by a series of line periods. Will be done.
Therefore, in the odd-numbered field period, the imaging signal IP1 for one field period is obtained at the output terminal 23, and the imaging signal IP2 for one field period is obtained at the output terminal 24.
In the even-numbered field period, the imaging signal IP1 for one field period is obtained at the output terminal 23, and the imaging signal IP2 for one field period is obtained at the output terminal 24.

In the odd field period,
The photoelectric conversion element unit 15 that forms each of the odd-numbered ones (odd-numbered pixel horizontal rows) when viewed from the first and second horizontal charge transfer units 18 and 20 out of the large number of horizontal rows of pixels in the imaging surface unit. The obtained charges are sequentially transferred to the charge output unit 21 by the first horizontal charge transfer unit 18, and the first horizontal charge out of a large number of pixel horizontal rows on the imaging surface unit.
The charges obtained by the photoelectric conversion element units 15 forming the even-numbered ones (even pixel horizontal rows) as viewed from the second horizontal charge transfer units 18 and 20 are sequentially transferred to the second horizontal charge transfer units 18 and 20. The charge is transferred to the charge output unit 22 by the charge transfer unit 20.
In the even-numbered field period, the photoelectric conversion element unit 15 that forms each of the horizontal rows of the even-numbered pixels in the imaging surface unit is used.
Are sequentially transferred to the first horizontal charge transfer unit 1
8 and transferred by the second horizontal charge transfer unit 20 to the charge output unit 21, and the charges obtained by the photoelectric conversion element unit 15 forming each of the odd-numbered pixel horizontal rows in the imaging surface unit are sequentially transferred by the second horizontal charge transfer unit 20. The charge is transferred to the charge output unit 22.

Therefore, in the odd field period,
At an output terminal 23 derived from the charge output unit 21, an imaging signal for a line period based on the charge obtained by the photoelectric conversion element unit 15 forming each of the odd-numbered pixel horizontal rows is provided with an odd-numbered imaging signal on the imaging surface unit. An imaging signal IP1 for one field period formed continuously by the number of horizontal columns is obtained, and an output terminal 24 derived from the charge output unit 22 is connected to
An imaging signal for a line period based on the charge obtained by the photoelectric conversion element unit 15 forming each of the horizontal rows of the even-numbered pixels,
An imaging signal IP2 for one field period formed continuously by the number of horizontal rows of even-numbered pixels on the imaging surface is obtained. In the even-numbered field period, an imaging signal for a line period based on the charge obtained by the photoelectric conversion element unit 15 forming each of the horizontal rows of the even-numbered pixels is supplied to the output terminal 23 derived from the charge output unit 21. Obtains an image signal IP1 for one field period formed continuously by the number of even-numbered pixel horizontal columns on the imaging surface portion, and outputs each of the odd-numbered pixel horizontal columns to an output terminal 24 derived from the charge output unit 22. The imaging signal for the line period based on the charge obtained by the photoelectric conversion element unit 15 to be formed is obtained as the imaging signal IP2 for the one-field period formed by connecting the odd-numbered horizontal columns on the imaging surface unit. Can be

The drive signal forming unit 25 is supplied with the vertical clock signal CLV, the horizontal clock signal CLH, and the read command signal CR from the timing signal generating unit 26, and receives the two-phase vertical transfer drive signals φV1 and φV2. And the transfer gate drive signal φVH to the vertical clock signal C.
LV, and each of the two-phase horizontal transfer driving signals φH1 and φH2 is
H, and supplies them to the solid-state imaging unit 11 in accordance with the read command signal CR. The timing signal generating section 26 is supplied with the vertical synchronizing signal SV and the horizontal synchronizing signal SH from the synchronizing signal generating section 27, and further stores an accumulation command signal CC from a defect detecting section 40 described later.
Under the supply of G, a vertical clock signal CLV is formed based on the horizontal synchronization signal SH, and the horizontal clock signal CLH has a frequency significantly higher than that of the horizontal synchronization signal SH. The read command signal CR is formed based on the accumulation command signal CCG, and is supplied to the drive signal forming unit 25.

FIGS. 3 and 4 show the imaging signals IP1 and IP1 obtained at the output terminals 23 and 24, respectively, as described above.
2 is shown. FIG. 3 mainly shows a situation in an odd field period, and as shown in FIG.
In the odd-numbered field period OF starting from the leading edge of the vertical synchronization signal SV shown in FIG. 3B, the thirteenth counting from the start of the odd-numbered field period OF of the horizontal synchronization signal SH shown in FIG. After that of FIG.
As shown in FIG. 2, an image signal IP1 is formed in which image signals for a line period are continuously formed based on the charges obtained by the photoelectric conversion element units 15 forming each of the odd-numbered pixel horizontal columns. Odd field period O of synchronization signal SH
After the fourteenth pixel counting from the start point of -F, as shown in FIG. 3E, the line period based on the charge obtained by the photoelectric conversion element unit 15 forming each of the horizontal rows of the even-numbered pixels. Are obtained in succession, the image pickup signal IP2 is formed. Odd numbers given to each line period in the imaging signal IP1 and even numbers given to each line period in the imaging signal IP2 are pixels on the imaging surface where the charges forming the imaging signal for the line period are obtained. The numbers from the first horizontal charge transfer unit 18 side of the horizontal row are shown. In this example, this corresponds to a 20-line period from a point three lines before the start of the odd field OF until a lapse of 17 lines from the start of the odd field OF. The period is actually a vertical blanking period TBLK.

Similarly, FIG. 4 mainly shows a state in an even field period, and as shown in FIG.
In the even-numbered field period EF starting from the leading edge of the vertical synchronization signal SV shown in FIG. 4B, the horizontal synchronization signal SH (even-numbered field period OF shown) shown in FIG. There is a gap of 0.5 line period)
14 from the start of the even field period EF of
From the third pixel onward, as shown in FIG. 4D, image signals for a line period based on the charges obtained by the photoelectric conversion element units 15 forming each of the horizontal rows of the even-numbered pixels are continuously formed. The imaging signal IP1 is obtained, and each of the odd-numbered pixel horizontal columns is formed as shown in FIG. 4E after the fourteenth counting from the start of the even-numbered field period EF of the horizontal synchronization signal SH. The imaging signal IP2 is formed by continuously forming imaging signals for the line period based on the charges obtained by the photoelectric conversion element unit 15.
The even number given to each line period in the imaging signal IP1 and the odd number given to each line period in the imaging signal IP2 are pixels on the imaging surface portion where the charges forming the imaging signal for the line period are obtained. The numbers from the first horizontal charge transfer unit 18 side of the horizontal row are shown. In this case, a period corresponding to a 20-line period from a point three lines before the start of the even field EF to a lapse of seventeen lines from the start of the even field EF is also: Actually, it is set as a vertical blanking period TBLK.

An image pickup signal IP obtained at output terminals 23 and 24 provided on an image pickup surface of the solid-state image pickup unit 11, respectively.
1 and IP2 are the sampling and holding units 30 and 3
3 is supplied. In the sampling and holding section 30, the level of the image pickup signal IP1 is sampled every predetermined short period and the sample level is held to obtain a sampling and holding output signal SI1, which is analog / digital (A / D). ) Is supplied to the conversion unit 31. In the A / D converter 31, the imaging signal IP1 is digitized based on the sampling and holding output signal SI1, and a digital imaging signal DI1 corresponding to the imaging signal IP1 is obtained from the A / D converter 31. Then, it is supplied to the defect correction unit 32. Similarly, in the sampling and holding unit 33, the imaging signal IP2
Is sampled at predetermined short intervals and the sample level is held, thereby obtaining a sampling and holding output signal SI2, which is supplied to the A / D converter. In the A / D converter 34, the imaging signal IP based on the sampling and holding output signal SI2
2 is achieved, a digital image pickup signal DI2 corresponding to the image pickup signal IP2 is obtained from the A / D conversion section 34, and is supplied to the defect correction section 35.

The defect correction units 32 and 35 have defect correction instruction signals CD1 and CD2 sent from the defect detection unit 40.
Are also supplied respectively. The defect correction section 32 responds to the defect correction instruction signal CD1 by using the digital imaging signal DI1.
Of the photoelectric conversion element sections 15 in the imaging surface section of the solid-state imaging section 11 included in the above, correction of a defective portion caused by a defective pixel is performed. The defect correction unit 35 corrects a defect portion included in the digital imaging signal DI2 caused by a defective pixel on the imaging surface of the solid-state imaging unit 11 in response to the defect correction instruction signal CD2. Is performed.

The defect correction section 32 corrects a defective portion in the digital image pickup signal DI1 according to the defect correction instruction signal CD1, and the defect correction section 35 corrects a defect portion in the digital image pickup signal DI2 according to the defect correction instruction signal CD2. As for the method, a defect correction method for an imaging signal obtained from a solid-state imaging unit that has already been proposed is appropriately adopted. Then, the digital image pickup signal DIC1 obtained by subjecting the digital image pickup signal DI1 to defect correction according to the defect portion included in the digital image pickup signal DI1 is transmitted from the defect correction section 32, and the defect correction section 35 outputs
A digital image pickup signal DIC2 obtained by subjecting the digital image pickup signal DI2 to defect correction according to a defect portion included in the digital image pickup signal DI2 is transmitted.

The digital image pickup signal DIC1 obtained from the defect correction section 32 and the digital image pickup signal DIC2 obtained from the defect correction section 35 are supplied to a signal processing section 36. In the signal processing section 36, the digital imaging signal D
Various processing for each of IC1 and DIC2, synthesis of digital imaging signal DIC1 and digital imaging signal DIC2 subjected to various processing, digital imaging signal D
Various processes are performed on a signal obtained by synthesizing the IC1 and the digital imaging signal DIC2, and a video signal DV based on the imaging signals IP1 and IP2 obtained from the solid-state imaging unit 11 is formed. Is done.

The defect detector 40 includes a digital imaging signal DI1 from the A / D converter 31, a digital imaging signal DI2 from the A / D converter 34, and a timing signal generator 2.
6, a vertical clock signal CLV, a horizontal clock signal CLH, a read command signal CR, and a synchronization signal generator 2
7 and the reset signal CRS and the defect detection command signal CST from the control unit 41 are supplied. When the digital imaging signal DI1 or the digital imaging signal DI2 includes a defective portion caused by a defective pixel on the imaging surface of the solid-state imaging unit 11, the defect detection unit 40 detects the digital imaging signal DI1 or the digital imaging signal DI1. A defective portion in the DI2 is detected, and a defective pixel on the imaging surface of the solid-state imaging unit 11 that is responsible for the detected defective portion is identified by a vertical address AV and a horizontal address AH relating to the imaging surface, and the defective pixel is identified. Vertical address AV for specifying
And an operation for storing defect address data representing each of the horizontal addresses AH in a built-in memory unit, and a defect correction instruction to take appropriate timing based on the defect address data stored in the built-in memory unit The signals CD1 and CD2 are formed and supplied to the defect correction units 32 and 35, respectively.

The vertical address AV and the horizontal address AH for the imaging surface portion are as follows.
The horizontal direction address AH is an address for specifying each of a number of horizontal rows of pixels on the imaging surface section, and the address for specifying the position of each pixel in each of the horizontal rows of pixels on the imaging surface section. Therefore, the address represented by the defective address data is the vertical address A that specifies the pixel horizontal row to which the defective pixel belongs on the imaging surface portion.
V and a horizontal address AH for specifying the position of the defective pixel in the pixel horizontal column specified by the vertical address AV.

Further, the defect detecting section 40 supplies the accumulation command signal CCG to the timing signal generating section 26 through such an operation, and detects and detects a defective portion in the digital imaging signal DI1 or DI2. When the operation of storing the defective address data for specifying the defective pixel on the imaging surface portion of the solid-state imaging unit 11 that is the cause of the detected defective portion in the built-in memory unit is completed, the control unit 4 outputs the detection end signal CE.
Send to 1.

The control unit 41 makes the defect detection unit 40
A defective portion in the digital imaging signal DI1 or the digital imaging signal DI2 is detected, and defective address data for specifying a defective pixel in the imaging surface portion of the solid-state imaging unit 11 that is responsible for the detected defective portion is stored in a built-in memory unit. A defect detection operation switch 42 that is operated so as to perform the following operation is provided. Then, when the defect detection operation switch 42 is turned on by operating the defect detection operation switch 42, the control unit 41 first supplies a reset signal CRS to the defect detection unit 40, and subsequently, outputs a defect detection command signal CST to the defect detection unit 40. Thereafter, the signal is supplied to each of the defect detection unit 40 and the drive signal forming unit 25 until the detection end signal CE arrives from the defect detection unit 40.

The drive signal forming unit 25 includes a control unit 41
Is supplied with the defect detection command signal CST, the diaphragm mechanism drive signal CI supplied to the diaphragm mechanism 12 causes the diaphragm mechanism 12 to assume the full aperture state. When the aperture mechanism 12 is in the full aperture state,
The imaging surface portion of the solid-state imaging unit 11 is maintained in a state in which external light does not substantially enter. After that, the drive signal forming unit 2
5 from the control unit 41 for the defect detection command signal C
When the supply of ST is stopped, the drive signal forming unit 25 returns the aperture mechanism drive signal CI supplied to the aperture mechanism 12 to the one that causes the aperture mechanism 12 to assume a state before the supply of the defect detection command signal CST. .

When the reset signal CRS is supplied from the control unit 41, the defect detection unit 40
The defective address data stored in the built-in memory unit is erased to prepare for writing new defective address data to the built-in memory unit. Then, subsequently, the defect detection command signal C coming from the control unit 41
In accordance with ST, under the condition that the aperture mechanism 12 assumes the full aperture state, a defective portion in the digital imaging signal DI1 or the digital imaging signal DI2 is detected, and the solid-state imaging unit 11 which is responsible for the detected defective portion is detected. An operation of storing defective address data for specifying a defective pixel on the imaging surface portion in a built-in memory portion is started.

FIG. 5 shows an example of a specific configuration of the defect detection section 40. In this example, the signal input terminals 56 and 57
The horizontal synchronizing signal SH and the vertical synchronizing signal SV from the synchronizing signal generator 27 are respectively supplied. Vertical synchronization signal SV
As shown in FIG. 6A, the odd-numbered field period OF and the even-numbered field period EF are alternately set in each cycle as shown in FIG. 6B. . The signal input terminals 54 and 55 are connected to the vertical clock signal CLV from the timing signal generator 26.
And the horizontal clock signal CLH are supplied.

The defect detection operation switch 42 provided in the control unit 41 is operated to be turned on, and accordingly, the reset signal CRS and the subsequent defect detection command signal CST are sent from the control unit 41. Then, the defect detection command signal CST is supplied to the signal input terminal 58 at the timing shown in FIG. 6C, for example. When the defect detection command signal CST is supplied to the signal input terminal 58 as shown in FIG. 6C, the supply start time of the defect detection command signal CST is
Imaging signals IP1 and IP2 obtained from the solid-state imaging unit 11
In the video signal output period TCO in which the digital imaging signals DI1 and DI2 based on the digital imaging signals DI1 and DI2 are formed and the video signal DV formed based on the digital imaging signals DI1 and DI2 is derived to the output terminal 37. It is said. In such a video signal output period TCO,
The digital imaging signal DI is input to the signal input terminals 51 and 52.
1 and DI2 are supplied, respectively, as shown at F and G in FIG.

The digital image pickup signal DI1 supplied to the signal input terminal 51 is obtained in the odd field period OF by the photoelectric conversion element section 15 which forms each of the odd-numbered pixel horizontal rows on the image pickup surface of the solid-state image pickup section 11. An odd line field period signal OLF is formed as a series of image signals for a line period based on the received charges, and in the even field period EF, the even pixel horizontal line of the imaging surface of the solid-state imaging unit 11 is formed. An image signal for a line period based on the electric charge obtained by the photoelectric conversion element unit 15 forming each of them is taken as an even line field period signal ELF formed continuously. On the other hand, in the odd field period OF, the digital imaging signal DI2 supplied to the signal input terminal 52 is an even line field period signal.
ELF, and in an even field period EF, an odd line field period signal OLF.

Further, before the supply of the defect detection command signal CST in the video signal output period TCO, the storage command signal generating section 60 to which the vertical synchronizing signal SV is supplied through the signal input terminal 57 and the signal input terminal 58 Is not supplied, so that the accumulation command signal CCG obtained from the accumulation command signal generator 60 is not supplied.
Is a pulse signal that appears in synchronization with the vertical synchronization signal SV as shown in FIG. 6D. Then, when the defect detection command signal CST is supplied to the accumulation command signal generation unit 60 through the signal input terminal 58, the accumulation command signal generation unit 60 thereafter thereafter immediately before the start of the supply of the defect detection command signal CST. After the accumulation command signal CCG is generated as a pulse signal synchronized with the vertical synchronization signal SV, the accumulation command is generated until a preset period TCG corresponding to, for example, an n-field period (eg, a 9-field period) elapses. The signal CCG is not generated, and thereafter, when the period TCG elapses, the accumulation command signal CCG is generated as a pulse signal appearing in synchronization with the vertical synchronization signal SV, and after that, after a period corresponding to two field periods, Thereafter, the accumulation command signal CCG is again changed to the vertical synchronization signal SV.
Is generated as a pulse signal appearing in synchronization with.

In this way, as shown in FIG. 6D, the accumulation command signal CCG which does not appear during the period TCG is sent out through the signal output terminal 61 and supplied to the timing signal generator 26. You. The timing signal generator 26 sends the read command signal CR as a pulse train signal issued in synchronization with the accumulation command signal CCG. Therefore, during the period TCG, the read command signal C
R is not emitted. Therefore, within the period TCG, the two-phase vertical transfer drive signals φV1 and φV2, the transfer gate drive signal φVH, and the two-phase horizontal transfer drive signals φH1 and φH1 from the drive signal forming unit 25 to the solid-state imaging unit 11 are output. φH2 is not supplied, and the charge obtained by the photoelectric conversion element unit 15 on the imaging surface of the solid-state imaging unit 11 is read out to the vertical charge transfer unit 16, and the read charge is transferred by the vertical charge transfer unit 16. And the transfer by the first and second horizontal charge transfer units 18 and 20 is not performed, so that the imaging signals IP1 and IP2 cannot be obtained from the solid-state imaging unit 11,
Accordingly, the digital image pickup signals DI1 and DI2 are not supplied to the signal input terminals 51 and 52.

As described above, during the period TCG, the charge accumulation state on the imaging surface portion of the solid-state imaging section 11 is set. At this time, the diaphragm mechanism disposed in front of the solid-state imaging section 11 Since the aperture 12 is in the full aperture state, the imaging surface of the solid-state imaging unit 11 is substantially in a state where external light is not incident, and the photoelectric conversion element 15 accumulates charges due to external light. Is not done.

When the end point of the period TCG arrives, the accumulation command signal CCG is generated from the accumulation command signal generator 60 as a pulse signal appearing in synchronization with the vertical synchronizing signal SV, and transmitted through the signal output terminal 61. Is done. As a result, the timing signal generator 26
At the end of period TCG, read command signal CR is transmitted as a pulse train signal issued in synchronization with accumulation command signal CCG. As a result, the two-phase vertical transfer drive signals φV1 and φV1 from the drive signal forming unit 25 to the solid-state imaging unit 11 are output.
V2, the supply of the transfer gate drive signal φVH and the two-phase horizontal transfer drive signals φH1 and φH2 were started at the end of the period TCG, and were obtained by the photoelectric conversion element unit 15 on the imaging surface of the solid-state imaging unit 11. The reading of the charges to the vertical charge transfer unit 16 and the transfer of the read charges by the vertical charge transfer unit 16 and the transfer by the first and second horizontal charge transfer units 18 and 20 are performed at the end of the period TCG. Be started.

In this case, the charge obtained by the photoelectric conversion element 15 on the imaging surface of the solid-state imaging unit 11 is read out to the vertical charge transfer unit 16 and the read charge is transferred by the vertical charge transfer unit 16. The transfer by the first and second horizontal charge transfer units 18 and 20 includes the reading and transfer of charges from a region of the imaging surface that does not directly contribute to the formation of an image signal. This takes place over a longer period of time. Thereby, the imaging state representing the charge state of each photoelectric conversion element unit 15 when the period TCG elapses from the solid-state imaging unit 11 when the imaging surface of the solid-state imaging unit 11 is substantially in a state where external light does not enter. The signals IP1 and IP2 are obtained, and accordingly, the digital imaging signals DI based on the imaging signals IP1 and IP2 at that time are input to the signal input terminals 51 and 52.
1 and DI2 are supplied during a period TDD which is longer than one field period starting from the end of the period TCG, as shown in F and G of FIG.

The storage command signal CCG issued from the storage command signal generator 60 is also supplied to the memory write control signal generator 62, and is supplied from the memory write control signal generator 62 at the end of the period TCG. Storage command signal C
Depending on the CG, the period TCG, as shown in FIG.
, A memory write control signal CWC which takes a high level over a two-field period from the end of is supplied to the control terminal of the memory unit 63. Memory unit 63
Is provided with a first memory area 63A and a second memory area 63B which are formed similarly to each other, and a memory write control signal supplied from a memory write control signal generator 62. Only when CWC is at a high level, data can be written in each of the first memory area 63A and the second memory area 63B. Otherwise, the first memory area 63A and the second memory area 63A can be written. Data can be read from each of the areas 63B, or data can be erased. Therefore, the digital imaging signals DI1 and DI2 are applied to the signal input terminals 51 and 52, respectively, as shown in FIG.
As shown in F and G of FIG. 7, when supplied in the period TDD, each of the first memory area 63A and the second memory area 63B in the memory unit 63 can write data. Put in.

The digital imaging signal DI1 supplied to the signal input terminal 51 during the period TDD is
, The black level is fixed, and in the blanking unit 66, blanking is performed on a portion other than the portion obtained based on the charges from the photoelectric conversion element portions 15 forming the horizontal rows of pixels in the imaging surface portion of the solid-state imaging portion 11. Ranking is applied to the digital image signal DI1 ', which is supplied to the level comparing section 67. In the digital imaging signal DI2 supplied to the signal input terminal 52 during the period TDD, the black level of the digital imaging signal DI2 is fixed at the clamp unit 68. Further, the blanking unit 69 displays each pixel horizontal column on the imaging surface of the solid-state imaging unit 11. Blanking is applied to portions other than the portion obtained based on the charges from the photoelectric conversion element portion 15 to be formed, and the blanking portion is supplied to the level comparing portion 70 as a digital imaging signal DI2 '. The digital imaging signals DI1 ′ and DI2 ′ are obtained by setting the aperture mechanism 12 to the full aperture state and setting the imaging surface of the solid-state imaging unit 11 to a state where substantially no external light is incident.
1 and IP2, the level of each pixel should be low when the pixel on the imaging surface, that is, the photoelectric conversion element unit 15 operates properly. In other words, in each of the digital imaging signals DI1 'and DI2', if there is a portion having a relatively large level, that portion is a defective portion caused by a defective pixel on the imaging surface portion.

Each of the level comparison sections 67 and 70 is supplied with reference level data DX representing a preset reference level from the reference level generation section 71. And
In the level comparing section 67, the digital imaging signal DI
1 'and the reference level represented by the reference level data DX are compared. From the level comparing section 67, when the level of the digital imaging signal DI1' is lower than or equal to the reference level, it indicates a low level, and the level of the digital imaging signal DI1 ' Is higher than the reference level, level comparison data DD1 representing a high level is obtained. Therefore, when the digital image pickup signal DI1 'is appropriate and has a relatively low level, the level comparison data DD1 indicating a low level is obtained, and the digital image pickup signal DI1 is obtained.
In the case where 1 'includes a defective portion which is assumed to take a relatively large level, level comparison data DD1 representing a high level is obtained corresponding to the defective portion, and the digital image pickup signal The defective portion included in DI1 'is detected by setting the level comparison data DD1 to a high level.

In the level comparing section 70, the level of the digital image pickup signal DI2 'and the reference level data DX
Is compared with a reference level represented by
Thus, level comparison data DD2 representing a low level when the level of the digital imaging signal DI2 'is equal to or lower than the reference level, and representing a high level when the level of the digital imaging signal DI2' exceeds the reference level is obtained.
Therefore, when the digital imaging signal DI2 'is appropriate and has a relatively low level, level comparison data DD2 representing a low level is obtained, and the digital imaging signal DI2' takes a relatively high level. Is included, the level comparison data DD representing a high level corresponding to the defective portion.
2 is obtained, and the digital imaging signal DI2 ′
Are detected when the level comparison data DD2 takes the high level.

The level comparison data DD1 obtained from the level comparison section 67 and the level comparison data DD2 obtained from the level comparison section 70 are supplied to the first memory area 63A and the second memory area 63B in the memory section 63, respectively. At the same time, it is supplied to the storage address data forming section 72.

In this case, the vertical clock signal CLV through the signal input terminal 54 is supplied to the vertical address counter (V-address counter) 73, and the horizontal clock signal CLH through the signal input terminal 55 is supplied in the horizontal direction. Address counter (H-address counter) 74
Supplied to Further, the V-address counter 73 is connected to the timing signal generator 2 through the signal input terminal 53.
6, a read command signal CR formed based on the accumulation command signal CCG is supplied as a reset signal.
The address counter 74 has a vertical clock signal C
LV is supplied as a reset signal.

Thus, the V-address counter 73
The H-address counter 74 counts the vertical clock signal CLV and sends the count data DAV under the condition that the count value is reset each time the read command signal CR arrives. Under the condition that the count value is reset every time the signal CLV arrives, the horizontal clock signal CLH
And sends out the count data DAH. Therefore, V
-Count data DAV obtained from the address counter 73
Changes in synchronization with the charge transfer in the vertical charge transfer unit 16 in the imaging surface unit in the solid-state imaging unit 11,
Further, the content of the count data DAH obtained from the H-address counter 74 changes in synchronization with the charge transfer in each of the first and second horizontal charge transfer units 18 and 20 on the imaging surface of the solid-state imaging unit 11. It is said.
Therefore, the content of the count data DAV obtained from the V-address counter 73 is based on the imaging signal I from the solid-state imaging unit 11.
When P1 and IP2 are obtained, at each point in time, a pixel that has provided a charge that is to form each of the imaging signals IP1 and IP2 obtained at that time, that is, a pixel horizontal row to which the photoelectric conversion element unit 15 belongs And an H-address counter 7
When the imaging signals IP1 and IP2 are obtained from the solid-state imaging unit 11, the content of the count data DAH obtained from No. 4 is to form the imaging signals IP1 and IP2 obtained at that time at each time. The horizontal address AH that specifies the position of the pixel that has provided the electric charge, that is, the position of the photoelectric conversion element unit 15 in the pixel horizontal row to which the photoelectric conversion element unit 15 belongs is represented. V-address counter 73;
The H-address counter 74 includes an address data generator.
It is formed.

Therefore, during the period TDD, when the level comparison data DD1 from the level comparison section 67 indicates a high level, and a defective portion included in the digital image pickup signal DI1 'is detected, then V- The vertical address AV represented by the count data DAV obtained from the address counter 73 represents the pixel horizontal row to which the defective pixel on the imaging surface portion that causes the defective portion belongs, and at that time, the H-address counter 74 The horizontal address AH represented by the count data DAH obtained from the above indicates the position of the defective pixel on the imaging surface portion that causes the defective portion in the pixel horizontal row to which the defective pixel belongs. Therefore, the count data DAV and the count data DAH constitute defect address data. Similarly, in the period TDD, the level comparing section 70
Is set to a high level, and when a defective portion included in the digital image pickup signal DI2 'is detected, the count data DAV obtained from the V-address counter 73 at that time is also used. Represents the horizontal row of pixels to which a defective pixel on the imaging surface portion that causes the defective portion belongs, and the horizontal address AV represents the count data DAH obtained from the H-address counter 74 at that time. The direction address AH indicates the position of the defective pixel in the pixel horizontal row to which the defective pixel belongs on the imaging surface portion that causes the defective portion. Therefore, the count data DAV and the count data DAH constitute defect address data.

The horizontal synchronizing signal SH and the vertical synchronizing signal SV supplied to the signal input terminals 56 and 57, respectively, are supplied to the field discriminator 64. Field discriminator 6
4, the imaging signals IP1 and IP2 obtained from the solid-state imaging unit 11 at each time point based on the horizontal synchronization signal SH and the vertical synchronization signal SV, and further, the imaging signal IP
1 and IP2, it is determined whether the digital imaging signals DI1 ′ and DI2 ′ are obtained under an odd field period or an even field period. The determination output data DF representing the odd field period or the even field period as the determination result is supplied to the storage address data forming unit 72.

Under such circumstances, the V-address counter 73
Is supplied to the storage address data forming section 72, and the count data DAH obtained from the H-address counter 74 is stored in the memory section 6
3 is supplied to each of the first memory area 63A and the second memory area 63B. In the storage address data forming unit 72, when the level comparison data DD1 from the level comparison unit 67 or the level comparison data DD2 from the level comparison unit 70 indicates a high level, the vertical address represented by the count data DAV. AV
, An address conversion is performed in which a change is selectively applied in a different manner depending on whether the discrimination output data DF from the field discriminating unit 64 indicates an odd field period or an even field period. Storage defect address data DAVM1 and DAVM representing direction addresses AVM1 and AVM2, respectively.
VM2 is formed, and these are supplied to the first memory area 63A and the second memory area 63B in the memory unit 63, respectively. Indicates the vertical address AVM1
First to which the storage defect address data DAVM1 is supplied
Memory area 63A is a digital
Formation of defect correction instruction signal CD1 for image pickup signal DI1
The defect address data provided to the
For storing a vertical address AVM2.
Second memo to which defective address data DAVM2 is supplied
The area 63B stores the digital image signal as described later.
Signal DI2 for the signal DI2.
The defective address data to be stored
As can be understood, the vertical address AVM1 is
Digital imaging signal DI1 'or DI2'
The pixel horizontal row to which the defective pixel belongs when the defective part is detected
Digital address based on vertical address AV
Included in imaging signal IP1 converted to imaging signal DI1
Identify the pixel horizontal row to which the defective pixel causing the defective portion belongs.
And the vertical address AVM2
Is a digital imaging signal based on the vertical address AV.
Part included in the image pickup signal IP2 converted to the signal DI2
Identify the pixel horizontal row to which the defective pixel responsible for the minute belongs
It is assumed. The husband of the imaging signals IP1 and IP2
Odd and even field periods for each
State during the, is as shown in Figures 3 and 4
Therefore, the pixel horizontal row to which the defective pixel belongs is odd-numbered.
, The vertical address AVM2 is the same
The pixel horizontal column to which the defective pixel belongs is identified by a vertical address AV
It will be specified with a value larger than M1 by "1".
On the other hand, the pixel horizontal row to which the defective pixel belongs is even-numbered.
When the vertical address AVM2 has the same defect
The pixel horizontal column to which the pixel belongs is designated by a vertical address AVM1.
Will be specified with the same value as.

For this reason, the address conversion performed in the storage address data forming section 72 is performed as follows. (1) When the level comparison data DD1 indicates a high level while the discrimination output data DF indicates an odd field period, the storage address data DAVM1 indicates the vertical address AV indicated by the count data DAV as it is. In addition to the vertical address AVM1, the vertical address AV represented by the count data DAV is increased by "1" to be the vertical address AVM2 represented by the storage defect address data DAVM2. (2) If the discrimination output data DF indicates an odd field period and the level comparison data DD2 indicates a high level, the vertical address AV indicated by the count data DAV is used as the storage defect address data DAVM1 as it is. The vertical address AVM1, which represents
In addition, the vertical address AVM2 represented by the storage defect address data DAVM2 is used. (3) If the level comparison data DD1 indicates a high level while the discrimination output data DF indicates an even field period, the storage defect address data DAVM1 is used as the vertical address AV indicated by the count data DAV. The vertical address AVM1, which represents
In addition, the vertical address AVM2 represented by the storage defect address data DAVM2 is used. (4) When the discrimination output data DF indicates an even-numbered field period and the level comparison data DD2 indicates a high level, the vertical address AV indicated by the count data DAV is decreased by "1". The vertical address AVM represented by the storage defect address data DAVM2 is used as the vertical address AVM1 represented by the count data DAV, while the vertical address AVM1 represented by the storage defect address data DAVM1 is used.
Let it be 2.

The vertical address AVM represented by the storage defect address data DAVM1 thus obtained.
1 and the vertical address AVM2 represented by the storage defect address data DAVM2 are such that the level comparison data DD1 indicates a high level in a certain field period, and a defective portion included in the digital image pickup signal DI1 'is detected. , Vertical address AVM1
Properly represent a horizontal row of pixels to which a defective pixel in the imaging surface portion that causes the defective portion in the digital imaging signal DI1 ′ based on the defective portion included in the imaging signal IP1 belongs, and the vertical address AVM2 has the same defective pixel. In the digital imaging signal DI 2 ′ in the next field period that includes a defective portion due to the defective pixel, the pixel horizontal line to which the defective pixel on the imaging surface portion that causes the defective portion belongs is properly represented, and the level comparison is performed in a certain field period. When the data DD2 indicates a high level and a defective portion included in the digital image pickup signal DI2 'is detected, the vertical address AV
M2 appropriately represents a pixel horizontal row to which a defective pixel on the imaging surface portion that causes a defective portion in the digital imaging signal DI2 ′ belongs, and the vertical address AVM1 is
The horizontal row of pixels to which the defective pixel belongs on the imaging surface portion that causes the defective portion in the digital imaging signal DI1 ′ in the next field period that includes the defective portion due to the same defective pixel is appropriately represented.

Under the circumstances, in the period TDD, when the level comparison data DD1 from the level comparison section 67 or the level comparison data DD2 from the level comparison section 70 represents a high level, The storage defect address data DAVM1 from the storage address data forming unit 72 and the count data DAH from the H-address counter 74, which are supplied to the first memory area 63A at that time, are written to the first memory area 63A. The storage defect address data DAVM2 and H from the storage address data forming unit 72, which are supplied to the second memory area 63B at that time, are stored in the second memory area 63B of the memory unit 63.
-The count data DAH from the address counter 74 is written and stored. By doing this,
The first memory area 63A and the second memory area 63A in the memory unit 63
Of the digital imaging signal DI1 ′
Alternatively, when a defective portion in the digital image pickup signal DI2 'is detected, a vertical dress AV for accurately specifying a defective pixel on the image pickup surface portion that causes the defective portion.
And defective address data indicating the horizontal address AH.

As shown by the dashed line in FIG. 5, a level detector 75 for detecting the level of the digital image signal DI1 'and a level detector 76 for detecting the level of the digital image signal DI2' are provided. When the level comparison data DD1 from the level comparison unit 67 or the level comparison data DD2 from the level comparison unit 70 indicates a high level, the output signal DL1 of the level detection unit 75 further changes the digital imaging signal DI at that time.
1 '(the level of the defective portion of the digital image signal DI1') is equal to or higher than a predetermined value, or the output signal DL2 of the level detector 76 is the level (digital signal) of the digital image signal DI2 'at that time. The storage address data DAVM1 in the first memory area 63A and the second memory area 63B in the memory unit 63, on condition that the level of the defective portion of the imaging signal DI2 ′) is equal to or higher than a predetermined value. And the count data DAH, and the storage address data DAVM2 and the count data DAH may be stored. In such a case, there is no possibility that substantially unnecessary data will be stored in the memory unit 63.
The memory capacity of the memory unit 63 can be reduced.

When the period TDD elapses, the detection end signal generation unit 77 to which the memory write control signal CWC is supplied from the memory write control signal generation unit 62 supplies the memory write data as shown in FIG. A detection end signal CE formed according to the trailing edge of the control signal CWC is obtained, and the detection end signal CE is transmitted through the signal output terminal 78 and supplied to the control unit 41. Thereby, the control unit 4
1 is a defect detection command signal CS as shown in FIG.
The transmission of T is stopped at the leading edge of the detection end signal CE. Thereby, the defect detecting section 40 detects a defective portion in the digital imaging signal DI1 or the digital imaging signal DI2, and identifies a defective pixel in the imaging surface portion of the solid-state imaging section 11 which causes the detected defective portion. The operation of storing the data in the memory unit 63 is completed.
Return to

A defective portion in the digital image pickup signal DI1 or DI2 is detected, and defective address data for specifying a defective pixel in the image pickup surface portion of the solid-state image pickup portion 11 which causes the detected defective portion is stored in the memory portion 63. Defect detection unit 40 whose operation of storing in
In the following video signal output period TCO, the storage defect address data DAV stored in the first memory area 63A of the memory section 63 is stored in the first memory area 63A.
M1 and the count data DAH are read out, supplied to a vertical direction address comparison section (V-address comparison section) 81 and a horizontal direction address comparison section (H-address comparison section) 82 and latched, respectively. The storage defect address data DAVM2 and the count data DAH stored therein are read from the second memory area 63B in the section 63, and supplied to the V-address comparison section 83 and the H-address comparison section 84, respectively. Latched.

Each of the V-address comparison units 81 and 83 has the count data DAV from the V-address counter 73.
Is supplied. When the vertical address data AV represented by the count data DAV from the V-address counter 73 matches the vertical address AVM1 represented by the storage defect address data DAVM1 latched by the V-address comparison section 81, the V-address A comparison output signal CV1 having a high level is obtained from the comparison unit 81 and supplied to one input terminal of the AND gate 85. Similarly,
The vertical address data AV represented by the count data DAV from the V-address counter 73 is stored defective address data DAV latched by the V-address comparison unit 83.
When M2 matches the vertical address AVM2 represented, a comparison output signal CV2 having a high level is obtained from the V-address comparison unit 83 and supplied to one input terminal of the AND gate 86.

The count data DAH from the H-address counter 74 is supplied to each of the H-address comparison units 82 and 84. And the H-address counter 7
4 is the horizontal address data AH represented by the count data DAH represented by the count data DAH latched by the V-address comparison unit 82.
When it is coincident with, the comparison output signal CH1 having a high level is obtained from the H-address comparison unit 82 and supplied to the other input terminal of the AND gate 85. Similarly, when the horizontal address data AH represented by the count data DAH from the H-address counter 74 matches the horizontal address data AH represented by the count data DAH latched by the V-address comparator 84, the H-address comparison is performed. Part 84
, A high-level comparison output signal CH2 is obtained,
The signal is supplied to the other input terminal of the AND gate 86.

From the AND gate 85, the comparison output signal C
When both V1 and the comparison output signal CH1 are at a high level, a defect correction instruction signal CD1 is obtained, sent out through the output terminal 87 and supplied to the defect correction unit 32. Similarly, when both the comparison output signal CV2 and the comparison output signal CH2 take a high level from the AND gate 86, a defect correction instruction signal CD2 is obtained, which is sent out through the output terminal 88, and It is supplied to the defect correction unit 35.

In the above-described example, the defect detecting section 40 detects a defective portion in the digital imaging signal DI1 or DI2, and detects a defect in the imaging surface portion of the solid-state imaging section 11 which causes the detected defective portion. The defective address data for specifying the pixel is stored in the memory unit 6.
3 is performed in a state where the aperture mechanism 12 is in the full aperture state and the imaging surface of the solid-state imaging unit 11 is substantially in a state where external light does not enter. Detecting a defective pixel that causes an operation failure of storing and sending out a relatively large amount of electric charge even without receiving light, and correcting a defective portion of an imaging signal caused by the defective pixel are performed. However, the present invention is not limited to such an example.
Of the digital imaging signal DI1 or DI2, and stores defect address data for specifying a defective pixel in the imaging surface of the solid-state imaging unit 11 which is responsible for the detected defective part in the memory unit 63. The operation of the solid-state imaging unit 11 is performed in a state where the external light is substantially uniformly incident on the entire effective area of the solid-state imaging unit 11. Even in such a case, it may be possible to detect a defective pixel which does not accumulate an appropriate amount of charge and cause an operation failure, and correct a defective portion of an imaging signal due to the detection.

[0062]

From the above description, according to the present invention As is clear, according to the present invention
Imaging signal defect according to the first aspect detection and correction device and
The image signal defect detection and correction according to the second aspect of the present invention are performed.
In each of the video cameras, the first imaging signal formed based on the output signal from each of the pixels belonging to the odd-numbered pixel horizontal row in the imaging surface portion and the even-numbered pixel horizontal row in each field period. In the case where there is a defective pixel on the imaging surface portion of the solid-state imaging portion that obtains the second imaging signal formed based on the output signal from each of the pixels belonging to the first or second imaging device, Through detection of a defective portion caused by a defective pixel included in the imaging signal of No. 2, defect address data accurately representing the position of the defective pixel on the imaging surface portion is obtained, and the obtained defect address data is stored in the memory portion. The stored operation is appropriately performed under the condition that the solid-state imaging unit is put into a state where it is actually used. After the defect address data indicating the position of the defective pixel on the imaging surface portion is stored in the memory portion, a defective portion caused by the defective pixel included in the first or second imaging signal is stored in the memory portion. Correction is properly made under the timing setting based on the address data read from the.

Therefore, the image signal defect detection and correction apparatus according to the first aspect of the present invention, or the second aspect of the present invention.
According to the video camera that performs the image signal defect detection and correction according to the above, based on the first and second image signals obtained from the solid-state image pickup unit, detection of a defective pixel in an image pickup surface of the solid-state image pickup unit And its location can be determined easily and reliably as appropriate without any complicated and expensive test system, etc., and also including defective pixels generated after the solid-state imaging unit is put into actual use. Is performed, and the result is stored. After that, the correction of the defective portion of the first or second image pickup signal caused by the detected defective pixel is performed. With the timing set based on the result of specifying the position, the operation is properly performed.

[Brief description of the drawings]

FIG. 1 shows an example of an imaging signal defect detection and correction device according to the present invention, and an imaging signal defect detection according to the present invention including the same.
FIG. 2 is a block diagram illustrating an example of a video camera that performs correction and correction .

FIG. 2 is a schematic configuration diagram provided for describing an imaging surface section of the solid-state imaging section in the example shown in FIG. 1;

FIG. 3 is a time chart for explaining the operation of the solid-state imaging unit in the example shown in FIG. 1;

FIG. 4 is a time chart for explaining the operation of the solid-state imaging unit in the example shown in FIG. 1;

FIG. 5 is a block diagram showing a specific configuration example of a defect detection unit in the example shown in FIG. 1;

6 is a time chart used for describing an operation of a specific configuration example of the defect detection unit illustrated in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Lens system 11 Solid-state imaging part 12 Aperture mechanism 13 Semiconductor base 15 Photoelectric conversion element part 16 Vertical charge transfer part 17 Charge readout gate part 18 First horizontal charge transfer part 20 Second horizontal charge transfer part 21, 22 Charge output Unit 25 Drive signal forming unit 26 Timing signal generating unit 30, 33 Sampling and holding unit 31, 34 A / D converting unit 32, 35 Defect correcting unit 36 Signal processing unit 40 Defect detecting unit 41 Control unit 60 Storage command signal forming unit 62 Memory write control signal generating section 63 Memory section 64 Field discriminating section 67, 70 Level comparing section 71 Reference level generating section 72 Memory address data forming section 73 V-address counter 74 H-address counter 81, 83 V-address comparing section 82,84 H-address comparison unit 85,86 AND gate

Claims (4)

(57) [Claims] 1. A plurality of pixel horizontal columns and a plurality of pixel vertical columns are formed, a plurality of vertical charge transfer units along the pixel vertical columns, and a first and a second connected to the plurality of vertical charge transfer units.
The horizontal charge transfer portion, and has a first and an imaging surface having a second charge outputting section provided in the first and second horizontal charge transfer part, in the odd field period, the plurality The charge from each of the pixels belonging to the odd-numbered pixels in the pixel horizontal column is transferred to the plurality of vertical charge transfer units and the first water.
Led to the first charge output section through the flat charge transfer section.
Rutotomoni, vertical electric charge of the plurality of the respective pixels belonging to the even-numbered ones of the plurality of horizontal pixel line
Through the load transfer unit and the second horizontal charge transfer unit.
2 and output to the first and second charge output units, the odd-numbered ones in the plurality of pixel horizontal columns.
The first imaging signal based on the charge from each of the pixels belonging to
Signal and even-numbered ones in the horizontal rows of pixels.
The second imaging signal based on the charge from each of the pixels belonging to
Respectively, and within the even field period,
Of pixels belonging to even-numbered pixels in the horizontal row of pixels
The charge from each of the plurality of vertical charge transfer units and the first
To the first charge output unit through the horizontal charge transfer unit
And the odd number in the horizontal rows of pixels.
The charge from each of the pixels belonging to the eye
Through the direct charge transfer section and the second horizontal charge transfer section.
The second charge output unit outputs the first and second charge output units.
In the charge output section, the even-numbered
The first imaging based on the charge from each of the pixels belonging to
Odd number in the image signal and the plurality of pixel horizontal rows
Included in the first and second imaging signals with respect to the first and second imaging signals from the solid-state imaging unit from which the second imaging signals based on the charges from the pixels belonging to A defect correction unit that corrects a defective portion based on a defective pixel in the imaging surface unit; a signal defect detection unit that detects the defective portion included in the first and second imaging signals; Generating first address data representing each of the columns and second address data representing each of the pixels in each horizontal row of pixels in the imaging surface unit, and when the defective portion is detected by the signal defect detection unit,
The first address data is obtained as first defective address data for specifying a pixel horizontal row to which a defective pixel causing the defective portion belongs, and the second address data is specified by the first defective address data. An address data generating unit that obtains the second defective address data for specifying the position of the defective pixel in the horizontal pixel row to be processed; and a defective portion included in the first image signal based on the first defective address data. First storage defect address data for specifying a pixel horizontal row to which a defective pixel causing a problem belongs, and a first storage defect address data for specifying a pixel horizontal row to which a defective pixel causing a defect portion included in the second imaging signal belongs. 2
A storage address data forming unit that obtains the storage defect address data; and a storage address when the signal defect detection unit detects a defective portion included in the first imaging signal or the second imaging signal. Writing the first storage defect address data and the second defect address data from the data formation unit, and writing the second storage defect address data and the second defect address data from the storage address data formation unit; A memory unit to which the defect address data is written, and the defect correction unit based on the first storage defect address data and the second defect address data read from the memory unit. A signal for causing the first imaging signal to perform defect correction is transmitted, and the second storage defect address read from the memory unit is transmitted. A signal transmission unit for transmitting a signal for causing the defect correction unit to perform defect correction on the second imaging signal based on the scan data and the second defect address data. Defect detection and correction device. 2. A storage device according to claim 1, further comprising a field determining unit for determining whether the field period in which the first or second imaging signal including the defective portion is obtained is an odd field period or an even field period. The formation unit determines that the discrimination output from the field discrimination unit is in the odd field period.
If it indicates a delay, the signal defect detection unit
A defective portion included in the first image pickup signal is detected.
When the first defective address data is stored in the first storage
And defect address data for the first defect.
Indicates the address that is obtained by increasing the address data by "1"
To the second defective address data for storage.
In addition, the second imaging signal is output by the signal defect detection unit.
When the defective part included in the signal is detected, the first defect is detected.
For the first and second storages,
With each of the defective address data,
The discrimination output from the field discriminator indicates the even field period.
In the case where the signal defect is detected,
When a defective portion included in the first imaging signal is detected
The first defective address data is directly used in the first defect address data.
And the second storage defect address data, respectively.
In addition, the signal defect detector includes the second image signal in the second image signal.
When a defective portion is detected, the first defect address is detected.
Address indicating the address data reduced by "1"
To be the first storage defect address data.
And the first defective address data as it is.
2. The apparatus according to claim 1, wherein the second storage defect address data is used. 3. A signal defect detection unit, comprising:
And detecting the defective portion included in the second image pickup signal
External light does not substantially enter the imaging surface of the solid-state imaging unit.
The image signal defect detection and correction apparatus according to claim 1, wherein the detection is performed in a state where the image signal is defective. 4. A plurality of pixel horizontal columns and a plurality of pixel vertical columns are formed, a plurality of vertical charge transfer units along the pixel vertical columns, and a first and a second connected to the plurality of vertical charge transfer units.
The horizontal charge transfer portion, and has a first and an imaging surface having a second charge outputting section provided in the first and second horizontal charge transfer part, in the odd field period, the plurality The charge from each of the pixels belonging to the odd-numbered pixels in the pixel horizontal column is transferred to the plurality of vertical charge transfer units and the first water.
Led to the first charge output section through the flat charge transfer section.
Rutotomoni, vertical electric charge of the plurality of the respective pixels belonging to the even-numbered ones of the plurality of horizontal pixel line
Through the load transfer unit and the second horizontal charge transfer unit.
2 and output to the first and second charge output units, the odd-numbered ones in the plurality of pixel horizontal columns.
The first imaging signal based on the charge from each of the pixels belonging to
Signal and even-numbered ones in the horizontal rows of pixels.
The second imaging signal based on the charge from each of the pixels belonging to
Respectively, and within the even field period,
Of pixels belonging to even-numbered pixels in the horizontal row of pixels
The charge from each of the plurality of vertical charge transfer units and the first
To the first charge output unit through the horizontal charge transfer unit
And the odd number in the horizontal rows of pixels.
The charge from each of the pixels belonging to the eye
Through the direct charge transfer section and the second horizontal charge transfer section.
The second charge output unit outputs the first and second charge output units.
In the charge output section, the even-numbered
The first imaging based on the charge from each of the pixels belonging to
Odd number in the image signal and the plurality of pixel horizontal rows
And a solid-state imaging unit that obtains a second imaging signal based on the charge from each of the pixels belonging to the first and second imaging signals, respectively, for the first and second imaging signals from the solid-state imaging unit. A defect correction unit that corrects a defective portion based on a defective pixel in the imaging surface portion included in the imaging signal of No. 2; a signal defect detection unit that detects the defect portion included in the first and second imaging signals; Generating first address data representing each of the plurality of horizontal rows of pixels and second address data representing each of the pixels within each horizontal row of pixels on the imaging surface unit; and detecting the defective portion by the signal defect detection unit. When is detected,
The first address data is obtained as first defective address data for specifying a pixel horizontal row to which a defective pixel causing the defective portion belongs, and the second address data is specified by the first defective address data. An address data generating unit that obtains the second defective address data for specifying the position of the defective pixel in the horizontal pixel row to be processed; and a defective portion included in the first image signal based on the first defective address data. First storage defect address data for specifying a pixel horizontal row to which a defective pixel causing a problem belongs, and a first storage defect address data for specifying a pixel horizontal row to which a defective pixel causing a defect portion included in the second imaging signal belongs. 2
A storage address data forming unit that obtains the storage defect address data; and a storage address when the signal defect detection unit detects a defective portion included in the first imaging signal or the second imaging signal. Writing the first storage defect address data and the second defect address data from the data formation unit, and writing the second storage defect address data and the second defect address data from the storage address data formation unit; A memory unit to which the defect address data is written, and the defect correction unit based on the first storage defect address data and the second defect address data read from the memory unit. A signal for causing the first imaging signal to perform defect correction is transmitted, and the second storage defect address read from the memory unit is transmitted. A signal transmission unit for transmitting a signal for causing the defect correction unit to perform a defect correction on the second imaging signal based on the scan data and the second defect address data. A video camera that performs correction.