JP3330992B2 - Transmission method of incremental signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for transmitting an incremental signal.

[0002]

2. Description of the Related Art Conventionally, in a motor such as a brushless motor, position data of a motor main shaft has been detected. This data is detected by A, B
This is performed by providing a magnetic recording medium for phase detection and obtaining a position data signal from the magnetic recording medium. These data are transmitted to the control device via cables that bundle the transmission paths, and various processes such as feedback control are performed based on the data. However, in the above-described device, since signals of two channels of A-phase and B-phase are transmitted, the number of transmission lines is large, and the cable for bundling them has to be thickened, resulting in high cost. Therefore, an apparatus for solving the above problem has been proposed in Japanese Patent Application Laid-Open No. 2-140617.
In this device, the A-phase and B-phase signals are converted into counter values by an up / down counter, transmitted on one transmission path, and the position is determined from the counter values to simplify the device. .

[0003]

However, when an up-down counter is used as in the above-described apparatus or when two-phase A-phase and B-phase signals are transmitted, there are the following problems. That is, since the counter value of the up / down counter is transmitted as it is, there is a problem that the signal amount is large, the transmission time is lengthened, the control performance is deteriorated, and the storage capacity must be increased. When the AB phase is transmitted over a long distance using a cable, a low-pass filter is inserted on the receiving side for noise suppression. Therefore, the duty of the AB phase is set to 50% ± 10%.
Otherwise, the signal will not be transmitted correctly. Therefore,
There is a problem that the accuracy of the output of the analog sensor of the AB phase is strictly required to keep the AB phase within the tolerance of the duty. Further, noise may be included in the incremental signals A and B. In such a case, the counter value is indicated by a dotted line with respect to the actual counter value indicated by a solid line as shown in FIG. Since such an error occurs and the indexing position is incorrect, there is also a problem that reliability is reduced.

Accordingly, it is a first object of the present invention to provide a method for transmitting an incremental signal which can reduce the amount of signal, reduce the storage capacity, and improve the control performance by shortening the transmission time. Further, in addition to the first object, a second object is to provide a method of transmitting an incremental signal which can improve the duty of the AB-phase output even if the accuracy of the output of the AB-phase analog sensor is poor and can improve the quality. . Further, in addition to the first object, a third object is to provide a method of transmitting an incremental signal which can detect a transmission error and improve reliability. In addition, in the case of use on a poor quality transmission line where frequent transmission errors occur,
The reliability of the data allows a conventional level of error. Single errors due to noise do not generate an alarm, the previously received data is used as is to avoid malfunction, and multiple consecutive true errors generate an alarm. I did it,
A fourth object of the present invention is to provide a method for transmitting an incremental signal that can improve noise resistance.

[0005]

According to a first aspect of the invention, there is provided a method for transmitting an incremental signal, comprising the steps of: inputting an incremental signal to a counter;
Considering the counting direction, the amount of change in the counter value over a certain period of time (n + 1) bits (n is a natural number) is converted into a serial signal and transferred, and the signal including this serial signal is transferred.
A signal transmission method for converting the signal into an incremental signal on the receiving side of the serial signal.
Clock pulse generated from basic clock is divided by frequency divider
Density and number of pulses ^[(natural number n) 2 n -1] obtained by
Divided into n types of pulse trains, and the above n types of pulses
Out of the column by adding selected Pal <br/> scan string corresponding to the serial signal thus received is characterized in that so as to reproduce the incremental signal.

[0006]

A method for transmitting an incremental signal according to a second aspect of the present invention, in addition to the first means, achieves the third object by dividing a serial signal into frame units for each sampling data. It is characterized by detecting an error.

According to a third or fourth aspect of the present invention, in order to achieve the fourth object, in addition to the second means, the serial signal is divided into frame units for each sampling data, and detecting an error in each frame, when an error occurs, repeatedly used data of the previous frame, or when an error occurs repeatedly setting times is characterized in that to determine the abnormality.

[0009]

SUMMARY OF According to the transmission method of the incremental signals in such a first unit, and transmits the amount of change in the counter value at a certain time of the counter, together with the transmission time with the signal amount becomes small is shortened, the counter value When
And [2 ⁿ -1 (n is a natural number)] pulses
Select a pulse according to the counter value received from
Regenerates the incremental signal, so the pulse density is relatively uniform
Etc., the AB phase that does not disappear with the low-pass filter on the receiving side
Of the analog sensor output of AB phase so that the duty becomes
The conventional problem of improving accuracy is eliminated.

[0010]

According to the method for transmitting an incremental signal in the second means, an error detection function is added, so that data reliability is remarkably improved.

According to the method of transmitting an incremental signal in the third or fourth means, if an error does not occur repeatedly for a set number of times, the error is determined to be an error due to noise and the data of the previous block is repeatedly reproduced. Erroneous operation is avoided. On the other hand, if the error occurs repeatedly for a set number of times, this error is determined to be a true error.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic perspective view of a signal transmission device to which a method for transmitting an incremental signal according to a first embodiment of the present invention is applied. In FIG. 1, reference numeral 1 denotes, for example, a brushless motor, and an end surface of a main shaft 1 a of the motor 1 has
A disk-shaped magnet 2 for detecting magnetic poles is provided. The magnetic pole detection magnet 2 has N and S poles alternately magnetized in the circumferential direction, and transmits U, V, and W phase drive position data. This magnetic pole detection magnet 2
Is provided with a disk-shaped magnetic recording medium 3. This magnetic recording medium 3 has an N pole and an S pole
It has an upper portion which is magnetized side by side and a lower portion in which N and S poles are alternately magnetized on the circumference in the same phase as the upper portion. It transmits the B-phase position data.

The motor 1 has the above-mentioned A, B, Z, U, V,
A position detector 4 such as an encoder for detecting the W-phase position data is provided. In the case 44 of the encoder 4 (indicated by a dotted line to avoid complicating the figure), the magnetic pole detecting magnet 2 and the magnetic pole detecting section The hall element 4a and the MR sensor 4b are arranged, and the hall element 4a includes a waveform shaping circuit 4c, a multiplying + direction detection circuit 40, an up / down counter 5, a parallel / serial converter 6, a communication control Part 5
0, CRC bit adder 51, line driver 8, 5V
It is attached to the back of the base of a signal processing circuit 17 composed of a power supply 18 and a ground power supply 19. The output lines of the Hall element 4a and the MR sensor 4b are connected to a waveform shaping circuit 4c for shaping the waveform into a rectangular wave as shown in FIG. The output lines of the A and B phases of the waveform shaping circuit 4c are connected to a quadruple pulse + direction detecting circuit 40 for converting the pulse into a quadruple pulse and an up / down signal, respectively. The output line of the circuit 40 and the output line of the communication control unit 50 for sending clear and sampling instruction signals are connected to a 6-bit up / down counter 5 that counts up or down in accordance with the advance or delay of the AB phase. Have been. The output line of the up / down counter 5 is connected to the parallel / serial converter 6, and the output lines of the other phases (Z, U, V, W phases) are directly connected to the parallel / serial converter 6, respectively. Have been. The output line of the CRC bit adder 51 for error detection is also connected to the parallel / serial converter 6. The serial signal line 7 from the serial converter 6
It is connected to a line driver 8.

The BUS line 10 and the inverted BUS line 11 of the line driver 8 are connected to the control device 1 as shown in FIG.
6 are connected to line receivers 14 respectively.
The signal processing circuit 17 and the control device 16 have a 5V power supply 1
8 and 41, and ground power supplies 19 and 42 are provided, respectively. These 5V power supplies 18 and 41 are connected to each other, and the ground power supplies 19 and 42 are connected to each other.
3 are connected to each other. These 5V power lines 1
2. The ground power supply line 13 is bundled together with the BUS line 10 and the inverted BUS line 11 in the encoder cable 9. The encoder cable 9 is appropriately supported by a support member (not shown).

The output line of the line receiver 14 in the control device 16 is connected to a serial / parallel converter 15 via a serial signal line 30, and the serial / parallel converter 15 outputs the Z, U, V, The W-phase position data, counter value, and CRC bit for error detection can be output in parallel. The output line of the counter value of the serial / parallel converter 15 determines whether the value is a positive value or a negative value. If the value is a negative value, the absolute value circuit 45 changes the value to a positive value. All output lines for the V and W phase position data, counter values, and CRC bits are connected to an error detector 48 for performing error detection. The output line for instructing hold of the error detector 48 is an absolute value circuit. 45 and a latch 49. The output of the error detector 48 is output to the outside as an error alarm once, and is also connected to a continuous detection circuit three times. The output of the three consecutive detection circuit is output to the outside as a three consecutive error alarm. If the quality of the transmission line is good, the one-time error alarm output is connected to a motor power supply stop circuit (not shown). Conversely, if the quality of the transmission line is not good, the alarm is connected to a three-time continuous alarm or a motor energization stop circuit. The output line of the reset signal corresponding to the serial signal of one frame of the serial / parallel converter 15 is connected to a 1/12 frequency divider 43 which receives a 10 MHz basic clock and generates 2 ⁿ -1 pulses. The output line of the 1/12 frequency divider 43 is connected to a 1 / ²ⁿ frequency divider 44 that generates five types of pulse trains having different densities. The output line of the 1/2 ⁿ divider 44 and the output line of the absolute value circuit 45 are connected to a pulse generator 46 for selecting a pulse according to the absolute value.
The output line of the pulse generator 46, the value of the counter value b ₅ (to be described later in detail) performs switching of the up-down according to, A-phase, A reproduced rectangular wave of phase B, connected to the B-phase generating circuit 47 Have been. The control device 16 and the motor 1 are connected by a motor cable 31 as shown in FIG. 1 so that the control device 16 can drive the motor 1.

Next, the operation of the signal transmission device will be described.
This will be briefly described below. When drive power is supplied from the control device 16 to the motor 1 via the motor cable 31 to operate the motor 1, the main shaft 1a starts rotating, and the magnetic field is changed by the magnetic pole detecting magnet 2 and the magnetic recording medium 3. . This change in the magnetic field is caused by U,
It is detected as V and W phase drive position data. In the MR sensor 4b, the position data is detected as Z, A, and B phase position data, and the A and B phases are detected as sine waves. These data signals Vu, Vv, Vw,
Vz, Va, and Vb (see FIG. 2) are input to the waveform shaping circuit 4c and shaped into a rectangular wave. FIGS. 5B and 5C show the A and B phase signals whose waveforms have been shaped by the waveform shaping circuit 4c. These signals (incremental signals) A and B shaped into rectangular waves are converted into four-multiple pulses and up-down signals in a four-multiple pulse + direction detection circuit 40, and these four-multiple pulses and up-down signals are converted into six. The bit is input to the up / down counter 5 and the up / down counter 5 counts up or down.

FIG. 7 shows an example of the operation of the quadruple pulse + direction detection circuit 40 and the up / down counter 5. As shown in the figure, the quadrupled pulse (a) is generated according to the edge of the signals A and B (the switching portion of the signal), and the up-down signal (b) is determined according to the advance and delay of the phase of the signals A and B. , When the B phase is advanced, the up is instructed, and when the A phase is advanced, the down is instructed. ) And the up-down signal (b), a step-like counting is performed.

In this embodiment, the up / down counter 5 samples the counter value at regular intervals according to the sampling signal shown in FIG. 5 (e) from the communication control unit 50. When the sampled counter value is loaded into the parallel-to-serial converter 6, the communication controller 50 outputs the counter value shown in FIG.
The counter value is cleared according to the clear signal shown in FIG. Here, in the present embodiment, since the phase of the signals A and B advances in the B phase at all times,
The counter value of the up / down counter 5 is as shown in FIG.
It becomes as shown in.

These counter values are input to the parallel-to-serial converter 6 as 6-bit signals b _{0 to} b _5. On the other hand, the position data signals U, V, W and Z shaped into rectangular waves are The signals are directly input to the parallel / serial converter 6. Note that b ₅ counter value M
SB and b ₀ are LSBs, and are set such that b ₅ = 0 when the phase of the B phase is advanced, and b ₅ = 1 when the phase of the A phase is advanced. The numbers enclosed by circles in FIGS. 5B and 5C correspond to those in FIG. 5D. That is, (b),
(C) shows that the change point of the AB phase corresponds to the change of the counter value. The numbers not enclosed by circles in (d) indicate counter values.

Here, the up / down counter 5 is set to 6
The reason why the bit is set will be described. The transmission speed of the serial signal output from the parallel / serial converter 6 is, for example, 5
00 kbps and the format of the serial signal
Assuming (a), one frame is sampled by 38
μs. The AB phase is output at 2048 pulses per revolution of the spindle 1a, and the spindle is up to 5000 rpm
Assuming that the rotation is performed as follows, the frequency of the 4 × pulse is 5000 rpmｒ60 seconds × 2048 pulses × 4 × =
682.7 kHz. Since the sampling period is 38 μs as described above, a pulse of 682.7 kHz × 38 μs = 25.9 pulses / period is inserted during this period. Here, 25.9 <31 =
Since the value is 2 ⁵ -1, 6 bits are sufficient for the counter value of the up / down counter 5 in consideration of the counting direction.

The 6-bit counter value and position data signals U, V, W, and Z are converted into serial signals by a parallel-to-serial converter 6, and the parallel-to-serial converter 6 outputs the signals shown in FIG. A serial signal in the format shown is transmitted.

In this format, the transmission speed is 500 kbps as described above, and 38 μm per frame.
s. Reference numeral 20 denotes a rest space before transmission of various data, 21 denotes a start bit following the space 20 to notify the start of transmission, 22 denotes a start bit 21, 6 bits of a counter value transmitted from the up / down counter 5 following the start bit 21, and 23 Inspects a U, V, W, Z position data signal transmitted from the waveform shaping circuit 4c following the counter value 22, and 24 inspects a series of data following the U, V, W, Z position data signal 23 ( Each of the four CRC bits (for performing an error check) is shown. Here, this CRC bit 24 is a CRC for error detection.
The data is added to the data signal by a signal from the bit adder 51, and a rest space 20, start bit 21, counter value 22, position data signal 23, CR
One frame is constituted by the C bit 24. As the code, for example, a Manchester code is used.

The serial signal of one frame is obtained in accordance with detection signals from the Hall element 4a and the MR sensor 4b.
Repeating the line driver 8 while updating the transmission data,
The data is transmitted to the control device 16 via the encoder cable 9. As described above, this signal is a signal sampled at regular intervals in accordance with the sampling signal and the clear signal from the communication control unit 50. Therefore, the signal amount is significantly reduced as compared with the related art, and thus the storage capacity is reduced. The transmission time can be shortened as well as being reduced.

The serial signal is received by the line receiver 14 in the control device 16 via the encoder cable 9. This serial signal is converted into a parallel signal by the serial / parallel converter 15, and data is generated at the time when the CRC bit 24 is confirmed, that is, at the timing shown in FIG.

The U-, V-, W-, and Z-phase position data U ', V', W ', and Z', which have been converted in parallel, are sent to subsequent processing as they are, while the 6-bit counter value is stored in an absolute value circuit 45.
Is input, in the absolute value circuit 45, either a positive value or a negative value is determined based on the value of b _5. Here, b ₅ = 0
Is determined as a positive value when b ₅ = 1, and as a negative value when b ₅ = 1, and 100,000 when b ₅ = 1.
_{(2) -b 4 b 3 b} 2 b 1 b 0 Get to the (2) outputs. This output is 5 bits and b ₄ 'b ₃ ' b ₂ '
It is encoded as b ₁ 'b ₀ '. The number in parentheses indicates a base number, and (2) indicates a binary number.

Next, the 1/12 frequency divider 43 will be described. According to the above calculation of the required number of bits of the counter, it is sufficient that the pulse generator 46 at the subsequent stage generates up to 26 pulses in 38 μs, but in the present embodiment, A,
In order to reduce the jitter of the B-phase signal, a clock capable of generating 31 pulses in 38 μs is required (details will be described later). That is, a clock of 31 pulses / 38 μs = 815.8 kHz is required. This sets the basic clock to 10M
Assuming that the frequency is Hz, 10 MHz / 815.8 kHz = 12.3 frequency division may be performed. Therefore, in this embodiment, the 1/12 frequency divider 43 is used.

However, since the output of the 1/12 frequency divider 43, ie, 31 pulses of the 10/12 MHz clock, does not coincide with 38 μs, the reset signal corresponding to the serial signal of one frame is output from the serial / parallel converter 15. Is received and bookkeeping is performed.
This reset signal is shown in FIG. 6 (h), and 31/10 of the 10/12 MHz clock shown in FIG. 6 (i).
After the generation of the pulse, the 1/12 frequency divider 43 is reset and stopped, and the reset of the 1/12 frequency divider 43 is released at the data determination timing shown in FIG. Therefore, one pulse is generated every 1.2 μs, and the interval between the 31st pulse and the next 1st pulse is 2.0
μs.

The divided signal of 31 pulses is input to the 1/2 ⁿ frequency divider 44, in this 1/2 ⁿ frequency divider 44 5
It is divided into different types of pulse trains of different densities. This 1/2
Regarding the concept of the ⁿ frequency divider 44 and the pulse generator 46 described later, see “Digital Circuit—Basic and Application—” (Showa 57
Published on October 15, 2003, author: Hiroshi Kawahara, publisher: Shokodo Co., Ltd.), from page 154 to page 157. According to the pulse distribution principle of the MIT method,
The / 12 MHz clock is distributed to the clocks shown in FIGS. CLK16 is an odd-numbered pulse, CLK8 is a pulse that is divided by 4 and the remainder is 2,
4 has a pulse with a remainder of 4 divided by 8, CLK2 has a pulse with a remainder of 8 divided by 16, and CLK1 has a pulse with a remainder of 16 divided by 32. These CLK
16, CLK8, CLK4, CLK2, CLK1 and the output signal b ₄ 'b _3' from the absolute value circuit 45 b ₂ 'b
₁ 'b ₀ ' is input to the pulse generator 46, respectively.

The pulse generator 46 is a pulse generator 46 shown in FIG.
It comprises an ND circuit 46a and an OR circuit 46b.
CLK in accordance with the signal _{b 4 'b 3' b 2} 'b 1' b 0 '
16, CLK8, CLK4, CLK2, and CLK1 are selected, and a logical sum is output. Therefore, b
₄ 'b _3' if _{b 2 'b 1' b 0} ' is 01101 (2) as shown in the middle of the (o) in FIG. 6, CLK
8, CLK4, CLK1 are selected, ie, 10/1
2,4,6,10,12,14,1 of 2MHz clock
The sixth, 18, 20, 22, 26, 28, and 30th pulses are selected and added, and the pulse shown in FIG. 6 (p) is output. As is clear from FIG. 6 (p), the pulses are almost uniform, and the jitter is reduced. Accordingly, the output A'B 'of the AB phase generation circuit 47 described later also has less jitter.

The pulse train shown in FIG.
The AB-phase generation circuit 47
In, the reproduction of the incremental signals A ′ and B ′ is performed. The AB phase generation circuit 47 switches the output from the pulse generator 46 to an up or down input in accordance with the value of the transmitted 6-bit counter value b ₅ , where b ₅ = When it is 0, it goes up and b ₅ =
It is set to switch to down at 1. The A and B two-phase rectangular waves are such that adding one pulse to the output from the pulse generator 46 advances the phase of the B phase.
The phase of the B phase is advanced at the time of an up input, and the A phase is advanced at the time of a down input. The output signals from the AB phase generation circuit 47 are shown in (q) and (r) of FIG. 6, and it can be seen from this figure that the phase of the B phase is advanced.
Note that the edge codes in (b) and (c) of FIG.
.. Correspond to the edge codes in (q) and (r) of FIG. 6, and a time lag occurs. This is due to a delay in serial transmission or waiting for data confirmation. The time difference is 64 μs, and A, B
The transmission delay of the phase is a level that does not cause any particular problem. Moreover, if the transmission speed is increased from 500 kbps to 1 Mbps, the transmission delay can be further reduced.

Incidentally, in the error detector 48,
An error can be detected from the transmitted CRC bit 24. If an error is detected, an error alarm is output once and an absolute value circuit 45 is output.
And a hold signal is sent to the latch 49, and to use the data b ₅ ~b blocks received before one _0, U, V, W, and Z again. Data b ₅ ~b ₀ does not become a problem at all as the rotation so equivalent to rotating constant velocity be used again motor, not data U, V, W, a problem since the frequency is low with respect to Z . If an error has occurred three times in a row, a three-time consecutive error alarm is output from the three-times consecutive detection circuit. In addition, in the related art, if noise is included in the incremental signals A and B and the pulse disappears, the counter value becomes as shown by a dotted line in FIG. 8 and an error occurs, and the positioning position is shifted. However, in the present embodiment, as described above, if an error occurs, an error alarm is generated once, so that the motor can be stopped here and the user can be informed. Reliability can be improved. Also, ignoring the one-time error alarm, stop the motor with three consecutive error alarms,
If the user is informed, the data b _{5 to} b ₀ of the block received one time before is used.
Frequent motor stop and malfunction due to noise are prevented. However, if an error occurs three times in a row, it is determined that the error is a true error such as a decrease in the quality level of the communication path, and a continuous error alarm is generated and notified three times. In FIG. 3, the signals to be reproduced are denoted by 'such as A', B ', U', V ', W', Z '.
U, V, W, and Z are given a meaning to distinguish them because there is a transmission delay.

As described above, in the present embodiment, the up / down counter 5 is reset at regular intervals, and the data of the up / down counter 5 is sampled within this constant time. Therefore, the storage capacity can be reduced and the transmission time can be shortened.

The counter value is transmitted and [2 ⁿ -1]
(N is a natural number)] Since a pulse corresponding to the received serial signal is selected from the pulse trains and is reproduced as an incremental signal, the pulse density becomes relatively uniform, and the AB which cannot be eliminated by the low-pass filter on the receiving side. There is no need to increase the accuracy of the AB-phase analog sensor output so that the phase duty is obtained.

In addition, since the error is detected for each frame as compared with the conventional method of transmitting two AB-phase channels without detecting any error, the reliability of transmission data is improved. If the error does not occur repeatedly for the set number of times, this error is regarded as an error due to noise, and the data of the previous block is repeatedly reproduced. On the other hand, if the error occurs repeatedly for the set number of times, this error is Since it is determined that the error is a true error, a malfunction is avoided.

Further, in the present embodiment, the following effects can be exerted. That is, the MR sensor 4
b, the two-phase sine waves of phases A and B are input to an up / down counter 5 to obtain a counter value, and the counter value and position data of other phases (U, V, W, Z phases) are obtained. The signal is converted into a serial signal by the serial / parallel converter 6 and transmitted to the control device 16, so that the number of transmission paths can be reduced to one channel and the thickness of the cable can be reduced, thereby reducing the cost. Can be planned.

When a part of the encoder cable 9 is wired, for example, in the arm of a robot, the thickness of the encoder cable 9 can be reduced as described above. The portion occupied by the robot 9 can be used effectively for other purposes, the arm itself can be made thinner, and the outside of the robot body is less subject to restrictions such as swinging of the cable 9 than before, and furthermore, inside and outside the robot. In either case, the support member for supporting the cable 9 can have a relatively simple structure, so that the degree of freedom in design can be improved.

FIG. 9 is a block diagram of a main part of a signal transmission apparatus to which an incremental signal transmission method according to a second embodiment of the present invention is applied, in which only necessary parts are shown. The second embodiment is different from the first embodiment in that the input signal to the up / down counter 5 is changed to a feed pulse C and its up / down signal D instead of the quadruple pulse and its up / down signal. The point is that the reproduction of these signals C and D is performed by the CD signal reproducer 52. Here, the feed pulse C and its up / down signal D are, for example, as shown in FIGS.
Therefore, the up / down counter value is as shown in FIG. It is needless to say that the same effect as in the first embodiment can be obtained even with this configuration.

FIG. 11 is a block diagram of a main part of a signal transmission apparatus to which an incremental signal transmission method according to a third embodiment of the present invention is applied, in which only necessary parts are shown. The third embodiment is different from the first embodiment in that the input signal to the up / down counter 5 is changed to an up pulse E and a down pulse F instead of the quadruple pulse and its up / down signal. EF signal regenerator 5 reproduces E and F
3 is performed. Here, the up pulse E and the down pulse F are, for example, as shown in FIG.
(B), and the up / down counter value is as shown in (c) of FIG.
It is needless to say that the same effect as in the first embodiment can be obtained even with this configuration.

FIG. 13 is a block diagram of a main part of a signal transmission apparatus to which an incremental signal transmission method according to a fourth embodiment of the present invention is applied, in which only necessary parts are shown. The fourth embodiment is different from the first embodiment in that two AB phase signals are input to two up / down counters 5 and the two counter values are converted into serial signals by a parallel-serial converter. By returning the two counter values to the serial-parallel converter 15, the two AB-phase regenerators (the portions described as AB-phase regeneration in FIG. 6) reproduce the two sets of AB phases. is there. XY 2 for mouse and trackball
From a device that generates incremental signals in one direction,
This is effective when transmitting to the above-described control device with a reduced number of cables. Of course, application to three or more sets of AB phase signals is not excluded. As an application to encoders for two axes, in addition to two counter values,
Two sets of Z, U, V, and W phases may be input to the parallel-serial converter.

FIG. 14 is a block diagram of a main part of a signal transmission apparatus to which an incremental signal transmission method according to a fifth embodiment of the present invention is applied, in which only necessary parts are shown. The fifth embodiment is different from the fourth embodiment in that two sets of input signals are E signals in FIG. 12A and two counters are counters for only up-counting. Also in this embodiment, since two inputs are converted into one serial signal and transmitted as two outputs, the cable can be saved.

FIG. 15 is a block diagram of a main part of a signal transmission apparatus to which a method for transmitting an incremental signal according to a sixth embodiment of the present invention is applied, showing only the transmission side. This sixth
This embodiment is mainly different from the first embodiment in the configuration of the up / down counter 5. This counter is, for example, an 8-bit free running counter,
When counting up from 0 (2), 1111
If you count up further at 1111 (2), it will be 000
It is configured to return to 00000 (2). Also, it is not cleared every fixed period. Instead, the current counter value register is connected to the subsequent stage, and the previous counter value register is connected to the subsequent stage. The output of the current counter output register is connected to the positive input of the subtractor, and the output of the previous counter value register is connected to the negative input of the subtractor. Have been. The output of the subtractor is connected to the parallel-serial converter 6. This operation will be described with reference to the timing chart of FIG. FIGS. 16A and 16B show AB-phase input signals,
The waveforms are exactly the same as (b) and (c). Since the up / down counter 5 is not cleared, the counter value in FIG. 16C is steadily increasing. At the same timing as in FIG. 5E, the communication control unit 50
(D)) occurs, and the counter value is shifted from the current counter value register to the previous counter value register at the same timing. The subtracter subtracts the value of the previous counter value register from the value of the current counter value register, and outputs the result to the parallel-serial converter. From the sampling of these counter values, the relationship of the subtractor output is shown in FIG.
(D), (e), (f), and (g) show. In the present embodiment, instead of clearing the up / down counter 5, two registers are provided to store the current and previous values and to output the difference between them. As a result, the same effect as in the first embodiment can be expected.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, for example, in the above embodiment, the encoder 4 is
, But may be separated. Further, the encoder 4 may be a linear encoder. Further, the transmission path can be constituted by an optical fiber.

In the above embodiment, U, V,
Although an example is described in which the W and Z phase signals are superimposed on the serial signal and transmitted, the present invention may simply transmit and reproduce the A and B two phase signals by the above method. Further, in the above-described embodiment, the error detection is described based on only the CRC bit. However, for example, a check whether the start bit is 1 or a check whether the counter value is equal to or less than the allowable rotation speed may be added. .

It should be noted that the present invention is applicable to all methods for counting up and down of an incremental signal, and transmitting and reproducing the signal.

[0046]

As described above, according to the method for transmitting an incremental signal according to the first aspect of the invention, the amount of change in the counter value within a certain time of the up / down counter is sampled, so that the signal amount is reduced. The storage capacity can be reduced, and the transmission time is shortened, so that the control performance can be improved. In addition, since a pulse corresponding to the received serial signal is selected from the [2 ⁿ -1 (n is a natural number)] pulse train and reproduced as an incremental signal, even if the accuracy of the output of the AB-phase analog sensor is poor, , AB
The duty of the phase output can be improved, and therefore the quality can be improved. According to the incremental signal transmission method of the second invention, in addition to the first invention, the serial signal is divided into frames for each sampling data, and an error is detected for each frame . According to the incremental signal transmission method of the fourth invention, in addition to the second invention, when an error occurs, the data of the previous frame is repeatedly used, and when the error repeatedly occurs a set number of times, Since it is determined that an error has occurred, malfunctions can be avoided and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a signal transmission apparatus to which a method for transmitting an incremental signal according to a first embodiment of the present invention is applied.

FIG. 2 is a configuration diagram inside an encoder.

FIG. 3 is a configuration diagram in a control device.

FIG. 4 is a configuration diagram of a pulse generator.

FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. 2;

FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 3;

FIG. 7 is a timing chart for explaining an example of the operation of the 4 × + direction detection circuit and the up / down counter.

FIG. 8 is a diagram for explaining an error in a counter value when an error occurs due to noise.

FIG. 9 is a main part configuration diagram of a signal transmission apparatus to which a method for transmitting an incremental signal according to a second embodiment of the present invention is applied.

FIG. 10 is a timing chart for explaining an example of the operation of the up / down counter in FIG. 9;

FIG. 11 is a main part configuration diagram of a signal transmission device to which an incremental signal transmission method according to a third embodiment of the present invention is applied.

FIG. 12 is a timing chart for explaining an example of the operation of the up / down counter in FIG. 11;

FIG. 13 is a main part configuration diagram of a signal transmission device to which an incremental signal transmission method according to a fourth embodiment of the present invention is applied.

FIG. 14 is a main part configuration diagram of a signal transmission device to which an incremental signal transmission method according to a fifth embodiment of the present invention is applied.

FIG. 15 is a main part configuration diagram of a signal transmission apparatus to which an incremental signal transmission method according to a sixth embodiment of the present invention is applied.

FIG. 16 is a timing chart illustrating the operation of the circuit shown in FIG. 15;

[Explanation of symbols]

 5 Up / down counter A, B Incremental signal

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G08C 13/00-25/04 G01D 5/245 102

Claims (4)

(57) [Claims] 1. An incremental signal is input to a counter, and a change amount of a counter value in (n + 1) bits (n is a natural number) in a predetermined time is converted into a serial signal and transferred in consideration of a counting direction. Including signal
The receiving side of the signal A transmission method for converting an incremental signal, the receiving side of the serial signal, from the base clock
The resulting clock pulse is divided by a divider to obtain [2 ⁿ −
1 (n is a natural number)] pulses of n types with different densities
A method of transmitting an incremental signal, characterized in that the signal is divided into pulse trains, and a pulse train corresponding to the received serial signal is selected from among the n types of pulse trains and added, thereby reproducing an incremental signal. . 2. The incremental signal transmission method according to claim 1, wherein the serial signal is divided into frames for each sampling data and error detection is performed for each frame. 3. A performs error detection a serial signal for each divided into frames frames per sampling data, claims, characterized in that repeated use of data of the previous frame if an error occurred 2. The method for transmitting an incremental signal according to item 2. (4) Serial signal for each sampling data
Performs error detection for each frame by dividing into frames.
I If an error occurs repeatedly for the set number of times, it is determined to be abnormal
3. An incremental according to claim 2, wherein
Signal transmission method.