JP3331682B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit suitable for performing arithmetic or logical shift operations on a plurality of types of shift numbers.

[0002]

2. Description of the Related Art In recent years, more advanced techniques have been introduced into digital signal processing, and there has been a demand for an arithmetic unit to perform processing at a higher speed. Some of such processes include many logical shift and arithmetic shift operations, and the number of shifts is often given as a variable.

Hereinafter, an example of a conventional arithmetic unit will be described with reference to the drawings. FIG. 2 is a block diagram showing a conventional arithmetic unit.

In FIG. 2, reference numeral 101 denotes a bus to which input data is supplied, 102 denotes a barrel shifter for arithmetically or logically shifting data on the input data bus 101, 103 denotes a shift number register for holding a shift number, and 104 denotes an ALU.
(Arithmetic logic operation circuit) 105 is an output data bus. The shift number is provided from the output data bus 105 to the shift number register 103.

The shift operation of the above configuration will be described below. First, the number of shifts for shifting the input data is changed from the input data bus 101 to the ALU 104.
Is output to the output data bus 105, and then the shift number is output from the output data bus 105 to the shift number register 10.
3 is stored. Next, input data shifted from the input data bus 101 is input to the barrel shifter 102,
Arithmetic or logical shift operation is performed by the barrel shifter 102 based on the value stored in the shift number register 103, and the shift result is output to the ALU 104.

[0006]

However, in the above-mentioned conventional arithmetic unit, there is only one or two shift number registers 103 for holding the shift numbers. Must be stored in the shift number register 103 every time. Therefore,
In multivariable arithmetic, when shifting with a different shift number for each variable, it is necessary to store the shift number in the shift number register 103 for each shift.
There has been a problem that the operation speed is reduced and programming is complicated.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problem. In an arithmetic or logical shift operation for a plurality of types of shift numbers, a shift operation can be performed at a high speed and a program can be simplified. It is an object of the present invention to provide an arithmetic device capable of performing the following.

[0008]

The technical means of the present invention for achieving the above object comprises a bus to which input data is given, a barrel shifter for arithmetically or logically shifting data on the bus, and a shift number. Memory, a shift number bus for giving a shift number from the memory to the barrel shifter, and a plurality of pointers indicating addresses of the memory to be transmitted to the shift number bus.

[0009]

Therefore, according to the present invention, the barrel shifter arithmetically or logically shifts the input data by the shift number of the contents of the address indicated by the shift number memory pointer, so that there are a plurality of variable shift numbers, When shifting data using each of them, it is not necessary to set the number of shifts given to the barrel shifter for each shift operation.

[0010]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an arithmetic unit according to an embodiment of the present invention. In FIG. 1, 1 is a bus to which input data is supplied, 2 is a barrel shifter for arithmetically or logically shifting data on the input data bus 1, 3 is a memory for holding a shift number, 4 is a shift from a shift number memory 3 to a barrel shifter Reference numeral 5 denotes a shift number bus for giving a number, 5 denotes a plurality of pointers indicating addresses of the shift number memory 3 to be transmitted to the shift number bus 4, 6 denotes an ALU, and 7 denotes an output data bus.

The shift operation of the above configuration will be described below. When trying to arithmetically or logically shift certain variables X, Y, Z, first, the respective shift numbers sX, s
Y and sZ are sequentially stored at consecutive addresses in the shift number memory 3. Next, one of the shift number memory pointers 5 represented by psa is set to the address of the shift number memory 3 storing the shift number sX through the input data bus 1. When variables X, Y and Z are successively applied to barrel shifter 2 via input data bus 1, shift number memory pointer 5 indicating the address where shift number sX is stored
Is selected, and psa is incremented so that shift numbers sX, sY, and sZ corresponding to X, Y, and Z are given to the shift number bus 4, thereby obtaining X, Y, and
Z is shifted by the corresponding shift numbers sX, sY, and sZ, and output to the output data bus 7 via the ALU 6.

As described above, according to the present embodiment, the shift number for the variable is held in the shift number memory 3 and the contents of the address of the shift number memory 3 indicated by the shift number memory pointer 5 are given to the shift number bus 4. Thus, when there are many types of variable shifts, and when data is shifted using each of them, it is not necessary to set the number of shifts for each shift operation. A shift operation can be performed.

[0014]

As described above, according to the present invention, the barrel shifter arithmetically or logically shifts the input data by the shift number of the content of the address indicated by the shift number memory pointer. When a plurality of types exist and data is shifted using each of them, it is not necessary to set the number of shifts given to the barrel shifter for each shift operation. Therefore, the shift operation can be performed at high speed, the overhead of the program can be reduced, and a complicated setting of the number of shifts can be avoided, so that the program can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional arithmetic unit.

[Explanation of symbols]

 1 input data 2 barrel shifter 3 shift number memory 4 shift number bus 5 shift number memory pointer 6 ALU 7 output data bus

Claims (1)

(57) [Claims] A bus to which input data is supplied, a barrel shifter for arithmetically or logically shifting data on the bus, a memory for holding a shift number, a shift number bus for giving a shift number from the memory to the barrel shifter, And a plurality of pointers indicating addresses of the memory to be transmitted to the shift number bus.