JP3332022B2 - Semiconductor device damage evaluation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for evaluating damage caused in a semiconductor integrated circuit manufacturing process.

[0002]

2. Description of the Related Art A process for manufacturing a semiconductor device includes a dry etching process and a chemical vapor deposition (CVD) process.
n) process, sputtering process and the like.

[0003] In these steps, a semiconductor device in a manufacturing process may be electrically damaged. For example, MOS
In the case of a transistor, since a gate insulating film is thinned with miniaturization of an element, a high voltage is locally applied by charging or the like at the time of etching or film formation, and dielectric breakdown may occur.

[0004] Further, with the increase in the degree of integration and the increase in the number of layers of semiconductor integrated circuits, vias are formed in an interlayer insulating film, and wiring is drawn out onto the interlayer insulating film by buried wiring. When a defect occurs in a semiconductor element having such a structure, it is desired to determine which of the step of forming a via and the step of forming a wiring metal in the via causes the destruction of the element. .

[0005] For this reason, conventionally, damage in a semiconductor device manufacturing process has been evaluated to prevent the manufacture of a defective semiconductor device.

As a conventional method for evaluating the damage of via formation, for example, as described in JP-A-8-83827, a method is used in which an insulating film on a conductive film is formed using a method that does not cause plasma damage. After irradiating the substrate with plasma, the insulating film on the conductive film is removed, and the breakdown voltage between the substrate and the conductive film is measured to evaluate the damage. Also, Japanese Patent Application Laid-Open
No. 0-79407 discloses a semiconductor device in which a wiring metal connected to a gate electrode and another wiring metal adjacent to the wiring metal and connected via a semiconductor substrate and a diode are formed. A method is described in which the former damage to the wiring metal due to the presence of the wiring metal is calculated, and the result is used to evaluate the damage to the gate insulating film.

[0007]

SUMMARY OF THE INVENTION However, Japanese Patent Application Laid-Open No.
In the evaluation method described in Japanese Patent No. 3827, when forming a via, etching is performed using a method that does not cause plasma damage to the insulating film, and then the substrate is again irradiated with plasma. Since the method of evaluating the damage after removing the insulating film once formed is used, the evaluation of the damage is not performed according to the actual device structure.

Further, in the evaluation method described in Japanese Patent Application Laid-Open No. H10-79407, the presence or absence of damage is evaluated after the device is formed, so that it is not possible to specify the process in which damage occurs. For this reason, it is impossible to determine which of the step of forming the via and the step of forming the wiring metal in the formed via causes the destruction of the element.

The present invention has been made in view of such circumstances, and has as its object to determine the cause of damage more accurately or in detail.

Another object of the present invention is to specify whether the cause of damage is via formation or wiring metal formation.

Another object of the present invention is to evaluate damage in a state conforming to the actual device structure.

[0012]

According to a first aspect of the present invention, there is provided a method for evaluating damage to a semiconductor device, comprising: a semiconductor substrate on which an element region including a source region, a channel region, and a drain region is formed; A gate insulating film formed on a substrate, a conductive layer formed on the gate insulating film and having a gate electrode region, a via formation region, and a measurement pad region facing the channel region; and the gate insulating film and the conductive layer. An element forming step of forming a damage evaluation element having a structure including an interlayer insulating film formed on a conductive layer, and forming a via in the interlayer insulating film on the via forming region; wherein the interlayer insulating film, a via forming step of forming a hole having a large diameter than the via, by bringing probes into contact with the measurement pad area within the hole, the Dame A first measuring step of measuring electrical characteristics of the evaluation device, characterized in that it comprises a.

Furthermore, a wiring metal layer (metal wiring, for example, a plug) connected to the conductive layer is formed in the via and the hole formed in the interlayer insulating film, and on the interlayer insulating film, A wiring forming step of forming a wiring metal layer (metal wiring) connected to the wiring metal layer in the via, and a step of contacting a probe with the wiring metal layer to measure an electrical characteristic of the damage evaluation element. And two measurement steps.

Preferably, based on the electrical characteristics of the damage evaluation element measured in the first measuring step,
The damage to the semiconductor element caused by the via forming step is evaluated. If it is determined that the wiring metal layer has not been damaged, a wiring metal layer is formed in the via and the hole, and the electrical characteristics of the damage evaluation element in which the wiring metal layer is formed in the second measurement step are determined. Based on the evaluation, damage to the semiconductor element caused by the wiring forming step is evaluated.

According to this evaluation method, since the hole is larger in diameter than the via, damage is caused in the step of forming the hole by plasma etching or the like and the step of forming (depositing) a wiring metal layer in the hole by CVD or sputtering. Is unlikely to occur. Therefore, if it is determined from the electrical characteristics measured in the first measurement step that the damage evaluation element is damaged, it can be specified that the cause is due to the formation of vias. On the other hand, when the damage evaluation element which is determined not to be damaged in the first measurement step is measured in the second measurement step and is determined to be damaged, the wiring metal layer is removed from the via metal layer. It is possible to determine that damage has occurred by a process of forming the plug (for example, a process of forming a plug).

Therefore, it is possible to determine which of the step of forming the via and the step of forming the wiring metal layer in the via damages the semiconductor element.

Further, damage due to formation of vias and formation of a wiring metal layer is likely to occur in fine vias. Therefore, if the hole is formed in a size of 100 × 100 μm or more,
Almost no damage is caused by the formation of the hole or the formation of the wiring metal layer in the hole. Therefore, only the damage caused by the formation of the via and the formation of the wiring metal layer in the via can be evaluated.

By using a plurality of damage evaluation elements having different numbers of vias, the relationship between the number of vias and the damage can be further evaluated.

The damage evaluation element may further include, for example, a field insulating film having an opening on an element region on the semiconductor substrate, and the gate insulating film may be formed on the semiconductor substrate in the opening and on the field insulating film. The via forming region and the measurement pad region are formed on the field insulating film.

With this configuration, the element region is not damaged by the formation of the via and the formation of the wiring metal layer in the via.

It is desirable that the damage evaluation element has substantially the same configuration as the actual device. In other words, the actual device to be actually evaluated is substantially the same as the damage evaluation element having the above configuration except that it does not include, for example, the measurement pad region and the opening of the interlayer insulating film corresponding thereto. It is desirable to have the same configuration.

By making the structure of the damage evaluation element the same as that of the actual device (the device to be actually evaluated) except for the hole forming portion, the evaluation according to the actual device becomes possible.

According to a second aspect of the present invention, there is provided a method for evaluating damage to a semiconductor device, comprising: forming a semiconductor substrate on which an element region including a source region, a channel region, and a drain region is formed; Gate insulating film,
A conductive layer formed on the gate insulating film, a first interlayer insulating film formed on the gate insulating film and the conductive layer and having vias embedded with wiring, and a first interlayer insulating film on the first interlayer insulating film Forming a damage evaluation element having a structure including: a wiring layer having a via forming region and a measurement pad region; and a second interlayer insulating film formed on the first interlayer insulating film and the wiring layer. Forming a via in the second interlayer insulating film on the via forming region;
A via forming step of forming a hole having a larger diameter than the via on the measurement pad area;
And a first measurement step of measuring the electrical characteristics of the damage evaluation element by bringing a probe into contact with the measurement pad region in the inside .

Furthermore, a wiring metal layer connected to the wiring layer is formed in the via and the hole of the second interlayer insulating film, and the wiring and metal layer are formed on the second interlayer insulating film in the via and the hole. A wiring layer forming step of forming a wiring metal layer connected to the wiring metal layer formed on the substrate, and a second measurement of measuring an electrical characteristic of the damage evaluation element by bringing a probe into contact with the wiring metal layer. And a step.

Preferably, based on the electrical characteristics of the damage evaluation element measured in the first measuring step,
The damage to the semiconductor element caused by the via forming step is evaluated. If it is determined that the wiring metal layer is not damaged, a wiring metal layer is formed in the via and the hole of the second interlayer insulating film, and the damage evaluation element having the wiring metal layer formed in the second measurement step is formed. Based on the electrical characteristics of the semiconductor device, damage to the semiconductor element in the wiring layer forming step is evaluated.

By using the above method, it is possible to evaluate the damage after forming the via in the second interlayer insulating film, and to specify the damage due to the formation of the via and the damage due to the formation of the wiring metal layer. .

Damage due to the formation of vias and the formation of wiring metal layers usually occurs in fine vias. Therefore, the second
The size of the hole formed in the interlayer insulating film is 100 × 10
When the thickness is 0 μm or more, no damage is caused by the formation of holes and the formation of the wiring metal layer in the holes. Therefore, only the damage due to the formation of the via or the formation of the wiring metal layer in the via can be evaluated.

By using a plurality of damage evaluation elements having different numbers of vias, the relationship between the number of vias and the damage can be further evaluated.

The damage evaluation element further includes, for example, a field insulating film having an opening on the element region on the semiconductor substrate, and the gate insulating film is formed on the semiconductor substrate in the opening and on the field insulating film. The via forming region and the measurement pad region are formed on the field insulating film.

According to the above configuration, the element region is not damaged by the formation of the via and the wiring metal layer.

Further, it is desirable that the damage evaluation element has substantially the same configuration as the actual device. In other words, the actual device to be actually evaluated is, for example,
It is desirable that the device has substantially the same configuration as the damage evaluation element having the above configuration except that the measurement pad region and the corresponding opening of the interlayer insulating film are not provided.

By making the structure of the damage evaluation element the same as that of the actual device except for the portion where the hole is formed, it is possible to make an evaluation suitable for the actual device.

[0033]

(First Embodiment) A method for evaluating damage to a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1A is a cross-sectional view of a damage evaluation element for evaluating damage due to via formation.
FIG. 1B is a plan view of the damage evaluation element shown in FIG. An AA cross section in FIG. 1B corresponds to FIG. FIG. 2 is a cross-sectional view of a damage evaluation element for evaluating damage caused by forming a wiring metal in a via. FIG. 3 is a diagram for explaining a method of evaluating the damage of the damage evaluation element shown in FIG. 1, and FIG. 4 is a diagram for explaining a damage evaluation method of the damage evaluation element shown in FIG. is there. FIG.
FIG. 5A shows a cross-sectional configuration of an evaluation target element whose cause of damage is evaluated (identified) using the damage evaluation method according to the present embodiment, and FIG. 5B shows a planar configuration thereof. . FIG. 5B is a sectional view taken along the line A′-A ′ in FIG.
(A).

The element to be evaluated shown in FIG.
A semiconductor substrate 11 having an element region including a channel region and a drain region formed thereon, a field insulating film 12 having an opening 12a on the element region, and a semiconductor substrate 11 formed on the field insulating film 12 and the semiconductor substrate 11 in the opening 12a. A gate insulating film 13; a conductive layer 14 formed on the gate insulating film 13 and having a gate electrode region 14a and a via forming region 14b facing the channel region;
b having an via 15b formed thereon.
And wiring metal (plug) 1 formed in via 15b
6b, and a wiring metal layer 17 formed on the interlayer insulating film 15 and connected to the wiring metal 16b.

The via 15b is formed to have a diameter of 0.25 × 0.25 μm or less by dry etching.
The wiring metal 16b is formed by depositing a metal by CVD or sputtering and etching it back by dry etching.

In the present embodiment, the damage to the gate insulating film 13 caused by the step of forming the via 15 b
The present invention provides an evaluation method for independently evaluating the damage to the gate insulating film 13 caused by the step of forming the wiring metal 16b in 5b.

In order to evaluate the damage of the device to be evaluated shown in FIG. 5, for example, a device for damage evaluation having the structure shown in FIG. Configured in the manufacturing process.

In the damage evaluation device shown in FIG. 1, substantially the same portions as those of the device to be evaluated shown in FIG. 5 are denoted by the same reference numerals.

As shown in FIG. 1A, a damage evaluation element used in the first embodiment is formed on a semiconductor substrate 11 on which a source region, a channel region, and a drain region are formed. A field insulating film 12 having an opening 12a thereon is formed. And the opening 12a
Field insulating film 1 including over the element region in which is formed
2, a gate insulating film 13 is formed. A conductive layer 14 having a gate electrode region 14a facing the channel region, a via formation region 14b, and a measurement pad region 14c is formed on the gate insulating film 13, and an interlayer insulating film is formed on the gate insulating film 13 and the conductive layer 14. A film 15 is formed.

Vias 15b and holes 15c are formed in a region of the interlayer insulating film 15 above the via forming region 14b and the measuring pad region 14c. The via 15b and the hole 15c are simultaneously etched using dry etching. The size of the via 15a formed at this time has a diameter of 0.25 × 0.25 μm or less, and the size of the hole 15c has a diameter of 100 × 100 μm or more. Since the hole 15c has a sufficiently large diameter, even if it is formed by dry etching, local charging or the like hardly occurs and the gate insulating film 13 is not damaged.

The damage evaluation device shown in FIG. 1 is different from the damage evaluation device shown in FIG. 1 in that the conductive layer 14 has a measurement pad region 14c and a large-diameter hole 15c is formed in the region of the interlayer insulating film 15 on the measurement pad region 14c. For example, the configuration is substantially the same as the state in which the evaluation target element shown in FIG. 5 is in the manufacturing process.

When the damage evaluation element shown in FIG. 1 is completed, in order to evaluate the damage caused by etching (forming) of the via 15b, for example, as shown in FIG. 3, a probe is brought into contact with the measurement pad area 14c. , F. N.
(Fowler Nordheim) A voltage in a range in which a current (or a direct tunnel current) is not dominant is applied to the gate insulating film 13 and a leak current is measured.

If a leak current is detected, via 1
If the gate insulating film 13 is damaged by the etching (formation) of the gate insulating film 5b, and no leakage current is detected, it means that the via 15b has not been damaged by the etching.

When it is evaluated that the damage evaluation element of FIG. 1 has not been damaged by the via etching,
Subsequently, the via 1 is formed using CVD, sputtering, or the like.
A metal is deposited on the entire substrate including inside 5b and inside hole 15c. Further, this metal layer is etched back using dry etching, so that the wiring metal 16b and the wiring metal 16b are formed in the via 15b and the hole 15c as shown in FIG.
and c. Since the diameter of the hole 15c is sufficiently large, even if the wiring metal 16c is formed by CVD (or sputtering), dry etching, or the like,
Electrification and the like hardly occur, and the gate insulating film 13 is not damaged.

Next, a metal layer is deposited on the entire surface and is patterned to form a first metal wiring layer 17 connected to the wiring metals 16b and 16c as shown in FIG.

At the stage when the damage evaluation element shown in FIG. 2 is completed, in order to evaluate the damage caused by forming the wiring metal 16b in the via 15b, as shown in FIG. The probe was brought into contact with F.
N. A voltage in a range in which a current (or a direct tunnel current) is not dominant is applied to the gate insulating film 13 and a leak current is measured.

If a leak current is detected, damage due to the formation of the wiring metal 16b has occurred in the gate insulating film 13. If no leak current has been detected, no damage has occurred due to the formation of the wiring metal 16b. Will be.

As described above, according to the first embodiment, the damage due to via formation can be evaluated by using the damage evaluation element in which the measurement pad area 14c is provided on the conductive layer 14. . If no damage has occurred, the damage due to the formation of the wiring metal can be evaluated by using a damage evaluation element formed with the wiring metal 16b.

Therefore, the damage can be evaluated after the formation of the via and after the formation of the wiring metal, so that the cause of the damage can be specified. In addition, since the damage evaluation element uses a manufacturing method suitable for the actual device structure except for the formation of holes, damage can be evaluated in the same state as the actual device structure.

(Second Embodiment) Next, a method for evaluating damage to a semiconductor device according to a second embodiment will be described with reference to FIGS.

FIG. 6 is a sectional view of a damage evaluation element for evaluating damage when a via is formed in the second interlayer insulating film by dry etching. FIG.
FIG. 11 is a cross-sectional view of a damage evaluation element for evaluating damage when a wiring metal is formed in a via formed in a second interlayer insulating film.

The element for damage evaluation shown in FIG. 6 has a field insulating film 3 having an opening 32 a on a semiconductor substrate 31.
2 are formed, and a gate insulating film 33 is formed on the semiconductor substrate 31 in the opening 32a and on the field insulating film 32. A conductive layer is formed on the gate insulating film 33, and the first via 3 is formed on the gate insulating film 33 and the conductive layer.
A first interlayer insulating film 35 on which 5b is formed is formed. The first via 35b has a diameter of 0.3 × 0.3 μm.
It is a larger size, or formed by a process that does not cause damage, such as by not using plasma. Further, a wiring metal (plug) 36 is formed in the first via 35b in a process that does not cause damage.

On the first interlayer insulating film 35 including the first via 35b and the wiring metal 36, a first wiring metal layer 37 having a second via forming region 37b and a measurement pad region 37c is formed. Have been. Then, a second interlayer insulating film 45 is formed on the first interlayer insulating film 35 and the first wiring metal layer 37.

A second via 45b and a hole 45c are formed in the second interlayer insulating film 45 on the second via formation region 37b and the measurement pad region 37c. Second
The via 45b and the hole 45c are formed by simultaneous etching using dry etching. The size of the second via 45b is 0.3 × 0.3 μm or less, and the size of the hole 45c is 100 × 100 μm. Having.

Using the damage evaluation element shown in FIG.
In order to evaluate the damage caused by etching the second via 45b, a probe is brought into contact with the measurement pad area 37c, and the F.V. N. A voltage in a range where the current (or direct tunnel current) is not dominant is applied to the gate insulating film 33, and the leak current is measured.

If a leak current is detected, the gate insulating film 13 is damaged by the formation of the second via 45b in the second interlayer insulating film 45, and if no leak current is detected, No damage has occurred.

When it is evaluated that the damage evaluation element of FIG. 6 has not been damaged due to the formation of the second via 45b, subsequently, as shown in FIG. 7, the inside of the second via 45b and the hole are formed. In 45c, wiring metals 46b and 46c are formed by a CVD method or the like. Then, a third wiring metal 47 is formed on the second interlayer insulating film 45 including the wiring metals 46b and 46c.

Using the damage evaluation element shown in FIG.
In order to evaluate the damage caused by forming the wiring metal 46b in the second via 45b, a probe is brought into contact with the first wiring metal layer 17, and a DC power supply is used to evaluate the F.V. N.
A voltage in a range where the current is not dominant is applied to the gate insulating film 33.
To measure the leakage current.

When a leak current is detected, the wiring metal 46b is formed in the second via 45b of the second interlayer insulating film 45.
This means that the gate insulating film 33 has been damaged by the formation of. On the other hand, if no leak current is detected, no damage has occurred due to the formation of the wiring metal.

As described above, the first wiring metal layer 3
By using the damage evaluation element provided with the measurement pad area 37c on the top 7, the damage caused by the formation of the second via 45b can be evaluated. If no damage occurs, the damage caused by the formation of the metal wiring 46b can be evaluated by using a damage evaluation element in which the wiring metal 46b is formed in the second via 45b.

In the first and second embodiments, the damage evaluation method when forming a via in the first interlayer insulating film or the second interlayer insulating film and the damage evaluation when forming a wiring metal in the via are described. Although the method has been described, the damage due to the formation of the via and the formation of the wiring metal can be evaluated even in a semiconductor device having a more multilayer structure.

The method of forming vias and wiring metal is not limited to the above-described method. For example, sputtering or C
A metal is deposited on the interlayer insulating film including the via and the opening by VD, and the deposited metal layer is patterned to form a wiring metal in the via and the opening and a wiring layer on the interlayer insulating film. It is also possible.

In the first and second embodiments, the method of detecting a leak current has been described as a method of evaluating damage. However, the withstand voltage when a voltage is applied and the amount of charge that can be injected before destruction are determined. It is also possible to use interface state density, flat band voltage, and the like as indices.

In the present embodiment, a method for forming and evaluating a damage evaluation element on a part of a wafer has been described. However, a wafer having the damage evaluation element formed on a part of a semiconductor device manufacturing line is incorporated. It is also possible.

Further, by using several types of damage evaluation elements in which the number of vias formed in the via formation region is changed, the damage amount due to the number of vias can be relatively compared.

[0067]

As described above, according to the present invention, the cause of damage can be specified more accurately.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a damage evaluation element for evaluating damage due to via formation in a first embodiment, and FIG. 1B is a sectional view of the damage evaluation element shown in FIG. It is a top view.

FIG. 2 is a cross-sectional view of a damage evaluation element for evaluating damage due to formation of a wiring metal according to the first embodiment.

FIG. 3 is a diagram illustrating a method for evaluating damage due to via formation in the first embodiment.

FIG. 4 is a diagram for explaining a method for evaluating damage due to formation of wiring metal in the first embodiment.

5A is a cross-sectional view of an evaluation target element for which damage is to be evaluated, and FIG. 5B is a plan view of the evaluation target element shown in FIG.

FIG. 6 is a cross-sectional view of a damage evaluation element for evaluating damage due to via formation in the second embodiment.

FIG. 7 is a cross-sectional view of a damage evaluation element for evaluating damage due to formation of a wiring metal in a second embodiment.

[Explanation of symbols]

11, 31 Semiconductor substrate 12, 32 Field insulating film 12a, 32a Opening 13, 33 Gate insulating film 14, 34 Conductive layer 14a Gate electrode region 14b, 37b Via forming region 14c, 37c Measurement pad region 15, 35 First interlayer insulation Film 15b, 35b, 45b Via 15c, 45c Hole 16b, 16c, 36, 46b, 46c Wiring metal 17, 37 First wiring metal layer 45 Second interlayer insulating film 47 Second wiring metal layer

Claims (12)

(57) [Claims] A semiconductor substrate on which an element region including a source region, a channel region, and a drain region is formed; a gate insulating film formed on the semiconductor substrate; and a via formed on the gate insulating film. Forming a damage evaluation element having a structure including a conductive layer having a region, a measurement pad region, and a gate electrode region facing the channel region; and the gate insulating film and an interlayer insulating film formed on the conductive layer. Forming a via in the interlayer insulating film on the via forming region, and forming a hole with a larger diameter than the via in the interlayer insulating film on the measurement pad region; and characterized by comprising said probe is brought into contact with the measurement pad area within the hole, and a first measuring step of measuring electrical characteristics of the damage evaluation elements, the Damage evaluation how. 2. A wiring metal layer connected to the conductive layer is formed in the via and the hole formed in the interlayer insulating film, and on the interlayer insulating film, a wiring metal layer in the via is formed. A wiring forming step of forming a connected wiring metal layer; and a second measuring step of measuring the electrical characteristics of the damage evaluation element by bringing a probe into contact with the wiring metal layer. The damage evaluation method according to claim 1, wherein 3. A first evaluation step of evaluating damage to a semiconductor element in the via forming step based on the electrical characteristics of the damage evaluation element measured in the first measurement step; The second evaluation step measures the electrical characteristics of the damage evaluation element evaluated as having not been damaged in the second evaluation step, and evaluates the damage to the semiconductor element in the wiring formation step. The damage evaluation method according to claim 2, comprising: an evaluation step. 4. The method according to claim 1, wherein the step of forming the via includes:
The damage evaluation method according to claim 1, wherein the damage evaluation method is a step of forming a size of 100 μm or more. 5. The device for damage evaluation further includes a field insulating film having an opening on the element region on the semiconductor substrate, wherein the gate insulating film is provided on the semiconductor substrate in the opening and on the field. The damage according to any one of claims 1 to 4, wherein the damage is formed on an insulating film, and the via forming region and the measurement pad region are formed on the field insulating film. Evaluation method. 6. The method according to claim 1, wherein the relationship between the number of vias and the damage is further evaluated by using a plurality of damage evaluation elements having different numbers of vias. The damage evaluation method described. 7. A semiconductor substrate on which an element region including a source region, a channel region, and a drain region is formed, a gate insulating film formed on the semiconductor substrate, and a conductive layer formed on the gate insulating film A first interlayer insulating film formed on the gate insulating film and the conductive layer and having a via embedded with a wiring; a via forming region and a measurement pad region formed on the first interlayer insulating film; An element forming step of forming a damage evaluation element having a structure including a wiring layer having: a first interlayer insulating film and a second interlayer insulating film formed on the wiring layer; wherein a via is formed in the second interlayer insulating film, further, the measurement pad region, a via forming step of forming a hole having a large diameter than the via, pro to the measurement pad area within the hole Contacting the blanking, damage evaluation method characterized by and a first measuring step of measuring electrical characteristics of the damage evaluation element. 8. A wiring metal layer connected to the wiring layer is formed in the via and the hole of the second interlayer insulating film, and a wiring metal in the via is formed on the second interlayer insulating film. A wiring layer forming step of forming a wiring metal layer connected to the layer; and a second measuring step of measuring an electrical characteristic of the damage evaluation element by bringing a probe into contact with the wiring metal layer. The damage evaluation method according to claim 7, wherein: 9. A first evaluation step of evaluating damage to a semiconductor element in the via forming step based on electrical characteristics of the damage evaluation element measured in the first measurement step; A second measuring step of measuring the electrical characteristics of the damage evaluation element evaluated as not receiving the damage in the second evaluation step, and evaluating the damage to the semiconductor element by the wiring forming step; The damage evaluation method according to claim 8, comprising: 10. The method according to claim 1, wherein the step of forming the via has a size of 100.
10. The damage evaluation method according to claim 7, wherein the step is a step of forming a hole having a size of × 100 μm or more. 11. The relationship between the number of vias and the damage is further evaluated by using a plurality of damage evaluation elements having different numbers of vias formed in the second interlayer insulating film. The damage evaluation method according to claim 7. 12. The damage evaluation element further comprises a field insulating film having an opening on the element region on the semiconductor substrate, wherein the gate insulating film is provided on the semiconductor substrate in the opening and on a field insulating film. The damage evaluation according to any one of claims 7 to 11, wherein the via formation region and the measurement pad region are formed on the field insulating film. Method.