JP3332055B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art In a method of manufacturing a thin film transistor using a polysilicon layer as a semiconductor layer, in a case where an ion doping apparatus for a large glass substrate is used, a polysilicon layer is formed with a gate insulating film formed on the polysilicon layer. It is difficult to form source / drain regions by doping with ions because sufficient ion acceleration energy cannot be obtained. Therefore, in the related art, FIGS.
The thin film transistor is manufactured through the following steps.
Hereinafter, a conventional method of manufacturing a thin film transistor will be described with reference to these drawings. First, as shown in FIG. 2A, a polysilicon layer 2 serving as a device region is formed on the upper surface of a glass substrate 1. Then, as shown in FIG. 2B, a photoresist 3 is formed at a predetermined position on the upper surface of the polysilicon layer 2, and ions such as phosphorus (P) are doped by an ion doping apparatus using the photoresist 3 as a mask. . At this time, since a gate insulating film 6 described later is not provided on the upper surface of the polysilicon layer 2, ions can be satisfactorily doped into the polysilicon layer 2 which does not correspond to the photoresist 3. As a result, a channel region 4 is formed in a portion of the polysilicon layer 2 corresponding to the photoresist 3, and source / drain regions 5 are formed on both sides thereof. Next, the photoresist 3 is peeled off and the source / drain regions 5 are activated by laser irradiation, and a gate insulating film 6 is formed on the polysilicon layer 2 as shown in FIG. Next, as shown in FIG. 2D, a gate electrode 7 is formed on the gate insulating film 6 corresponding to the channel region 4. Thereafter, as shown in FIG. 2E, an interlayer insulating film 8 is formed on the gate insulating film 6 and the gate electrode 7, and the gate insulating film 6 and the interlayer insulating film 8 corresponding to the source / drain regions 5 are contacted. A hole is formed, and a source / drain electrode 9 is formed in the contact hole.
Are formed, and an overcoat film (not shown) is formed on these upper surfaces.
Is formed, a thin film transistor is completed.

[0003]

However, in this conventional method of manufacturing a thin film transistor, a gate electrode 7 is formed on a gate insulating film 6 formed on a channel region 4 of a polysilicon layer 2 by photolithography. Although high accuracy is required for mask alignment because of non-self-alignment, it is difficult to align the gate electrode 7 with a portion corresponding to the channel forming region. As a result, an overlapping portion A between the gate electrode 7 and the source / drain region 5 occurs. When such an overlapping portion A exists, a parasitic capacitance is generated, and when the thin film transistor operates, in addition to the channel region 4, the overlapping portion A
Therefore, there is a problem that the operation speed is reduced and the power consumption is increased because the extra capacity is charged and discharged. An object of the present invention is to provide a method of manufacturing a thin film transistor capable of high-speed operation and preventing an increase in power consumption even when an overlapping portion between a gate electrode and a source / drain region exists.

[0004]

According to the present invention, a resist is formed at a position corresponding to a channel forming region on a semiconductor layer, and ions are implanted into the semiconductor layer using the resist as a mask.
After forming the first insulating film on the semiconductor layer and the resist,
Peeling the resist and removing the resist
A concave portion is formed by removing the first insulating film, a second insulating film is formed on the semiconductor layer exposed in the first insulating film and the concave portion, and a gate is formed at a position corresponding to the concave portion on the second insulating film. An electrode is formed.

[0005]

According to the present invention, even if the gate electrode formed on the second insulating film overlaps the outside of the channel formation region of the semiconductor layer, for example, the source / drain region of the semiconductor layer, the semiconductor layer outside of the channel formation region is in advance. Since the first insulating film is formed thereon, the thickness of the overlapping portion can be made thicker by the first insulating film than the thickness of the portion corresponding to the channel formation region. It is possible to reduce the parasitic capacitance, and as a result, it is not necessary to charge and discharge extra capacitance at the overlapped portion during operation, so that a thin film transistor capable of high-speed operation and preventing an increase in power consumption can be obtained. Can be.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 (a) to 1 (f),
A method for manufacturing a thin film transistor according to an embodiment of the present invention will be described. First, as shown in FIG. 1A, a polysilicon layer (semiconductor layer) 11 serving as a device region is formed on the upper surface of a glass substrate 10 to a thickness of about 500 °. Then, as shown in FIG. 1B, a photoresist 1 is formed on a portion of the polysilicon layer 11 corresponding to the channel formation region.
Then, ions such as phosphorus (P) are doped by an ion doping apparatus using the photoresist 12 as a mask. As a result, a channel region 13 is formed in a portion of the polysilicon layer 11 corresponding to the photoresist 12, and source / drain regions 14 are formed on both sides thereof. The steps so far are the same as in the conventional case.

Next, as shown in FIG. 1C, a plasma CV is formed on the polysilicon layer 11 and the photoresist 12.
A buffer insulating film (first insulating film) 15 made of silicon oxide or the like is formed to a thickness of several thousand に よ っ て by the D method. next,
The buffer insulating film 15 corresponding to the side wall of the photoresist 12 is removed by light etching.
Expose part of 2 At this time, when the buffer insulating film 15 is formed, step coverage occurs at a position corresponding to the side wall of the photoresist 12, whereby the film thickness of the buffer insulating film 15 corresponding to the side wall of the photoresist 12 is reduced. Flat buffer insulating film 1
5, the buffer insulating film 15 corresponding to the side wall of the photoresist 12 is easily removed by light etching, and the flat buffer insulating film on the upper surface of the photoresist 12 is removed. 15 remains. Next, the photoresist 12 is removed. At this time, the buffer insulating film 15 on the photoresist 12 is formed together with the photoresist 12.
Is removed as well. As a result, as shown in FIG. 1D, the buffer insulating film 15 remains on the polysilicon layer 11 other than the channel region 13, and a concave portion 16 is formed in a portion of the polysilicon layer 11 corresponding to the channel region 13. .

Next, the source laser is irradiated by pulse laser irradiation.
The drain region 13 is activated, and as shown in FIG. 1E, a gate insulating film (second insulating film) 17 made of silicon oxide or the like is formed on the buffer insulating film 15 and the polysilicon layer 11 exposed in the concave portion 16 by 1000. It is formed with a film thickness of about. Next, a gate electrode 18 made of chromium or the like is formed on the gate insulating film 17 corresponding to the recess 16. At this time, since the alignment of the mask by the photolithography method is not self-aligned, the gate electrode 1
8 is outside the recess 16 as shown in FIG.
Some will be formed above the drain region 14 as well. Therefore, there is an overlapping portion B where the gate electrode 18 and the source / drain region 14 overlap.

Thereafter, as shown in FIG. 1F, an interlayer insulating film 19 made of silicon nitride or the like is formed on the gate insulating film 17 and the gate electrode 18 to a thickness of about 5000.degree. A contact hole is formed in the buffer insulating film 15, the gate insulating film 17, and the interlayer insulating film 19 corresponding to the above, a source / drain electrode 20 is formed in the contact hole, and an overcoat film (not shown) is formed on these upper surfaces. Is formed, a thin film transistor is completed.

In such a method of manufacturing a thin film transistor, when the gate electrode 18 is formed via the gate insulating film 17 in the concave portion 16 formed corresponding to the channel region 13, the gate electrode 18 and the source / drain region 14 are formed. Are present in advance even if there is an overlapping portion B where
Since the buffer insulating film 15 several times thicker than the gate insulating film 17 is formed on the polysilicon layer 11 outside, the thickness of the overlapping portion B is several times larger than the thickness corresponding to the channel region 13. It is possible to increase the thickness, thereby reducing the parasitic capacitance at the overlapping portion B. As a result, it is not necessary to charge and discharge the extra capacitance at the overlapping portion during operation, so that high-speed operation is possible, and A thin film transistor which can prevent an increase in power consumption can be obtained.

In the method of manufacturing the thin film transistor, the source / drain region 14 of the polysilicon layer 11 is covered with the buffer insulating film 15 when the photoresist 12 is peeled off. Good electrical characteristics can be obtained without impairing the smoothness of the film.

In the above embodiment, the polysilicon layer 1
Although the source / drain regions 14 are formed directly on both sides of one channel region 13, the invention is not limited to this. For example, a low concentration region may be formed between the channel region 13 and the source / drain regions 14. In this case, the photoresist 12 is formed on the channel formation region of the polysilicon layer 11.
Is formed, and the polysilicon layer 11 other than the channel formation region is formed.
After doping low-concentration ions (for example, phosphorus ions) therein, the photoresist 12 is removed and the polysilicon layer 1 is removed.
A photoresist is formed on the first channel region and the low-concentration formation region, and a high-concentration ion (for example, phosphorus ion) is doped in this state, thereby forming a low-concentration region between the channel region 13 and the source / drain region 14. Can be formed. Such a method of manufacturing a thin film transistor has the same effect as the above embodiment.

[0013]

As described above, according to the present invention, even if the gate electrode formed on the second insulating film overlaps the outside of the channel formation region of the semiconductor layer, for example, the source / drain region of the semiconductor layer, Since the first insulating film is formed on the semiconductor layer outside the channel formation region in advance, the thickness of the overlapped portion may be larger than the thickness of the portion corresponding to the channel formation region by the thickness of the first insulating film. As a result, the parasitic capacitance at the overlapped portion can be reduced, and as a result, it is not necessary to charge and discharge the extra capacitance at the overlapped portion during operation, thereby enabling high-speed operation and increasing power consumption. A thin film transistor that can be prevented can be obtained.

[Brief description of the drawings]

FIGS. 1A to 1F are cross-sectional views showing a manufacturing process of a thin film transistor to which an embodiment of the present invention is applied.

FIGS. 2A to 2E are cross-sectional views illustrating an example of a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Polysilicon layer 12 Photoresist 13 Channel region 14 Source / drain region 15 Buffer insulating film 16 Depression 17 Gate insulating film 18 Gate electrode

Claims (1)

(57) [Claims] 1. A resist is formed at a position corresponding to a channel formation region on a semiconductor layer, ions are implanted into the semiconductor layer using the resist as a mask, and a first insulating film is formed on the semiconductor layer and the resist. After the resist
And removing the first insulating film on the resist.
After forming a concave portion by removing , forming a second insulating film on the first insulating film and the semiconductor layer exposed in the concave portion, a gate is formed at a position corresponding to the concave portion on the second insulating film. A method for manufacturing a thin film transistor, comprising forming an electrode.