JP3332545B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a P-substrate type high breakdown voltage semiconductor device such as a PNP type high breakdown voltage planar transistor and a P-channel vertical MOS semiconductor device.

[0002]

2. Description of the Related Art FIG. 3A shows an example of the structure of a conventional PNP type silicon planar transistor. The P ⁺ -type silicon semiconductor substrate 1 includes a P ⁻ -type epitaxial growth layer 4, and an element diffusion region such as an N-type base region 2 and a P ⁺ -type emitter region 3 is formed in the epitaxial growth layer 4. ing. A peripheral portion of the chip around the element diffusion region is covered with an oxide film 6, and a P ⁺ type channel stop region 11 is provided at a peripheral portion of the chip. Ohmic contact.

[0003] The oxide film 6 of such a PNP-type silicon bipolar transistor contains a very small amount of mobile cations 7 such as an alkali element. Collector area 4
An extremely thin N-type inversion layer 15 is formed on the surface.
Therefore, on both sides of the collector / base junction PN junction,
In the case of not applying reverse bias voltage (V _R = 0), spreads the depletion layer 17 shown in Figure 3 (A).

For example, the breakdown voltage B of the collector / base junction
When a reverse bias voltage is applied between the collector electrode 12 and the base electrode 8 to measure V _CBO , the depletion layers 17 on both sides of the collector / base junction expand as shown in FIGS. 3 (B) and 3 (C). FIG. 3B shows the spread of the depletion layer 17 when V _R = approximately 50 V, which is sufficiently smaller than the breakdown voltage, is applied as an example. FIG. 3C shows the spread of the depletion layer 17 when V _R = 1000 V immediately before the breakdown voltage is applied. In a transistor having a general structure, the breakdown of the collector / base junction is caused by the fact that the potential gradient in the depletion layer at the portion indicated by reference numeral 18 having the smallest radius of curvature exceeds a certain intensity. appear.

However, the breakdown voltage of such a PNP transistor tends to increase when a high-temperature reverse bias (BT) test is performed. Figure 4 shows the high temperature reverse bias (BT)
It is explanatory drawing which shows the movement of a movable ion and an inversion layer after a test. The high-temperature reverse bias test is a test in which a (-) voltage is applied to the collector electrode 12 of the PNP transistor and a (+) voltage is applied to the base electrode 8, and the PNP transistor is left at a high temperature.

As the high-temperature reverse bias (BT) test proceeds, the movable ions 7 move to the interface with the collector region 4 in the oxide film 6 as shown in FIG. This is because movable ions 7 such as Na ⁺ and Ka ⁺ ions, which are positive charges, are attracted to the collector region 4 side because the cocker region 4 is biased to the (−) side.
As the mobile ions 7 move toward the collector region 4 in the vertical direction, the influence of the positive charges on the collector region 4 becomes stronger, so that electrons are attracted to the surface of the collector region 4 to form an N-type inversion layer.

For this reason, the inversion layer 15 formed by the movable ions 7 in the oxide film 6 moves to a deeper position from the surface of the semiconductor substrate during the BT test. Therefore, the depletion layer 1
7 moves downward in the collector region 4 as the inversion layer 15 moves, the radius of curvature of the depletion layer 17 is reduced near the corner of the diffusion region, the potential gradient decreases, and as a result, the collector / base junction of the collector / base junction is reduced. The breakdown voltage _BVCBO increases.

FIG. 5 illustrates a change in the collector / base junction breakdown voltage (BV _{CV O} ) in the BT test. As shown, the conventional PN shown in FIG.
The breakdown voltage of the P-type transistor is 700 V immediately after the start of the test.
It gradually increases from the level, reaches a constant value of about 1000 V, and saturates.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a P-substrate type semiconductor device which can provide a high withstand voltage and whose withstand voltage does not change with time, and a method of manufacturing the same. The purpose is to:

[0010]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device having an element diffusion region in a P-type semiconductor substrate, a hole trap level is formed by electron beam irradiation in an oxide film on the surface of the substrate.

According to a method of manufacturing a semiconductor device of the present invention, there is provided a step of forming an N-type element diffusion region on a P-type semiconductor substrate and an oxide film on the substrate; Forming a hole trap level in the film.

[0012]

Since hole trap levels are provided by electron beam irradiation in the oxide film on the surface of the P-type semiconductor substrate, an N-type inversion layer is formed on the surface of the P-type semiconductor substrate. This N
The inversion layer of the type spreads the depletion layer on the PN junction collector side at the time of reverse bias in the deep direction of the element diffusion region, relaxes the curvature of the depletion layer, and increases the breakdown voltage. High temperature reverse bias (B
T) In the test, even if mobile ions in the oxide film are attracted to the interface side of the semiconductor substrate, the depth of the N-type inversion layer is only slightly increased, and does not substantially affect the distribution of the depletion layer. Therefore, even in the BT test, the breakdown voltage of the collector / base junction is maintained at the initial high value,
No fluctuation of breakdown voltage occurs.

According to the method of manufacturing a semiconductor device of the present invention,
After a normal device diffusion region and an oxide film are formed to complete a P-substrate type semiconductor device, the semiconductor substrate is irradiated with an electron beam, so that a crystal structure distortion occurs in the oxide film on the semiconductor substrate. Can be given. The crystal structural distortion is
A hole trap level is formed in the oxide film, holes of positive charges are trapped in the oxide film, and N
A mold inversion layer is formed. Therefore, a P-substrate-type semiconductor device having a high withstand voltage and having no variation over time can be produced only by adding an electron beam irradiation step to the normal P-substrate-type semiconductor device production process.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First and second embodiments of the present invention will be described below with reference to the accompanying drawings. The structure of the PNP type bipolar transistor shown in FIG.
The structure is the same as that of the NP-type bipolar transistor, and the same or corresponding components are denoted by the same reference numerals, and redundant description will be omitted. In the semiconductor device of this embodiment shown in FIG. 1B, a hole trap level 16 indicated by a black dot is formed in an oxide film 6 provided on a semiconductor substrate 1. The hole trap level 16 is formed by diffusing an N-type base region 2 and a P ⁺ -type emitter region 3 in the semiconductor substrate 1 to form aluminum electrodes 8, 9, and 10. It is formed by irradiation.
The electron beam irradiation repeatedly irradiates the entire surface of the semiconductor substrate with a high energy electron beam of 1 to 2 mega eV. Since the electron beam has high energy, it penetrates through the aluminum electrode, the oxide film and the silicon semiconductor substrate 1 to form an oxide film. 6 forms a crystalline strain. It is considered that this crystal distortion forms a hole trap level that traps holes that are positive charges.

The amount of hole trap levels due to electron beam irradiation is proportional to the amount of electron beam irradiation. For this reason, the N-type inversion layer can be formed with high precision in proportion to the amount of irradiation with the electron beam having the unit energy.

The holes that are positive charges trapped in the hole trap levels 16 form an N-type inversion layer 15 deeper than the inversion layer formed by mobile ions on the surface of the P-type semiconductor substrate. When a reverse bias of about V _R = 1000 V close to the breakdown voltage is applied to the collector / base junction before the BT test, the depletion layer 17 spreading on both sides of the junction is shown in FIG.
The structure extends along the inversion layer 15 moved to a deep position as shown in FIG. Accordingly, in the region where the radius of curvature of the depletion layer is the tightest around the corner of the base diffusion region 2,
The depletion layer 17 is pushed down from the surface of the semiconductor substrate in a deeper direction, and the potential gradient is reduced.
The breakdown voltage is improved as compared with the state shown in FIG. That is, the N-type inversion layer 15 is formed by attracting the mobile ions 7 in the oxide film to the semiconductor interface side by the BT test in FIG. Level 16 is formed by trapping holes.

FIG. 1C illustrates the positions of the mobile ions 7 and the inversion layer 15 in the oxide film after the BT test. After the BT test, the movable ions 7 move toward the semiconductor substrate interface side in the oxide film 6 because the collector region 4 is biased to the negative side, as described above. However, since the N-type deep inversion layer 15 has already been formed by the hole trap level 16, the mobile ions 7 having positive charges that have moved to the semiconductor substrate interface side.
Only exerts the effect of pushing the inversion layer 15 slightly deeper from the state shown in FIG. Therefore, since the distribution of the depletion layer 17 at the time of reverse bias is hardly affected, the breakdown voltage does not change before and after the BT test.

FIG. 5 shows the transition of the breakdown voltage BV _CBO of the base / collector junction in the BT test. As shown in the figure after the formation of the hole trap level, in the transistor of this example, the breakdown voltage _BVCBO remains unchanged at the initial value of about 1000 V even after about 1000 hours have passed in the BT test.

In the above embodiment, the PNP type bipolar transistor has been described.
The present invention is also applicable to devices having a P-type substrate, such as SFETs and IGBTs.

FIG. 2 shows a second embodiment applied to a power MOSFET. An N-type body region 30 for forming a MOS element on the surface of the substrate
^{A +} source region 31 is formed, a polysilicon gate electrode 32 is arranged on a channel region of the body region 30 via a gate oxide film, and an aluminum source electrode 33 contacting both the body region 30 and the source region 31 is formed. Is formed. FIG. 2A shows a state before the formation of the hole trap level.
_It shows the state of _R = 700V. FIG. 2B shows a state in which hole trap levels are formed in oxide film 6 by electron beam irradiation. Inversion layer 15 is moved from the substrate surface to a deep position, the depletion layer pushed down, the breakdown voltage of curvature is relaxed is improved approximately V _R = 1000V. FIG. 3C shows a state after the BT test. The movable ions 7 move toward the substrate interface, but the inversion layer 15 and the depletion layer 17
Has little effect. Therefore, the breakdown voltage BV _SD between the source and the drain does not fluctuate with time, and the improved initial value withstand voltage is maintained as it is.

[0021]

As described above, the P-substrate type semiconductor device of the present invention has a hole trap level formed in the oxide film on the P-substrate surface. As a result, an N-type deep inversion layer is formed on the surface of the P-type substrate, and the depletion layer spreads deeper in the vicinity of the corner of the diffusion region, relaxing the potential gradient and increasing the breakdown voltage. Then, even if mobile ions in the oxide film move to the semiconductor substrate interface side in the BT test, a deep inversion layer is formed in advance, so that the expansion of the depletion layer is not affected.
Variations in breakdown voltage can be suppressed.

According to the method of manufacturing a semiconductor device of the present invention,
By simply adding one step of electron beam irradiation to the normal P-substrate-type semiconductor device manufacturing process, a P-substrate-type semiconductor device having a higher withstand voltage and having no fluctuation over time can be easily manufactured. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing the movement of mobile ions in an oxide film and the spread of a depletion layer in a PNP-type bipolar transistor according to a first embodiment of the present invention. FIG. 1A shows a state before a hole trap level is formed. , (B) shows the state before the BT test after the formation of the hole trap level, and (C) shows the state after the BT test after the formation of the hole trap level.

FIG. 2 shows a P-channel power MOS according to a second embodiment of the present invention.
4A and 4B are cross-sectional views showing movement of mobile ions in an oxide film of a FET and a state of expansion of a depletion layer, wherein FIG. 5A shows a state before a hole trap level is formed, and FIG. (C) shows the result after the BT test after the formation of the hole trap level.

FIG. 3 is a cross-sectional view showing a state in which a depletion layer of a conventional PNP bipolar transistor is expanded before a BT test;
(A) shows no reverse bias, (B) shows reverse bias V
_R = 50 V, and (C) shows a reverse bias V _R = 1000
V.

FIG. 4 is a cross-sectional view showing a spread state of a depletion layer of a conventional PNP-type bipolar transistor after a BT test;
(A) shows no reverse bias, (B) shows reverse bias V
_R = 700 V, and (C) shows a reverse bias V _R = 100
Indicates 0V.

FIG. 5 is an explanatory diagram showing a change in breakdown voltage BV _CBO in a BT test.

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Claims (2)

(57) [Claims] An N-type and P-type element are provided on a P-type semiconductor substrate.
Around the chip around the element diffusion region, including the element diffusion region
An oxide film is provided in the portion, and a chip periphery of the P-type semiconductor substrate is provided.
In a semiconductor device in which a channel stop region is provided at an edge, from the N-type element diffusion region to the channel stop region.
The oxide film covering the surface of the P-type semiconductor substrate at
The level that expands the depletion layer is formed by the irradiation of the beam, and the reverse bias is generated.
At the time of assembling, the P-type semiconductor substrate has the N-type element diffusion region.
A depletion layer having a gentle curvature is formed in the vicinity of the corner of the semiconductor device. 2. An N-type and P-type element on a P-type semiconductor substrate.
Forming a device diffusion region, and forming a chip around the device diffusion region.
Forming an oxide film in a peripheral portion and forming a chip on the P-type semiconductor substrate;
Forming a channel stop region in a peripheral portion; and forming a channel stop region from the N-type element diffusion region to the channel stop region.
An electron beam on the oxide film covering the surface of the P-type semiconductor substrate
To form a level in the oxide film that extends a depletion layer.
The method of manufacturing a semiconductor device characterized by comprising the that step.