JP3332866B2 - Video signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit used for processing a composite video signal output from, for example, a time lapse VCR. (2) A video signal processing circuit for processing a composite video signal provided at each of predetermined positions.

[0002]

2. Description of the Related Art According to the conventional surveillance camera system shown in FIG. 8, video signals Va to Vd output from a plurality of surveillance cameras 1a to 1d are thinned out by a multiplexer 4 for each predetermined field. The video signal after the thinning is intermittently recorded on the video cassette 3 by the time lapse VCR 2. Video tracks Va to Vd are formed on the video tape 3a, for example, as shown in FIG. When the video cassette 3 on which such intermittent recording is performed is reproduced, the time lapse V is set to prevent loss of the vertical synchronization signal and erroneous detection of the vertical synchronization signal due to switching noise.
In CR2, a pseudo vertical synchronizing signal is added to each of the reproduced video signals Va to Vd. Since the type of the reproduced video signal changes for each field, the multiplexer 4 individually writes the reproduced video signals Va to Vd into the memories 4a to 4d, and then outputs the signals to the monitor 5. As a result, the reproduced videos Va to Vd are divided and displayed on the monitor 5 as shown in FIG.

[0003]

However, the multiplexer 4 stores the video signals Va-Vd in the memories 4a-4d.
, The write start timing is determined based on the pseudo vertical synchronization signal. Therefore, if the pseudo vertical synchronizing signal is not correctly added, the write start timing will be shifted, and as a result, the reproduced videos Va to Vd displayed on the monitor 5 will be blurred in the vertical direction.
In other words, the video component starts from the 30th H of each field, but if the position of the pseudo vertical synchronizing signal is shifted as shown in FIG. 11, the reproduced video displayed on the monitor 5 is blurred.

[0004] Therefore, a main object of the present invention is to provide a video signal processing circuit capable of preventing blurring of a reproduced video.

[0005]

According to the present invention, there is provided a video signal processing circuit for processing a video signal provided at a first predetermined position of each field, wherein the identification signal for each camera is detected by a video signal processing circuit. Specifying means for specifying a predetermined position of the video signal based on the detected identification signal; writing means for writing the video signal from a predetermined position to a memory; and reading means for reading the video signal written to the memory. It is a video signal processing circuit characterized by the following.

[0006]

The predetermined information component provided at the first predetermined position of each field is detected by the component detecting means. The specifying means specifies a second predetermined position of the video signal based on the detected predetermined information component, and the writing means writes the video signal from the second predetermined position to the memory. The reading means reads the video signal thus written from the memory. For this reason, a vertical blur does not occur in the video signal read from the memory. According to an aspect of the present invention, in the specifying unit, the specific information detecting unit detects the specific information from the predetermined information component. Further, the first counter counts the number of lines based on the detection time of the specific information, and outputs second predetermined position information.

In one embodiment of the present invention, the predetermined information component extends over a plurality of lines. Then, the start position detecting means included in the specifying means detects the start position of the predetermined information component. Further, the two counters count the number of lines based on the detection time of the start position and output second predetermined position information.
Further, an end position detecting means detects an end position of the predetermined information component. The third counter counts the number of lines based on the detection time of the end position, and outputs second predetermined position information.

[0008] When a plurality of second predetermined position information are obtained in this way, the selection means selects any of the second predetermined position information according to a predetermined order. The writing unit resets the writing address according to the second predetermined position information output from the selection unit. Note that the second predetermined position is a start position of the effective component of the video signal.

[0009]

According to the present invention, the second predetermined position of the video signal is specified based on the predetermined information component, and the video signal is converted to the second predetermined position.
Since the data is written to the memory from a predetermined position, it is possible to prevent the vertical blurring of the video signal read from the memory. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0010]

Referring to FIG. 1, the surveillance camera system of this embodiment is the same as the surveillance camera system shown in FIG. 8 except that the multiplexer 10 is configured as shown in FIG. Description is omitted. Timelapse VC
Analog composite video signal Va output from R
To Vd are connected to the decoder 12a via the input terminals S1 to S4.
To 12d. Decoders 12a-12
d, digital composite video signals Va to V
d is output. The composite video signals Va to Vd are respectively reduced to 1/4 by the data compression circuits 14a to 14d.
And the compressed video signals Va to Vd are generated. Each of the compressed video signals Va to Vd is written to a predetermined address of the memory 18 according to a write address signal output from the corresponding write controller 16a to 16d. As a result, the compressed video signals Va to Vd are stored in the memory 18 in an image as shown in FIG.

The memory 18 includes a read controller 20
, And the compressed video signals Va to Vd are read from the memory 18. The read compressed video signals Va to Vd are output from the terminal S5 to the monitor via the ID-added data output circuit 22 and the encoder 24. Each of the composite video signals Va to Vd has a corresponding surveillance camera ID.
A signal has been added. As can be seen from FIG. 6, the ID signal is superimposed on the fifteenth to eighteenth lines of the odd field and the 277th to 280th lines of the even field. In this embodiment, the starting position of the effective period including the video component is specified based on the ID signal superimposed on the predetermined line. That is, unless the pseudo vertical synchronizing signal is added at an accurate position, the video component written in each of the memories 16a to 16d is blurred in the vertical direction. Thus, the start position of the video component cannot be specified from the position where the pseudo vertical synchronization signal is added. Therefore, in this embodiment, an ID signal superimposed on a predetermined position is detected, and a write address of the memory 18 is determined based on the ID signal.

The write controllers 16a to 16d are configured as shown in FIG. 2, and the composite video signal output from the corresponding decoder
It is provided to the detection circuit 26. The synchronization separation circuit 32 separates the horizontal synchronization signal and the vertical synchronization signal from the input composite video signal, and supplies the separated synchronization signals to the section detection circuit 34. The section detection circuit 34 is supposed to include the ID signal according to the input synchronization signal.
A line section is detected, and an ID detection circuit 2 is used in the detected section.
6 and the ID discrimination circuit 28 are activated. The ID detection circuit 26 monitors the level of the input signal, and outputs a high-level signal when the high-level period exceeds 3 μs. Thus, the ID signal superimposed on the video signal is detected.

The ID determining circuit 28 is configured as shown in FIG. The detection signal from the ID detection circuit 26 is given to the U / D terminal of the up / down counter 28a. The up / down counter 28a is incremented in response to the clock when the detection signal is at a high level, and decremented in response to the clock when the detection signal is at a low level. When the count value reaches “7”, the carry signal is RS
To the set terminal of the FF circuit 28b, and when the count value becomes "0", the borrow signal becomes the same as the RS-FF circuit 28b.
b is applied to the reset terminal. RS-FF circuit 28b
Outputs a high-level signal when a pulse is applied to a set terminal, and drops the output level from a high level to a low level when a pulse is applied to a reset terminal.

The D-terminal is connected to the Q terminal of the RS-FF circuit 28b.
The FF circuits 28c to 28e are serially connected. D-
A clock is applied to each of the FF circuits 28c to 28f every 3 μsec, and the D terminal input is latched by the clock. As a result, data strings are output every 3 μsec from the Q terminals of the D-FF circuits 28c to 28e. RS-F
When the output of the F circuit 28b is included, a 4-bit data string is obtained.

The output of the RS-FF circuit 28b is supplied to an AND circuit 28n via an inverter 28h, supplied to an AND circuit 28p via an inverter 28m, and supplied to the OR circuit 28q as it is. D-FF circuit 28c
Output from the AND circuit 28n and the OR circuit 28
q and A via the inverter 28k.
This is provided to ND circuit 28p. The output of the D-FF circuit 28d is used as it is by the AND circuit 28n and the OR circuit 28q.
And an inverter AN via an inverter 28j.
It is provided to D circuit 28p. The output of the D-FF circuit 28e is supplied to an AND circuit 28n via an inverter 28f, supplied to an AND circuit 28p via an inverter 28i, and supplied to the OR circuit 28q as it is.

The AND circuits 28n and 28p perform a logical AND operation on the input data, and the OR circuit 28q performs a logical OR operation on the input data. Therefore, the RS-FF circuit 28
b and the data string output from the D-FF circuits 28c to 28e becomes "0010" and the AND circuit 28
A pulse is output from n. If the data string is “000”
When the signal is "0", a pulse is output from the AND circuit 28p.
When the data string becomes "0001" or more, that is, when the numerical value represented by the 4-bit data string is "1" or more, a pulse is output from the OR circuit 28q.

As described above, the sequentially changing data string is "0".
001 "indicates that the ID signal period has started, and the OR circuit 28q outputs a high level signal, and when the data string indicates" 0000 ", the AND signal 28p indicates that the ID signal period has ended. Further, when the data string indicates "0010", a high-level signal is output, and the high-level signal is output from the AND circuit 28n assuming that the specific information has been obtained, that is, the OR circuit 28q.
Outputs an ID signal period start detection signal, and an AND circuit 28p outputs an ID signal period end detection signal.
A specific information detection signal is output from AND circuit 28n.

The down counter 28r is connected to an AND circuit 28.
The count value “6” when the output of n goes high
, And the down counter 28 s
Count value "4" when the output of p becomes high level
, And the down counter 28t loads the count value “8” when the output of the OR circuit 28q becomes high level. Each of the down counters 28r to 28t decrements the count value in response to the horizontal synchronization signal, and outputs a borrow signal, that is, reset pulses P1, P3 and P2 when the count value becomes "0".

As described above, the ID signal is superimposed on the fifteenth to eighteenth lines of the odd field and the 277 to 280 lines of the even field. On the other hand, the valid period including the video component starts from the 23rd line of the odd field and the 285th line of the even field. That is, there are eight lines between the start position of the ID signal and the start position of the valid line, and there are four lines between the end position of the ID signal and the start position of the valid period.
The specific information is added to the 17th line of the odd field and the 279th line of the even field. As a result, there are 6 lines between the specific information and the start position of the valid period. Therefore, the down counter 28r-
Numerical data "6", "4" and "8" are loaded into 28t, respectively, and the count value is decremented in response to the horizontal synchronizing signal, so that reset pulses P1, P3 and P2 at the start of the effective period. Is output. The reset pulses P1 to P3 thus obtained are given to the priority processing circuit 30.

The horizontal synchronization signal and the vertical synchronization signal output from the synchronization separation circuit 32 are also applied to an H counter 36. The H counter 36 is reset in response to a vertical synchronization signal, and is incremented in response to a horizontal synchronization signal. The count value of the H counter 30a is given to the decoder 30b, and the decoder 30b outputs a reset pulse P4 when the count value becomes "23". As can be seen from FIG. 6, when the pseudo vertical synchronization signal is correctly added, the valid period starts on the 23rd line from the start position of this signal. Therefore, when the count value becomes "23", the reset pulse P4 is output from the decoder 30b. The reset pulse P4 thus generated is also input to the priority processing circuit 30.

Referring to FIG. 4, reset pulses P1 to P
3 is input to the reset terminals of the RS-FF circuits 30a to 30c, respectively, and the same vertical signal is input to the RS-FF circuits 30a to 30c.
The signal is input to the set terminal 30c. Therefore, RS-
The outputs of the FF circuits 30a to 30c rise in response to the vertical synchronization signal, and fall in response to the corresponding reset pulse. The AND circuit 30d includes an RS-FF circuit 30a
AND of the reset pulse P2 and the output of
The D circuit 30e performs a logical product on the outputs of the RS-FF circuits 30a and 30b and the reset pulse P3, and the AND circuit 30e performs the AND operation on the RS-FF circuits 30a to 30c.
And the reset pulse P4. Further, the OR circuit 30g performs a logical sum on the reset pulse P1 and the outputs of the AND circuits 30d to 30f, and outputs a logical sum signal to the write address generation circuit 40.

For example, when reset pulses P1 to P4 are input at the timings shown in FIGS.
Reset pulses P3 and P4 are gated based on reset pulse P2. On the other hand, the reset pulse P1
It is not gated by another reset pulse.
As shown in FIG. 5E, only reset pulses P2 and P1 are output from OR circuit 30g. That is,
A reset pulse with a large coefficient has priority over a reset pulse with a small coefficient.

The write address generation circuit 40 is provided with an address counter 40a, and the write address is generated based on the count value of the address counter 40a. That is, the video signals Va to Vd are written to the memory 18 as shown in FIG. 7, and the write start address of the video signal Va is (0, 0), but the write start address of the video signals Vb to Vd is , (320,0), (0,240) and (320,240), respectively. Therefore, each write address generation circuit 40 generates a write address based on the count value of address counter 40a.

The count value of the address counter 40a is reset in response to a reset pulse output from the priority processing circuit 30. In the example of FIG. 5, two reset pulses P1 and P2 are output, and the address counter 40a is reset by both reset pulses. However, since the last output is the reset pulse P1, the write address is determined based on the reset pulse P1. That is, as long as all the reset pulses P1 to P4 are output from the ID determination circuit 28 and the decoder 38, the write address is determined based on the reset pulse P1. When only some of the reset pulses are generated, the write address is reset by the reset pulse having the largest coefficient.

The write address signal thus generated is applied to the memory 18, and the video signals Va to Vd are written at desired addresses. Note that the video signals Va to Vd
Are input to the terminals S1 to S4 at different times, and the write operations do not collide with each other. According to this embodiment, since the start position of the valid period is specified based on the ID signal superimposed on the predetermined position of the video signal, the video signal is always written into the memory from the start position of the valid period. For this reason, the image displayed on the monitor does not blur in the vertical direction. In addition, a plurality of reset pulses are processed in a predetermined priority order, and the write address is determined based on any one of the reset pulses, so that blurring can be reliably prevented.

In this embodiment, the high-level signal is output from the AND circuit 28n when the 4-bit data string becomes "0010".
"0" is a header added to the identification code of the monitoring camera. However, when the 4-bit data string indicates the identification code of the monitoring camera, a high-level signal is output from the AND circuit 28n. In this case,
It is necessary to change the arrangement state of the inverters in the preceding stage of the AND circuit 28n for each of the write controllers 16a to 16d.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a write controller.

FIG. 3 is a block diagram illustrating an ID discrimination circuit.

FIG. 4 is a block diagram illustrating a priority processing circuit.

FIG. 5 is a timing chart showing a part of the operation of the priority processing circuit.

FIG. 6 is an illustrative view showing one portion of a composite video signal;

FIG. 7 is an illustrative view showing a memory;

FIG. 8 is a block diagram showing a conventional technique.

FIG. 9 is an illustrative view showing one portion of an operation in the related art;

FIG. 10 is an illustrative view showing another portion of the operation of the related art;

FIG. 11 is a waveform chart showing another part of the operation of the conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Multiplexer 16a-16d ... Write controller 18 ... Memory 26 ... ID detection circuit 28 ... ID discrimination circuit 30 ... Priority processing circuit 40 ... Write address generation circuit

Claims (8)

(57) [Claims] An identification signal for each camera is provided in a video signal processing circuit for processing a video signal provided at a first predetermined position in each field, a detection means for detecting the identification signal, and a detection signal based on the detected identification signal. A video signal processing circuit comprising: a specifying unit that specifies a predetermined position of the video signal; a writing unit that writes the video signal from a predetermined position to a memory; and a reading unit that reads a video signal written to the memory. 2. The method according to claim 1, wherein the identification means includes specific information detection means for detecting specific information in the identification signal, and a first counter for counting the number of lines based on the detection time of the specific information and outputting a predetermined position. The video signal processing device according to claim 1. 3. The method according to claim 2, wherein the identification means includes a start position detection means for detecting a start position of the identification signal, and a second counter for counting the number of lines based on the detection time of the start position and outputting a predetermined position. The video signal processing device according to claim 1. 4. The identification means includes end position detection means for detecting the end position of the identification signal, and a third counter for counting the number of lines based on the detection time of the end position and outputting a predetermined position. The video signal processing circuit according to the above. 5. A specific information detecting means for detecting specific information in an identification signal, a first counter for counting the number of lines based on a detection time of the specific information and outputting a predetermined position, a starting position of the identification signal Position detection means for detecting the start position, a second counter for counting the number of lines based on the detection time of the start position and outputting a predetermined position, end position detection means for detecting the end position of the identification signal, and detecting the end time of the end position. 2. The video signal processing circuit according to claim 1, further comprising a third counter that counts the number of lines based on a reference and outputs a predetermined position, and a selection unit that selects a predetermined position output by each counter in a predetermined order. 6. The video signal processing circuit according to claim 5, wherein said writing means includes reset means for resetting a write address of a memory in accordance with a predetermined position output from said selection means. 7. The video signal processing circuit according to claim 1, wherein the predetermined position is a start position of an effective component of the video signal. 8. A surveillance camera system comprising the video signal processing circuit according to claim 1.