JP3333861B2 - Digital / analog conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog conversion circuit connected downstream of a digital signal processing circuit in digital audio equipment.

[0002]

2. Description of the Related Art Generally, a digital / analog conversion circuit of this kind converts a sampling value output data of each sampling point of a digital signal processing circuit into a ladder resistance type digital / analog conversion circuit.
The analog converter converts the signal into an analog signal (analog staircase wave, pulse width modulation wave, etc.) and passes the analog output signal through an LPF (low-pass filter) to remove high-frequency components.

[0003] Techniques such as oversampling have been introduced to reduce the load on the LPF, and to suppress a decrease in auditory sound quality due to the LPF.

[0004]

However, in the conventional digital / analog conversion circuit, since the output waveform is a staircase wave as shown in FIG. 4, it is difficult to sufficiently improve the auditory sound quality. Was.

[0005] The present invention solves the above problems and provides an LPF.
It is an object of the present invention to provide a digital / analog conversion circuit which can extremely reduce the burden on the user or can omit the LPF and can sufficiently improve the auditory sound quality.

[0006]

Means for Solving the Problems In order to solve the above problems,
A digital / analog conversion circuit according to the present invention includes: a difference calculation circuit that calculates a difference value between sampling value data of adjacent sampling points based on sampling value output data of each sampling point of a digital signal processing circuit; A ladder resistance type first digital / analog converter for converting the difference value output data of the arithmetic circuit into an analog current, and a ladder resistance type for converting the sampling value output data at each sampling point of the digital signal processing circuit into an analog voltage. A second digital / analog converter, a current integration circuit connected to an output side of the first digital / analog converter, an output side of the second digital / analog converter, and an input side of the current integration circuit. And an analog switch for conducting / cutting off the analog switch. The second digital / analog converter is turned on to apply the analog output voltage of the second digital / analog converter to the current integration circuit. Thereafter, the current integration circuit is charged / discharged with the analog output current of the first digital / analog converter. It is characterized by having comprised so that it might be.

[0007]

According to the digital / analog conversion circuit according to the present invention, the output waveform of the current integration circuit has a continuous waveform component formed by connecting the sampling values of adjacent sampling points with a straight line. In other words, since the output waveform of the current integration circuit is a smooth analog waveform, it is possible to obtain an analog output waveform on which high-frequency components are not superimposed. For this reason, the burden on the LPF at the subsequent stage can be reduced, and the auditory sound quality can be improved.
The LPF can be omitted.

In the output waveform of the current integration circuit,
The waveform component corresponding to each sampling period is the analog output voltage of the second digital / analog converter, in other words,
Since it is always formed so as to include the sampling value output data of the digital signal processing circuit, the analog output current of the first digital / analog converter is small, the voltage change amount of the current integration circuit is small, and the DC level is small. It is possible to sufficiently reproduce signals in a low frequency range including the signals.

[0009]

An embodiment of the present invention will be described below with reference to the drawings.

The digital / analog conversion circuit according to this embodiment includes a digital section 1 (FIG. 1A) connected to an output side of a known digital signal processing circuit (not shown) and an output side of the digital section 1. And a digital / analog conversion unit 2 (FIG. 1 (B)).

Digital Unit 1 (FIG. 1A) The digital unit 1 is provided with each sampler of the digital signal processing circuit.
Based on the sampling value output data S at the
Sampling value data S of sampling point_n, S _n-1 Among
Difference value data △ S_n And a difference calculation circuit 3 for calculating
You.

The difference calculation circuit 3 includes a first register 4 of SIPO (serial-in / parallel-out) type, a first bit inverter 5, a second register 6 of SIPO type, a first adder 7, and a second adder 8. , PISO (parallel-in / serial-out) type third register 9 and timing generator 1
0.

[0013] The first register 4, the sampling value output data S _n of the digital signal processing circuit is excisional.

A first bit inverter 5, the output data S _n in the first register 4 bits inverted to create a complement to the "1" of the sampled value data S _n in the first register 4.

In the second register 6, when the sampling value data _Sn is set in the first register 4, the output data _{Sn-1 of} the first bit inverter 5, that is, the data previously set in the first register 4 is set. ₁ of sampling value data _Sn- 1
Is set.

The first adder 7 generates the complement of 2 stored data in the second register 6 by setting the carry input terminal of the least significant digit full adder to 1.
From the stored data _Sn of the second register 6, subtracting the one's complement of the sampled value data _Sn-1 in the second register 6 to obtain the difference value data _{ S _} between the sampled value data Sn and Sn _-1 at adjacent sampling points. Calculate _n .

The second adder 8 adds an offset value O to the difference value output data △ S _n of the first adder 7. Here, the offset value O is always set to a value that satisfies △ S _n + O> 0, and the first digital / analog converter 12 described later
To prevent the occurrence of zero cross distortion.

The third register 9 stores the difference value data _{ S _n
And the offset value O are set, and the addition value data A is serially input to the first digital / analog converter 12 (FIG. 1B).

On the serial output side of the second register 6 of the difference calculation circuit 3, the sampling value S of the second register 6
_A second bit inverter 11 is connected to reduce the one's complement of _n-1 to the sampling value output data S _n-1 of the digital signal processing circuit. The output data of the second bit inverter 11, that is, the sampling value data _Sn-1 is input to the second digital / analog converter 13 (FIG. 1B).

The timing generator 10 outputs a timing signal to each of the first, second, and third registers 4, 6, and 9, thereby enabling the calculation and output of the addition value data A as described above. The output timing of the sampling value data _{Sn-1 and} the output timing of the addition value data A are synchronized. Further, the timing generator 10 is connected to an analog switch 14 (FIG. 1B) described later.
And outputs a control signal CS for controlling the switch operation of.

Digital / Analog Converter 2 (FIG. 1B) The digital / analog converter 2 includes a difference calculation circuit 3 (FIG. 1).
A ladder resistance type first digital / analog converter 12 for converting the added value output data A of (A)) into an analog current is provided. A ladder resistance type second digital / analog converter 13 for converting the sampling value output data _Sn-1 of the second bit inverter 11 (FIG. 1A) into an analog voltage.
Is provided.

On the output side of the first digital / analog converter 12, a current integration circuit 15 composed of a capacitor is connected.

An analog switch for switching between the output side of the second digital / analog converter 13 and the input side of the current integration circuit 15 in accordance with a control signal CS from the timing generator 10 to conduct / cut off between them. 14 is provided, and the analog switch 14 is turned on for a very short time from the start of sampling at each sampling cycle.
The analog output voltage of the second digital / analog converter 13 is applied to the current integration circuit 15.

A current amplification circuit 16 is provided between the first digital / analog converter 12 and the current integration circuit 15. The current amplification circuit 16 includes a transistor 17 for holding the output potential of the first digital / analog converter 12 at the ground potential, and transistors 18 and 19 as constituent elements.

At the connection point between the current amplifying circuit 16 and the current integrating circuit 15, the current corresponding to the offset value O is reduced from the analog output current of the first digital / analog converter 12, and the difference value data ΔS _n Is connected to the first constant current source 20 for causing a current corresponding to only to flow through the current integration circuit 15.

Between the second digital / analog converter 13 and the analog switch 14, there is provided a zener diode 21 for lowering the analog output voltage of the second digital / analog converter 13 by a predetermined voltage value. A second constant current source 22 for bias is connected to the anode side of the Zener diode 21.

The output side of the current integration circuit 15 is connected to the base of the transistor 24 of the buffer circuit 23.
The LPF 25 is connected to the output side of the buffer circuit 23.

Since the digital / analog conversion circuit of this embodiment has the above-described configuration, the difference calculation circuit 3 of the digital section 1 uses the sampling value output data S _n and S _n−1 of the digital signal processing circuit. The difference value data △ S _n is calculated, the offset value O is added to the difference value data △ S _n to generate addition value data A, and the addition value data A is converted into the first digital / analog data of the digital / analog conversion unit 2. It outputs the sampling value data _Sn-1 to the second digital / analog converter 13 in synchronization with the output timing of the addition value data A.

The added value data A is converted into an analog current by the first digital / analog converter 12, while the sampling value data S _n-1 is converted into an analog voltage by the second digital / analog converter 13. . This analog voltage is applied to the current integration circuit 15 when the analog switch 14 is on, that is, for a very short time from the start of sampling. On the other hand, the analog current is a current from which the offset value O has been canceled. The circuit 15 is charged and discharged. Therefore, the output voltage of the current integration circuit 15 is
As shown in FIG. 2, the waveform does not change stepwise but approximates an analog waveform in which adjacent sampling points t _1, ..., T ₉ are connected by a straight line. When the DC level signal is reproduced, the output voltage of the current integration circuit 15 is held at an analog voltage value corresponding to the sampling value data Sn _-1 based on the ON operation of the analog switch 14, as shown in FIG. Become like Since the output voltage of the current integration circuit 15 controls the base voltage of the transistor 24 of the buffer circuit 23, a voltage corresponding to the output voltage of the current integration circuit 15 is output from the buffer circuit 23 and input to the LPF 25. You.

As is apparent from the above description, according to the digital / analog conversion circuit of this embodiment, the output waveform of the current integration circuit 15 is formed by connecting the sampling values of adjacent sampling points with a straight line. Since the waveform components are continuous, in other words, the output waveform of the current integration circuit 15 is a smooth analog waveform, an analog output waveform on which no high-frequency component is superimposed can be obtained. For this reason, the burden on the LPF 25 at the subsequent stage can be reduced, the sound quality in hearing can be improved, and the LPF 25 can be omitted.

The waveform component corresponding to each sampling period in the output waveform of the current integration circuit 15 is the analog output voltage of the second digital / analog converter 13, in other words, the sampling value output data of the digital signal processing circuit, , The analog output current of the first digital / analog converter 12 is small, and the voltage change amount of the current integration circuit 15 is small.
Even a signal in a low frequency range including a DC level can be sufficiently reproduced.

Further, since an offset value is added to the difference value data and input to the first digital / analog converter 12, zero cross distortion of the first digital / analog converter 12 can be prevented.

In the above embodiment, the processing of adding the offset value is not performed for the sampling value data. However, if the addition processing is performed, the second value can be obtained.
Zero cross distortion of the digital / analog converter 13 can also be prevented.

[Brief description of the drawings]

FIG. 1 shows a digital / analog conversion circuit according to one embodiment, wherein (A) is a configuration diagram of a digital unit, and (B) is a configuration diagram of a digital / analog conversion unit.

FIG. 2 is an output waveform diagram of a current integration circuit of a digital / analog conversion unit.

FIG. 3 is an output waveform diagram of a current integration circuit when a DC level signal is reproduced.

FIG. 4 is an output waveform diagram of a digital / analog conversion circuit in a conventional example.

[Explanation of symbols]

 3 Difference Operation Circuit 12 First Digital / Analog Converter 13 Second Digital / Analog Converter 14 Analog Switch 15 Current Integration Circuit

Claims (1)

(57) [Claims] 1. A difference calculation circuit for calculating a difference value between sampling value data of adjacent sampling points based on sampling value output data of each sampling point of a digital signal processing circuit, and a difference value output circuit of the difference calculation circuit. A first digital / analog converter of a ladder resistance type for converting data into an analog current; a second digital / analog of a ladder resistance type for converting the sampling value output data at each sampling point of the digital signal processing circuit into an analog voltage A converter, a current integration circuit connected to an output side of the first digital / analog converter, and an analog for conducting / cutting off an output side of the second digital / analog converter and an input side of the current integration circuit. A second switch for turning on the analog switch for a very short time every sampling period. / The analog output voltage of the analog converter is applied to the current integrator circuit, thereafter,
A digital / analog conversion circuit, wherein the current integration circuit is charged and discharged with the analog output current of the first digital / analog converter.