JP3335653B2 - Zero detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting a zero of an addition / subtraction result of a digital adder / subtracter.

[0002]

2. Description of the Related Art Conventionally, whether or not the result of an operation such as addition and subtraction is zero can be obtained as a result of calculating the inverted OR of all the bits as a result of the operation.

FIG. 8 is a block diagram of a zero detecting circuit for explaining this conventional method. The arithmetic unit 31 receives n-bit binary numbers A and B and outputs n-bit data. The inverted OR circuit 32 takes the inverted OR of all the bits of the output of the arithmetic unit 31. Thus, if the operation result is zero, the zero signal Z becomes 1, and if the result is not zero, the zero signal Z
Becomes 0.

[0004]

However, in the conventional zero detection circuit, since the zero is detected after the operation result is obtained, the zero signal is obtained only after the operation result is obtained.
There was a disadvantage that it took time to obtain a result. In addition, addition and subtraction, in particular, takes a long calculation time due to propagation of carry, and further adds zero detection time, thereby increasing the total calculation time.

In the case of subtraction, if the two numbers are equal, the result is zero. Therefore, it can be substituted by checking whether or not the exclusive OR of each bit of the two numbers is zero. However, in the case of addition, when the two numbers have a two's complement relationship, the result is zero. However, means for examining the two's complement relationship is required.

An object of the present invention is to provide a circuit for directly obtaining a zero detection signal indicating whether the result of addition / subtraction of two numbers is zero from two numbers.

[0007]

SUMMARY OF THE INVENTION The first invention is a zero detection circuit 2 number of addition and subtraction result of any bit is detected whether zero or divides the number 2 to the upper part and lower part, before
In the upper part, there is no carry from the lower part
In this case , a zero signal (first zero) indicating whether the result of addition / subtraction is zero or not.
Signal) and carry signal (1st carry signal)
Signal, and a zero signal (second zero signal) when there is a carry.
No.) and obtains a carry signal (second carry-signal), the lower
When there is no carry from the lower part in the part,
Zero signal (third zero signal) and carry signal (third carry signal)
Signal) and a zero signal (the fourth zero signal) when there is a carry.
Signal and carry signal (fourth carry signal).
If there is no carry signal when there is no carry signal from the lower part of the part (third carry signal = 0) , a zero signal (first zero signal) when there is no carry from the lower part of the upper part And before
Zero signal in the case where there is no carry signal from the lower of the serial sub-parts
The logical product of the (third zero signal) is defined as a zero signal (fifth zero signal) when there is no carry from the lower part of the result of addition / subtraction of the two numbers,
Carry signal in the absence of the carry signal of the carry signal in the absence of carry (the first carry-signal) from the further lower of the two numbers of addition and subtraction result from the lower portion of the upper portion
(Fifth carry signal) and there is no carry signal when there is a carry signal from the lower part of the lower part (fourth carry signal).
No. = 0), zero signal (fourth zero signal when there is a carry signal from the lower zero signal (first zero signal) and the lower portion in the absence of a carry from the lower of the upper portion the logical product of) a zero signal when there is a carry from the lower of the two numbers addition and subtraction result (sixth zero signal), in the absence of a carry from the <br/> lower portion of the upper portion Carry signal (first digit
Carry signal) when there is a carry signal from the lower order of the result of addition / subtraction of the two numbers (sixth carry signal).
When there is a carry signal when there is no carry signal from the lower part of the lower part (third carry signal = 1) , a zero signal when there is a carry from the lower part of the upper part (No.
2 zero signal) and the zero signal in the case where there is no carry signal from the lower of the lower portion (third zero signal) zero signal in the absence of a carry a logical product from the lower of the two numbers addition and subtraction result of ( Fifth
A zero signal), the carry signals when there is a carry from the lower portion of the upper portion (second carry-signal) 2
A carry signal (fifth carry signal) when there is no carry signal from the lower part of the result of addition / subtraction of a number is a carry signal when there is a carry signal from the lower part of the lower part. is there
(Fourth carry-signal = 1) case, zero signal when there is a carry signal from the lower zero signal (second zero signal) and the lower part of the case where there is a carry from the lower of the upper portion (No.
The logical product of 4 zero signals is calculated from the lower order of the result of addition and subtraction of the two numbers
Zero signal when there is a carry (Sixth zero signal), and the upper portion of the carry signal (first carry-signal) when there is a carry from the lower portion of the 2 number of addition and subtraction result Sa
The carry signal in the case of La there is a carry signal from the lower (the
(6 digit carry signal) .

According to a second aspect of the present invention, there is provided a zero detecting circuit for detecting whether or not a result of addition and subtraction of two arbitrary bits is zero.
Dividing the number in the upper portion and lower portion, said upper portion smell
A zero signal (first zero signal) indicating whether the result of addition / subtraction is zero, a carry signal (first carry signal) indicating the presence or absence of a carry, when there is no carry from the lower part ; And digits
When there is up, obtains a zero signal (second zero signal), the
When there is no carry from the lower part in the lower part
Signal (third zero signal) and carry signal (third carry signal)
Signal) and a zero signal (the fourth zero signal) when there is a carry.
), And if there is no carry signal when there is no carry signal from the lower part of the lower part (third carry signal = 0) , zero if there is no carry from the lower part of the upper part. signal wherein a logical product of (first zero signal) and the zero signal in the absence of a carry signal from the lower of the lower portion (third zero signal) 2
Zero signal when there is no carry from the bottom of the result of adding or subtracting numbers
(Fifth zero signal), and there is no carry signal from the further lower the upper portion of the case there is no carry from the lower part carry signal (first carry-signal) the 2 number of addition and subtraction result If the carry signal from the lower part of the lower part does not exist (third carry signal = 1) , the lower part of the upper part is used as the carry signal (fifth carry signal). zero signal when there is a carry from the (second zero signal) and the zero signal (third zero signal) when there is no carry signal from the lower sub-portions ANDing the two numbers addition and subtraction result of a zero signal in the case where there is no carry from the lower (5 zero signal), the carry signal in the case where there is no carry signal from the lower of the two numbers of addition and subtraction results (fifth carry-signal) and a logic 1 ,
Smell if there is a carry signal from the lower of the lower part
Te is the logical product of the zero signal when there is a carry from the lower of the upper portion (second zero signal) and the zero signal in the case where there is a carry signal from the lower of the lower portion (fourth zero signal) Is a zero signal (sixth zero signal) when there is a carry from the lower part of the result of addition and subtraction of the two numbers.

A zero detection circuit according to a third invention is characterized in that, in the first invention or the second invention, two zero signals obtained by dividing two arbitrary bits into upper and lower bits are obtained.

[0010] A zero detection circuit according to a fourth aspect of the present invention comprises a 1-bit 2
The exclusive OR of the numbers is a zero signal when there is no carry from the lower order, the exclusive OR of the two numbers is a zero signal when there is a carry from the lower order, and one of the two numbers is a digit. It is characterized by detecting whether or not the result of 1-bit addition / subtraction is zero by using an up signal.

According to a fifth aspect of the present invention, there is provided a zero detection circuit for detecting whether or not the result of addition and subtraction of two 1-bit numbers is zero. , The exclusive-OR of the two numbers is used as the zero signal when there is a carry from the bottom, one of the two numbers is used as the carry signal, and the subtraction of the two numbers is used in subtraction. It is characterized in that the logical inversion logical sum is set to a zero signal and the carry signal is set to no carry.

[0012]

In order to detect whether or not the result of addition / subtraction of two n-bit numbers is zero, the carry signal propagates from the least significant bit to the most significant bit in the worst case during the operation.
The calculation time becomes longer. With two numbers shorter than n bits, the number of propagation stages of the carry signal becomes shorter, so that the calculation time can be reduced. Therefore, the n bits are divided into the upper nh bits and the lower nl bits, and it is detected whether or not the respective addition / subtraction results are zero. Since both the nh bit and the nl bit are shorter than n bits, the detection can be performed in a shorter time than the zero signal resulting from the n-bit addition / subtraction.

Next, from each of the divided zero signals, n
Find the zero signal for all bits. For that purpose, it is necessary to prepare two types of zero signals of the upper nh bits, with and without a carry signal from the lower order. Also, a carry signal indicating whether or not to carry in addition and subtraction of the lower nl bits is required. If there is no lower carry signal, a zero signal without a carry from the lower one is selected from the upper two kinds of zero signals. It is sufficient that the zero signal in the addition / subtraction of is also 1. If there is a lower carry signal, select the zero signal when there is a carry from the lower side as the upper zero signal. It is sufficient to set it to l. Otherwise, the overall zero signal is zero.

In order to detect that the result of addition / subtraction of the divided nh bits and nl bits is zero, the signal is further divided into shorter bits, and a zero signal can be obtained by the same method. By repeating this, eventually, everything can be divided into one bit. In the case of 1-bit addition, if there is no carry from the low order, the result is 0 when both numbers are 0 or 1, and if there is a carry from the low order, one of the two numbers is 1 and the other is 0. Sometimes the result is 0
Becomes Therefore, it can be obtained with a simple logic gate. These results are combined two bits at a time, a zero signal for addition and subtraction of two bits is obtained, and further two are combined to perform zero detection of an arbitrary bit.

As described above, in order to combine, not only a zero signal as a result of addition and subtraction but also a carry signal is required. In the case of 1-bit addition / subtraction, when the carry from the lower order is 0, the two numbers are zero when both are 1 or 0. Therefore, the carry signal is 1 when both 2 are 1 and 0 when both are 0.
It is good. If the numbers are 1 and 0, the zero signal is 0
Since the upper zero signal becomes 0 when combined in any case, the carry signal does not have to be correct. Therefore, it is sufficient to use one of the two numbers as the carry signal. If there is a carry from the lower part, the zero signal becomes 1 when the two numbers are 1 and 0. Therefore, if the lower carry is added, a carry signal is also generated from this bit. When the two numbers are both 1 or 0, the zero signal becomes 0, but there is no need to find the correct carry signal as in the case where there is no carry signal. Therefore, the carry signal in this case should always be 1. These can be summarized as follows. The input two numbers are a and b, and the zero signal is Z
0, Z1 and carry signals C0, C1. When the last character is 0, the value when the carry from the lower bit is 0 is the value, and when the last character is 1, the value when the carry from the lower bit is 1 is the value. ＾ is an exclusive OR and 〜 is an operator representing bit inversion. Z0 = 〜 (a ＾ b) (1) Z1 = a ＾ b (2) C0 = a (or b) (3) C1 = 1 (4).

When the combination is repeatedly performed, a zero signal and a carry signal after the combination must be generated. In order to consider the presence / absence of a carry from the lower part of the combined zero signal, two kinds of signals with and without the carry from the lower part are prepared and used for the combined lower zero signal. That can be dealt with. This can be summarized as follows. ZL0 (third zero signal) , ZL1
(4th zero signal) , lower carry signal CL0 (3rd digit upper
Signal , CL1 (fourth carry signal) , upper zero signal ZH0 (first zero signal) , ZH1 (second zero signal) , higher carry signal CH0 (first carry signal) , CH1 (Second
Carry signal) , the combined zero signal as Z0 (fifth zero signal) ,
Z1 (6th zero signal) , carry signal C0 (5th carry signal)
) , C1 (sixth carry signal) . However, when the last character is 0, the value when the carry signal from the lower order is 0, and when it is 1, the value when the carry signal from the lower order is 1 is the value. & Is a logical product, | is a logical sum, and ~ are operators representing bit inversion.

Z0 = ZL0 & ((＆ CL0 & ZH0) │ (CL0 & ZH1)) (5) Z1 = ZL1 & ((〜CL1 & ZH0) │ (CL1 & ZH1)) (6) C0 = (〜CL0 & CH0) │ (CL0 & CH1) (7) C1 = (~ CL1 & CH0) | (CL1 & CH1) (8) Equations (5) and (6) are used when there is no carry signal from the lower part and when there is no carry from the lower part of the upper zero signal, This means that when there is a carry signal, the signal with no carry from the lower order is selected from the upper zero signals and the logical product with the lower zero signal is taken. The lower zero signal and the carry signal used here are the values in the case where there is no carry from the lower order, and the expression (5) is used, and the values in the case where the carry is used are (6). It is an expression. Regarding the carry signal, if there is no carry signal from the lower position, among the upper carry signals, the signal without the carry from the lower position, and if there is the carry signal from the lower position, the upper carry signal. Select the signal with a carry from the bottom among the signals. Equation (7) uses a value when there is no carry from the low order, and Equation (8) uses a value when there is a carry. These four equations allow the generation of the zero signal and the carry signal in the connector block.

As can be seen from equation (4), the value of C1 is always 1, so that the subsequent selector is always fixed when there is a carry. When the equations (6) and (8) are rewritten in consideration of this, Z1 = ZL1 & CL1 (6 ′) C1 = CH1 = 1 (8 ′) As described above, when the carry from the lower order is 1, the carry signal is 1, and therefore this signal is not necessary at the time of coupling.

[0019]

Next, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows an embodiment of the present invention. The two bits A and B of n bits are converted to AH and B of upper nh bits.
It is divided into H and lower nl bits AL and BL. AH, B
H is input to the nh-bit zero detection circuit 2 and the zero signal ZH0,
ZH1 and carry signals CH0 and CH1 are generated. At the same time, the nl-bit zero detection circuit 3 is used to generate zero signals ZL0 and ZL1 and carry signals CL0 and CL1 from AL and BL. Using these signals, the combined zero signals Z0, Z1 and carry signals C0, C1 are generated by a zero detection signal combining circuit 1 which is a circuit that realizes the equations (5) to (8).
Here, Z0 is a zero signal of A + B, and Z1 is a zero signal of A + B + 1. The subtraction is performed by inverting B bit by bit to ~ B,
+ (ら れ る B) +1, so that Z1 may be a zero signal.

FIG. 2 is a diagram showing an example of the configuration of the zero detection signal synthesizing circuit 1. The processing of the expression (5) is performed by the selector circuit 21 and the AND circuit 25, and the selector circuit 23 and the AND circuit 26 are processed.
Performs the processing of equation (6), the processing of equation (7) by the selector circuit 22, and the processing of equation (8) by the selector circuit 24.

FIG. 3 is a diagram showing a one-bit zero detection circuit according to another embodiment of the present invention. 1-bit two numbers a,
b, zero signal Z when there is no carry from the bottom
The value 0 is obtained from the exclusive OR circuit 11 of a and b, and the zero signal Z1 when there is a carry from the lower order is obtained from the exclusive OR circuit 12 of a and b. C0 outputs a as it is as shown in equation (3). Further, as shown in the equation (4), C1 is set to 1 by using the logic 1 output circuit 13.

FIG. 4 shows still another embodiment of the present invention. According to the equations (6 ') and (8'), the carry signal is always 1 when there is a carry signal from the lower order, so that the selector circuits 23 and 24 controlled by the signal are carried out.
Is fixed and its value is unnecessary. Also, this carry signal is unnecessary. Therefore, as shown in FIG. 1, four signals are not required, and a total of three signals of two zero signals and one carry signal may be used. Therefore, FIG. 4 shows a zero detection signal synthesizing circuit 4 and an nh bit zero detection circuit 5 which perform processing with three signals.
And an nl-bit zero detection circuit 6.

FIG. 5 is a diagram showing an example of the configuration of the zero detection signal synthesizing circuit 4. The selector circuit 21 and the AND circuit 25 perform the processing of the expression (5), the AND circuit 26 performs the processing of the expression (6 ′), and the selector circuit 22 performs the processing of the expression (7). Since the carry signal when the carry signal from the lower order is 1 is unnecessary, there is no portion corresponding to the processing of equation (8). Further, since there is no carry signal CH1 from the divided block, the logic 1 output circuit 27 is used instead.

FIG. 6 shows still another embodiment. Since there is no need for a carry signal when there is a carry from the bottom,
The output of C1 is deleted as compared with FIG.

FIG. 7 shows still another embodiment. As an input, o is added as a control signal in addition to 1-bit two numbers a and b. When generating a carry signal, a may be output as it is for addition, and a and b may be used for subtraction.
Since it is sufficient to detect whether or not the signals match, the signal of Z0 which becomes 1 at that time may be selected. Therefore, the carry signal is fixed to 0 so that Z0 is always selected. The above processing can be performed by giving 1 to the input o and 0 to the subtraction. If this zero signal detector is used, a zero detection circuit corresponding to both addition and subtraction can be made.

[0027]

According to the zero detection circuit of the present invention, a zero signal indicating whether or not the result of addition / subtraction is zero can be directly obtained from the given two numbers. By providing in parallel with the arithmetic unit, zero detection can be performed in parallel with the arithmetic unit. Therefore, the speed of the entire arithmetic unit can be increased. In addition, in the case of the number of bits of a power of 2, since the same circuit can be used more than once because it can be divided exactly into half,
Design is easy.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a zero detection circuit of the present invention.

FIG. 2 is a diagram illustrating a zero detection signal synthesis circuit.

FIG. 3 is a diagram showing an embodiment of a 1-bit zero detection circuit of the present invention.

FIG. 4 is a diagram showing another embodiment of the zero detection circuit of the present invention.

FIG. 5 is a diagram illustrating another zero detection signal synthesis circuit.

FIG. 6 is a diagram showing another embodiment of the one-bit zero detection circuit of the present invention.

FIG. 7 is a diagram showing an embodiment of another 1-bit zero detection circuit of the present invention.

FIG. 8 is a diagram illustrating an example of a conventional zero detection circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 zero detection signal synthesis circuit 2 nh bit zero detection circuit 3 nl bit zero detection circuit 4 zero detection signal synthesis circuit 5 nh bit zero detection circuit 6 nl bit zero detection circuit 11 exclusive inverted OR circuit 12 exclusive OR circuit 13 Logical 1 output circuit 14 Logical OR circuit 21 Selector 22 Selector 23 Selector 24 Selector 25 Logical product circuit 26 Logical product circuit 27 Logical 1 output circuit 31 Operation unit 32 Inverted logical OR circuit

Claims (3)

(57) [Claims] 1. A zero detection circuit for detecting whether a result of addition / subtraction of two numbers of an arbitrary bit is zero is to extract two bits of each bit constituting the two numbers and divide them into upper bits and lower bits. A zero signal (first zero signal) indicating whether or not the result of addition / subtraction is zero when the upper bits of each of the two numbers are input and there is no carry from the lower bit in the upper bits And a carry signal indicating the presence or absence of a carry (first
A carry signal), an upper bit zero detection circuit for obtaining a zero signal (second zero signal) and a carry signal (second carry signal) when there is carry, and the lower bit of each of the two numbers A zero signal (third zero signal) and a carry signal (third carry signal) when there is no carry from the lower bits in the lower bits, and A lower bit zero detection circuit for obtaining a zero signal (fourth zero signal) and a carry signal (fourth carry signal); and When there is no carry, the zero signal (first zero signal) indicating whether the result of addition and subtraction is zero, the carry signal (first carry signal) indicating the presence / absence of carry, and the carry In some cases, the zero signal (second zero signal) and the carry signal (The second carry signal) and the zero signal (third zero signal) and the carry signal (the third carry signal) when there is no carry from the lower bit in the lower bits from the lower bit zero detection circuit. A third carry signal) and the zero signal (fourth zero signal) and the carry signal (fourth carry signal) when there is carry, and carry from the lower part of the lower part When there is no carry signal in the absence of a signal (third carry signal = 0), the zero signal (first zero signal) in the absence of carry from the lower part of the upper part and the lower part of the lower part The logical product of the zero signal (third zero signal) when there is no carry signal from the lower part is the zero signal (fifth zero signal) when there is no carry from the lower part of the result of addition and subtraction of the two numbers. A carry signal (no. 1 carry signal) as a carry signal (fifth carry signal) when there is no carry signal from the lower part of the result of addition and subtraction of the two numbers, and when there is a carry signal from the lower part of the lower part. When there is no carry signal (fourth carry signal = 0), the zero signal (first zero signal) when there is no carry from the lower part of the upper part and the carry signal from the lower part of the lower part are two. The logical product of the zero signal (fourth zero signal) in a certain case is defined as a zero signal (sixth zero signal) when there is a carry from the lower part of the result of addition and subtraction of the two numbers, and The carry signal when there is no carry (first carry signal) is the carry signal when there is a carry signal from the lower order of the result of addition and subtraction of the two numbers (sixth carry signal). There is a carry signal when there is no carry signal from the lower part (third carry signal) = 1) case, zero signal (second zero signal when there is a carry from the lower of the upper portion)
The logical product of the zero signal (third zero signal) when there is no carry signal from the lower part of the lower part and the zero signal (fifth zero signal) when there is no carry from the lower part of the addition / subtraction result of the two numbers ), A carry signal (a second carry signal) when there is a carry from the lower part of the upper part, and a carry signal when there is no carry signal from the lower part of the result of addition and subtraction of the two numbers. (Fifth carry signal), and if there is a carry signal when there is a carry signal from the lower part of the lower part (fourth carry signal = 1), the carry from the lower part of the upper part is The logical product of a zero signal (second zero signal) in a certain case and a zero signal (fourth zero signal) in the presence of a carry signal from the lower part of the lower part is carried from the lower part of the result of addition and subtraction of the two numbers. If there is a zero signal (sixth zero signal), the lower part of the upper part Zero to carry signal when there is a carry carry signal when a (second digit on up signal) is carry signal from the further lower of the two numbers of addition and subtraction result (sixth carry-signal) A zero detection circuit comprising a detection signal synthesis circuit. 2. A zero detection circuit for detecting whether a result of addition / subtraction of two numbers of an arbitrary bit is zero, extracting two bits of each bit constituting the two numbers, and dividing the bits into upper bits and lower bits A zero signal (first zero signal) indicating whether or not the result of addition / subtraction is zero when the upper bits of each of the two numbers are input and there is no carry from the lower bit in the upper bits And a carry signal indicating the presence or absence of a carry (first
A carry signal) and an upper bit zero detection circuit for obtaining a zero signal (second zero signal) when there is a carry; and the lower bits of each of the two numbers are input. The zero signal (third zero signal) and the carry signal ( third carry signal) when there is no carry from the lower order, and the zero signal (fourth zero signal) when there is a carry. A lower bit zero detection circuit to be obtained; and a zero signal (first signal) indicating whether or not the result of addition and subtraction is zero in the upper bits from the upper bit zero detection circuit when there is no carry from the lower bit. Zero signal) and the carry signal (first carry signal) indicating the presence or absence of carry, and the zero signal (second zero signal) when there is carry, and the lower bit zero detection circuit. In the lower bits, In the absence of a carry, the zero signal (third zero signal) and the carry signal (third carry signal), and, when there is a carry, the zero signal (fourth zero signal) but When there is no carry signal when there is no carry signal from the lower part of the lower part (third carry signal = 0), a zero signal when there is no carry from the lower part of the upper part ( The logical product of the first zero signal) and the zero signal (third zero signal) when there is no carry signal from the lower part of the lower part is the zero signal when there is no carry from the lower part of the result of addition and subtraction of the two numbers. (Fifth zero signal), and the carry signal (first carry signal) when there is no carry from the lower part of the upper part is no carry signal from the lower part of the result of addition / subtraction of the two numbers. Carry signal (fifth carry signal), and the carry signal from the lower part of the lower part If there is a carry signal when there is no (third carry signal = 1), a zero signal (second zero signal) when there is a carry from the lower part of the upper part and a lower signal from the lower part of the lower part The logical product of the zero signal (third zero signal) when there is no carry signal is defined as the zero signal (fifth zero signal) when there is no carry from the lower part of the result of addition and subtraction of the two numbers, and the addition and subtraction of the two numbers is performed. The carry signal (fifth carry signal) when there is no carry signal from the lower part of the result is logic 1
When there is a carry signal from the lower part of the lower part, a zero signal (second zero signal) when there is a carry from the lower part of the upper part and a carry signal from the lower part of the lower part A zero detection signal combining circuit which sets the logical product of the zero signal (fourth zero signal) in the case where there is a carry from the lower part of the result of addition and subtraction of the two numbers to the zero signal (sixth zero signal) A zero detection circuit. 3. A zero detection circuit for detecting whether addition or subtraction of an arbitrary two numbers consisting of 2 ⁿ bits is zero or not, wherein said two numbers are separated into 2 ^n-1 two bits, Into upper bits and lower bits, the upper bits are input to an upper bit zero detection circuit, the lower bits are input to the lower bit zero detection circuit, and output from the upper bit zero detection circuit, An upper bit zero signal, an upper bit carry signal, and a lower bit zero signal and a lower bit carry signal output from the lower bit zero detection circuit are input signals, and a zero signal and a carry signal are output. ^n-2 first-stage zero-signal combining circuits, wherein the second stage corresponding to the 2 higher-order bits of the 2 ^n-2 first-stage zero-signal combining circuits The upper bit zero signal and the upper bit output from the zero signal Input and preparative carry signal, the output from the zero-signal combining circuit corresponding to lower bits of the two numbers 2 ^n-2 pieces of zero signal combining circuit, and a low-order bit zero signal and a lower bit carry signal And 2 ⁿ⁻³ second-stage zero-signal combining circuits that output a zero signal and a carry signal. The N-th (N> 2) zero-signal combining circuit has 2 It consists ^nN number of zero signal combining circuit, from 2 ^nN-1 or zero signal combining circuit of the first N-1 stage corresponding to the upper bits of the two numbers of the N-1 stage of the zero signal combining circuit The high-order bit zero signal and the high-order bit carry signal output from the zero signal synthesizing circuits corresponding to the two lower bits of the ( ^2nN-1 ) N-1st zero signal synthesizing circuits. Input the low-order bit zero signal and the low-order carry signal, and output a zero signal and a carry signal. 3. The zero detection circuit according to claim 1, wherein zero is detected from a zero signal of the M-th stage zero signal synthesis circuit including the zero detection signal and a carry signal.