JP3335926B2 - Read and clear circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a read-and-clear circuit, and more particularly to a read-and-clear circuit having an automatic clear function.

[0002]

2. Description of the Related Art A conventional read and clear circuit will be described with reference to the drawings.

FIG. 3 is a block diagram of a conventional read and clear circuit, and FIG. 4 is a timing chart showing the operation of the read and clear circuit of FIG.

As a method of confirming the operation state of the peripheral circuit, there is a method in which a status signal output from the peripheral circuit is latched in a register and the value of the register is read and read by a CPU (not shown). Has been taken.

In this prior art, for example, a circuit shown in FIG. 3 is well known. This conventional technique will be described with reference to FIG.

In this prior art, a status signal 1 and a status signal 2 are set for one cycle period of an operation clock (hereinafter abbreviated as SCLK) of a peripheral circuit according to an operation state of the peripheral circuit. SCL is used for register 38 and register 45
Status signal 32, status signal 33 in synchronization with K
Are set respectively. A flip-flop (hereinafter abbreviated as FF) 48 in the synchronization processing circuit 301 is
The read signal 34 from the CPU is sampled by SCLK and synchronous processing is performed.

The FF 51 is set when detecting the fall of the read-and-signal 34 from the CPU, and its output is
It is connected to a wait control circuit 302 for the PU.

[0008] The output of the FF 54 in the wait control circuit 302 becomes a wait request signal (Wait) 55 for a read and operation from the CPU.

Next, the operation of the prior art will be described with reference to FIG.

[0010] A signal indicating that a reception error has occurred in serial communication is assigned to the status signal 33. When the read signal 34 is set by reading from the CPU, the output of the FF 48 is set in synchronization with SCLK. In FIG. 4, the setting of the FF 48 and the setting of the status signal 33 occur simultaneously. Therefore, SCLK
After one cycle, the output of the FF 54 maintains the set state, and the wait request signal 55 (the output of the FF3) is set to the CPU. Therefore, the CPU is in the wait state, and the wait is also inserted in the read signal from the CPU. The value of the status signal 33 is set in the register 45. Further, after one cycle of SCLK, the output of the FF 54 is cleared, and the value of the register 45 is set in the buffer 46. Further, after one cycle of SCLK, the register 45 is cleared. Also, by clearing the FF 54, the wait of the CPU is cleared and the read signal 34 is also cleared.

[0011]

However, this prior art has the following problems.

The first problem is that the circuit scale becomes large. The reason is that a synchronous processing circuit for synchronously processing the read signal with the operation clock of the peripheral circuit is required.

Further, when a read operation from the CPU conflicts with the set timing of the status signal, a wait control circuit for outputting a wait request signal to the CPU is required.

[0014] The second problem is that the performance of the CPU is reduced. The reason is that when the read from the CPU and the set timing of the status signal conflict, it is necessary to insert a wait for the CPU operation.

An object of the present invention is to provide a read-and-clear circuit which solves the above problems.

That is, the read-and-clear circuit according to the present invention performs a register read operation and sets an automatic clear signal only for a register whose read value is "1", thereby setting the register set timing and clearing the register. This prevents the set data from being lost due to the timing conflict, and also realizes the automatic clearing of the register.

[0017]

A read-and-clear circuit according to the present invention reads a first register set by a status signal and a value of the first register by a read signal, and reads the value of the first register. A first buffer that captures the data, and an output of the first buffer and the read signal.
A logic circuit for performing an AND operation with a clear timing signal indicating that the CPU has read the value of the first register, so as to avoid conflict between the setting of the first register and the reset of the first register. Thus, the output of the logic circuit is input to the reset of the first register.

Further, the status signal of the read-and-clear circuit of the present invention may be a serial communication reception signal capable of continuous reception, and the read signal is a signal from a CPU. You can also.

Further, when the first register of the read-and-clear circuit of the present invention is at "0" level, the first
May be configured not to perform a reset operation. When the first register is at “1” level and the clear timing signal is at “1” level, the first register is configured to perform reset operation. You can also.

Further, the logic circuit of the read-and-clear circuit of the present invention may be configured to be a two-input AND circuit, and the first buffer may be configured to be a second register. it can.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a block configuration of the read-and-clear circuit according to the first embodiment of the present invention.

Referring to FIG. 1, the read and clear circuit 100 of the present invention is set at the rising edge of the status signal 1 (17), and the automatic clear signal 1 (25) is set.
And a register 12 receiving a status signal 2 (19) on the set side and receiving an automatic clear signal 2 (26) on the clear side. here,
Status signal 1 (17) and status signal 2 (1
The input signal 9) is connected to a signal output from a peripheral circuit (not shown) and indicating the operation state of the peripheral circuit.

Further, the read-and-clear circuit 100 of the present invention uses a read signal 2 from a CPU (not shown).
A buffer 13 for taking the value of the register 11 by 1;
A buffer 15 for taking in the value of the register 12 in response to a read signal 21 from the CPU;
And an AND circuit 16 that takes the logical product of the clear timing signal 23 and the automatic clear signal 18 and generates the automatic clear signal 18 by taking the logical product of the output signal 24 of the buffer 15 and the clear timing signal 23. Prepare.

Then, the clear timing signal 23 is
In this configuration, a signal indicating that the read operation of the register 11 and the register 12 has been performed by the PU is connected.

Next, the operation of the read-and-clear circuit according to the first embodiment of the present invention will be described with reference to FIG.

First, the read and clear circuit 1 of the present invention
00 is the status signal 1 depending on the operation state of the peripheral circuit.
(17) is set to "1". For example, a signal indicating that serial communication has started is assigned to the status signal 1 (17). Also, status signal 2
(19) is assigned a signal indicating that a reception error has occurred in serial communication.

The register 11 is set by the setting of the status signal 1 (17). Thereafter, when the CPU 11 reads the register 11 and sets the read signal 21, the value “1” of the register 11 is stored in the buffer 13.
And the value of the register 12 (assumed to be an initial value "0") is taken into the buffer 15, and the read data is determined. Immediately after this read, a diagnosis error occurs in serial communication, and the status signal 2 (19) is set.

When the clear timing signal 23 is set in accordance with the read operation, the register 11 is cleared to "0" by the output signal 25 of the AND circuit 14 (automatic clear signal 1). Since the read data is “0”, the output signal 26 of the AND circuit 16
(Automatic clear signal 2)
By setting the status signal 2 (19), the register 1
2 is set with data "1".

That is, a circuit (AND circuit 14 and AND circuit 16) for clearing a register with read data "1" and not clearing a register with read data "0" is added. By doing so, it is possible to avoid contention between register set timing and clear timing.

That is, when the clear timing signal is set to "1" by this read operation, the AND circuit 1
At 4, the automatic clear signal 1 is set to "1", and the AND circuit 16 does not set the automatic clear signal 2. Thus, the value of the register 11 whose read value is "1" is automatically cleared by the automatic clear signal 1, but the automatic clear signal 2 is not set in the register 12 whose read value is "0".

As a result, the clear timing signal and the set signal of the register 12 (rising of the status signal 2)
Even when the conflict occurs, data is set in the register 12, and loss of the set data due to the conflict can be prevented.

The register 12 holds the value "1" until the next time the register is read, and the automatic clear signal 2 is set by the read operation, and the value of the register 12 is automatically cleared.

In the above description, the buffer 13 is FF
Alternatively, the buffer 15 may be configured as a flip-flop receiving the output of the FF 12.

[0034]

As described above, the first effect of the read-and-clear circuit of the present invention is that it is possible to avoid conflict between register setting and clear timing with a small circuit scale. The reason is that the automatic clearing by the read operation and the conflict between the set timing and the clear timing can be avoided only by adding the result of the read data to the clear condition.

The register setting timing and C
Even when the read operation from the PU is asynchronous, a synchronous processing circuit is not required, and a wait control circuit for the CPU is not required.

A second effect of the read-and-clear circuit of the present invention is that the performance of the CPU can be improved. The reason is that there is no need to insert a wait into the CPU operation even if the read from the CPU conflicts with the set timing of the register because the synchronous processing is unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram of a read and clear circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the read and clear circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a conventional read and clear circuit.

FIG. 4 is a timing chart showing an operation of the read and clear circuit of FIG. 3;

[Description of Signs] 11, 12, 38, 45 Registers 13, 15, 39, 46 Buffers 14, 16 AND Circuits 17, 19, 32, 33 Status Signals 21, 34 Read Signals 22, 24, 40, 47 Read Data 23 Clear timing signal 25, 26 Automatic clear signal 31 SCLK 100 Read and clear circuit 301 Synchronous processing circuit 302 Wait control circuit

Continuation of the front page (56) References JP-A-10-41804 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/24

Claims (7)

(57) [Claims] A first register that is set by a status signal; a first buffer that reads a value of the first register by a read signal and captures a value of the first register; And a logical circuit for performing a logical AND operation between the output of the first register and a clear timing signal indicating that the CPU has read the value of the first register by the read signal, wherein the first register set and the first register A read-and-clear circuit, wherein an output of the logic circuit is input to a reset of the first register so as to avoid a reset conflict. 2. The system according to claim 1, wherein the status signal is a serial communication reception signal that can be continuously received.
Read and clear circuit as described. 3. The read and clear circuit according to claim 1, wherein the read signal is a signal from a CPU. 4. The read-and-clear circuit according to claim 1, wherein the first register does not perform a reset operation when the first register is at “0” level. 5. The read-and-clear according to claim 1, wherein said first register performs a reset operation when said first register is at "1" level and said clear timing signal is at "1" level. circuit. 6. The read-and-clear circuit according to claim 1, wherein said logic circuit is a two-input AND circuit. Wherein said first buffer claim 1 which is a second register, 2,3, 4, 5 or 6 read and clear circuit according.