JP3336669B2 - Correction waveform generation circuit for TV receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correction waveform generating circuit for a television receiver. More particularly, the present invention relates to a correction waveform generation circuit incorporated in a multi-scan compatible television receiver.

[0002]

2. Description of the Related Art A television receiver raster-scans an electron beam in accordance with a horizontal synchronizing signal and a vertical synchronizing signal to form an image display on the screen of a CRT. A correction waveform generation circuit that generates various correction waveform signals for correcting image distortion, misconvergence, and the like is incorporated. 2. Description of the Related Art Some television receivers are operable by switching and selecting a plurality of system frequencies. In such a multi-scan television receiver, the frequency of the correction waveform signal also needs to be changed according to the selected system frequency.

FIG. 18 is a block diagram of a conventional multi-scan compatible correction waveform generation circuit, which utilizes charging and discharging of a capacitor. The horizontal synchronizing signal HD or the vertical synchronizing signal VD is differentiated by the differentiating circuit 11, and a pulse is generated at each rising timing of the synchronizing signal. This pulse is used as a set pulse signal S11 for the next stage flip-flop 12, and sets the flip-flop 12 to generate the switch control signal S12. The switch 15 connected to the flip-flop 12 is turned on by the switch control signal S12, and charges the capacitor 16 in the positive direction by the constant current source 14. This operation is performed during a blanking period of a horizontal scan line or a vertical scan line. This capacitor 16 is a differential amplifier 17
Is connected between the output terminal and the negative input terminal. When the comparison circuit 13 detects that the positive charge peak potential of the capacitor 16 has exceeded the set / reset comparison voltage BIAS, a reset pulse signal S13 is output and the flip-flop 12 is reset. As a result, the switch control signal S12 is inverted, the switch 15 is turned off, and the capacitor 16 is gradually charged in the negative direction by another constant current source 19. This charging is continued until the next horizontal synchronization signal HD or vertical synchronization signal VD rises. In this way, a sawtooth wave that matches the horizontal synchronization signal or the vertical synchronization signal is obtained. By multiplying the sawtooth wave by the multiplying circuit 18, a parabolic wave can be obtained at the same time.

FIG. 19 shows an example in which an automatic gain control circuit (AGC circuit) 22 is added to the circuit of FIG. Based on the output signal S22 of the differential amplifier 17 and the AGC control signal S23,
The AGC circuit 22 outputs a charging current control signal S21,
The output current amount of the variable current source 21 is controlled. That is, when the frequency of the horizontal synchronizing signal HD or the vertical synchronizing signal VD changes and the amplitude of the sawtooth output signal S22 exceeds a predetermined value, the charging current is reduced. Conversely, when the amplitude falls below a predetermined value, feedback control is performed so as to increase the charging current.

[0005]

According to the conventional example shown in FIG. 18, it is possible to cope with a system in which the horizontal synchronizing signal HD and the vertical synchronizing signal VD have different frequencies. You can get parabola waves. However, in this conventional example, since the charging of the capacitor 16 is used, the horizontal synchronizing signal HD and the vertical synchronizing signal VD
Changes, the switching frequency of the switch 15 also changes. Therefore, there is a problem that the charging time of the capacitor 16 varies and the amplitude of the output sawtooth wave or parabola wave varies. That is, the amplitude of the output waveform decreases as the frequency of the synchronization signal increases, and conversely, the amplitude increases as the frequency of the synchronization signal decreases.

In order to remedy the drawbacks of the conventional circuit shown in FIG. 18, the conventional example shown in FIG. 19 has an AGC circuit 22 built therein, and the output current of a constant current source 21 used for charging the capacitor 16. Is feedback-controlled to keep the amplitude of the output waveform constant. However, there is a problem that complicated hardware is required to configure the AGC circuit 22. 18 and FIG.
A disadvantage common to both of the prior art shown in FIG. 9 is that since the correction waveform is formed by completely hardware means such as charging and discharging of a capacitor, it is limited to a relatively simple waveform and it is not easy to make changes. There is a problem that.

[0007]

[0008]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention provides a correction waveform generating circuit for a multi-scan television receiver capable of generating a variety of complicated waveforms with a simplified configuration. The purpose is to provide. The following measures were taken to achieve this purpose. That is, the television receiver correction waveform generating circuit according to the present invention is less
And a counter that counts the oscillation output at a given frequency.
A first and a first PLL circuit for outputting a counter signal, to accept the horizontal correction waveform data as addresses to store the predetermined horizontal correction waveform data of the first counter signal synchronized with the horizontal synchronizing signal the first is out repeatedly read 1
Memory circuit and at least an oscillation output of a predetermined frequency.
Has a counter for counting an address and a second PLL circuit for outputting a in synchronization with <br/> second counter signal the vertical synchronizing signal, a storing a predetermined vertical correction waveform data and the second counter signal as a second memory circuit for receiving said vertical correction waveform data is read out <br/> Ri, repeatedly, and the horizontal correction waveform data read out from said first memory circuit, from the second memory circuit And a digital-to-analog conversion circuit that performs a multiplication process on the read vertical correction waveform data, converts the multiplication process into a correction analog signal, and outputs the corrected analog signal. More specifically, the first memory circuit, said plant
Parabolic waveform data and / or S-shaped waveform data are stored as fixed horizontal correction waveform data . The second memory circuit also stores parabolic waveform data and / or S-shaped waveform data as the predetermined vertical correction waveform data . Further, the first or second memory circuit may include two or more different horizontal correction waveform data or two or more different vertical correction data.
The correction waveform data is alternately stored, and the first or second counter signal is stored in accordance with the first or second counter signal .
Horizontal correction waveform data or
The vertical correction waveform data is read.

[0009]

[0010]

In the present invention, necessary correction waveform data is stored in advance by using a memory circuit. Therefore,
Not only the parabolic waveform but also a complicated waveform such as an S-shaped waveform can be freely recorded. Further, a clock for addressing the memory circuit is generated in accordance with the horizontal synchronizing signal and the vertical synchronizing signal using the PLL circuit. Therefore, a desired waveform can be read from the memory circuit in synchronization with the synchronization signal of the system frequency selected as needed. further,
Since the read waveform data is converted into a corrected waveform signal using the digital-analog conversion circuit, an output having a constant amplitude can always be obtained. Further, the amplitude of the output waveform can be easily adjusted by controlling the reference voltage supplied to the digital-to-analog conversion circuit as desired.

[0011]

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a correction waveform generating circuit for a multi-scan television receiver according to the present invention. This correction waveform generation circuit includes a PLL circuit 31 and a vertical synchronization signal V corresponding to the horizontal synchronization signal HD.
A PLL circuit 37 corresponding to D is provided. For example, the horizontal synchronizing signal HD is input to the phase comparison circuit 34 included in the PLL circuit 31, and is compared with the phase comparison signal S33 to output the phase detection signal S31. This phase detection signal S31 is input to a voltage controlled oscillator (VCO) 35 and oscillates at a predetermined frequency to obtain a VCO output signal S32. The VCO output signal S32 is input to the counter 36 as a clock, and an address signal ad is obtained as a counter output synchronized with the horizontal synchronization signal HD. In response to the input of the address signal ad, the memory circuit 32 outputs waveform data dt recorded in advance therein. The read waveform data dt is supplied to the digital / analog conversion circuit 33.
To generate a corrected waveform signal. By appropriately setting the reference voltage ref of the digital / analog conversion circuit 33, the amplitude of the output correction waveform signal can be freely adjusted.

The portion corresponding to the vertical synchronizing signal VD has the same configuration. That is, the PLL circuit 37 outputs the vertical synchronization signal V
D and the phase comparison signal S36 to compare the phase detection signal S
34 is output. The VCO 311 generates a VCO output signal S35 according to the phase detection signal S34. Counter 31
2 counts the VCO output signal S35 and outputs an address signal AD. The memory circuit 38 reads out the previously recorded waveform data DT according to the address signal AD. The read waveform data DT is converted into a digital-to-analog conversion circuit 39.
And an output correction waveform signal is obtained. The amplitude of the output can be adjusted by controlling the reference voltage REF of the digital / analog conversion circuit 39.

FIG. 2 shows a specific example in which the multi-scanning correction waveform generation circuit according to the present invention is applied to a screen division type convergence correction circuit. The screen division type convergence correction circuit requires, for example, a one-dimensional horizontal correction parabola waveform signal, a one-dimensional vertical correction parabola waveform signal, and a two-dimensional correction waveform signal obtained by multiplying the pair of one-dimensional correction parabola waveform signals. . In this specific example, first, the horizontal synchronizing signal HD is input to an n-multiplier type PLL circuit 91 to obtain a counter signal S91 multiplied by n. This counter signal S
By inputting the address 91 into the memory circuit 93 as an address, parabola waveform data S93 synchronized with the horizontal synchronizing signal HD is obtained from the memory circuit 93. The read waveform data is processed by the digital / analog conversion circuit 95 to obtain a corresponding output signal S96.

FIG. 3 shows an arrangement of data stored in the memory circuit 93. Digital data HPx obtained by digitizing a horizontal period parabolic wave is stored. These 2n parabolic waveform data are sequentially read by the address signal ad.

FIG. 4 shows a parabolic wave read from the memory circuit 93. It is composed of data HP ₀ to HP _2n−1 arranged sequentially during one horizontal period 1H. When this waveform data S93 is input to the digital / analog conversion circuit 95 and a DC voltage is applied as the reference voltage S95, it is converted to an analog signal having a predetermined amplitude.

Returning to FIG. 2, description of the correction waveform generating circuit will be continued. Like the horizontal synchronizing signal HD, the vertical synchronizing signal V
D is input to the PLL circuit 92 multiplied by N, and an internal counter signal S92 synchronized with this is obtained. This is input to the memory circuit 94 as an address. By this addressing, parabola waveform data S94 synchronized with the vertical synchronizing signal VD is obtained from the memory circuit 94. The parabola waveform data S94 is processed by the digital / analog conversion circuit 97 to obtain a one-dimensional vertical correction parabola waveform signal.

FIG. 5 shows parabola waveform data recorded in the memory circuit 94 in advance. This memory circuit 94 includes 2N data VPx and is sequentially accessed by an address signal AD.

FIG. 6 shows the read parabolic wave for vertical correction. VP ₀ to VP _2N-1 over one vertical period 1V
Pieces of digital data are arranged. The read-out vertical correction parabolic waveform data S94 is input to the digital-to-analog conversion circuit 97 and the reference voltage S95 is set to a DC voltage, so that a parabolic wave output signal having a constant amplitude is obtained every vertical scanning cycle. can get.

Returning to FIG. 2, description of the correction waveform generating circuit will be continued. In this specific example, a third digital / analog conversion circuit 96 is included. The horizontal parabola waveform data S93 read from the memory circuit 93 is input to the digital / analog conversion circuit 96, and a vertical parabola waveform signal S98 is supplied as a comparison voltage. As a result, the digital / analog conversion circuit 96 can obtain an output waveform signal S97 obtained by multiplying the horizontal period parabola wave and the vertical period parabola wave by each other.

FIG. 7 shows a waveform subjected to the multiplication processing. This waveform changes as a whole every vertical cycle 1V, and includes a portion that changes every horizontal cycle 1H.

As apparent from the above description, the correction waveform generating circuit of FIG. 2 obtains a one-dimensional horizontal correction parabolic waveform signal from the first digital-to-analog conversion circuit 95, and outputs the one-dimensional horizontal correction parabolic waveform signal from the second digital-to-analog conversion circuit 97. A one-dimensional vertical correction parabolic waveform signal is obtained, and a two-dimensional correction waveform signal is obtained from the third digital / analog conversion circuit 96.

Next, referring to FIG. 8, a description will be given of a waveform signal processing circuit used for the screen division type convergence correction. This processing circuit performs the above-described three types of correction waveform signals S
96, S97 and S98 are processed. Before describing the circuit of FIG. 8, typical waveforms at each division point necessary for adjusting convergence by screen division will be described with reference to FIGS. For example, correction waveforms shown in FIGS. 10 to 13 are assigned to 3 × 3 division points or the like shown in FIG. These screen division points or convergence adjustment points that can be operated independently of each other.

FIG. 10 shows division points located at four corners of the screen.
, And are two-dimensional waveforms obtained by multiplying a vertical period parabola waveform VP and a horizontal period parabola waveform HP by each other. This two-dimensional waveform is divided into four parts at the top, bottom, left and right of the screen, and the amplitude of each is independently adjusted by an external volume or the like.

FIG. 11 shows a one-dimensional parabolic waveform HP having a horizontal period, which is a typical waveform necessary for adjusting the dividing points. This parabolic waveform HP is divided into two on the left and right sides of the screen,
The amplitude is independently adjusted by an external volume or the like.

FIG. 12 shows a typical waveform required for adjusting the dividing point and the vertical axis, which is represented by a one-dimensional vertical parabolic waveform VP. This parabola waveform VP is divided into two parts at the top and bottom of the screen, and the amplitude is adjusted by an external volume or the like.

Finally, FIG. 13 shows a typical waveform required for adjusting the center division point, which is DC.

Returning to FIG. 8, the convergence adjusting circuit will be described in detail. First, the output signal S96 from the correction waveform generation circuit shown in FIG. The input output signal S96 is supplied to an inversion circuit 1510.
A variable resistor (volume) assigned to an adjustment point together with an inverted signal S151 inverted by
A horizontal first-half output signal S152 and a horizontal second-half output signal S153 applied to both ends of VR4 and VR6 and subjected to amplitude adjustment, respectively, are obtained.

On the other hand, the output signal S97 obtained from the correction waveform generating circuit is input to the switch 157, and is switched by the vertical center pulse VCP. As a result, the output signal S97 is switched between the first half and the second half of the vertical cycle,
Vertical first half output signal S154 and vertical second half output signal S1
It is divided into 55. The vertical first half output signal S154 and the vertical second half output signal S155 include a second adjustment unit 152 including a pair of variable resistors VR1 and VR3 corresponding to an adjustment point and a variable resistor VR7 corresponding to the adjustment point.
The first and second horizontal output signals S156 and S158 and the output signals S157 and S159 for the second half of the horizontal are obtained by being input to the third adjustment unit 153 including the VR9, respectively. Furthermore, the output signals S152, S156, S158 for the first half of the horizontal are added to the addition circuit 1
511, and is added to the horizontal first half synthesized signal S151.
It becomes 0. Also, the horizontal second half output signals S153 and S15
7 and S159 are added by an adder circuit 1512 to become a horizontal second half synthesized signal S1511.

The pair of horizontal first-half synthesized signals S151
By inputting the composite signal S1511 for 0 and the horizontal second half to the switch 159 and switching by the horizontal center pulse HCP, a horizontal composite signal S1512 switched between the first half and the second half of the horizontal period is obtained. Therefore, at this point, the adjustment of the adjustment points,,, and can be performed independently of each other.

Next, the output signal S98 from the correction waveform generating circuit shown in FIG. 2 is input to the switch 158 and switched by the vertical center pulse VCP, whereby the output signal S98 is switched between the first half and the second half of the vertical cycle. The output signal is divided into a vertical first half output signal S1513 and a vertical second half output signal S1514. The divided vertical first half output signal S1513 and vertical second half output signal S1514
Are input to a fourth adjustment unit 154 including a variable resistor VR2 corresponding to an adjustment point and a fifth adjustment unit 155 including a variable resistor VR8 corresponding to an adjustment point, respectively. An adjustment signal S1516 is obtained.

Further, the DC voltage is input to the sixth adjusting unit 156 including the variable resistor VR5 corresponding to the adjustment point to obtain the static signal S1517. Then, the vertical first half adjustment signal S1515, the vertical second half adjustment signal S1516, and the static signal S1517 are input to the addition circuit 1513 to obtain a vertical composite signal S1518. Therefore, at this point, the adjustment of the adjustment points can be freely performed.

The horizontal composite signal S15 thus obtained is
12 and the vertical composite signal S1518 are input to the addition circuit 1514 to obtain a horizontal / vertical composite signal S1519. This is input to a convergence amplifier 1515, and a convergence correction signal S1520, which is an output signal thereof, is input to a convergence yoke CY to execute convergence correction. As described above, the correction waveform generation circuit according to the present invention can be used for convergence adjustment of a screen division type. Note that the present invention is not limited to this.

In the specific example of FIG. 2 described above, both the horizontal memory circuit and the vertical memory circuit record parabolic waveform data as shown in FIG. 3 and FIG. However,
The present invention is not limited to this, and the waveform data stored in the memory circuit can be easily changed to another shape. Although the memory circuit shown in FIG. 2 stores only one type of waveform data for each of the horizontal cycle and the vertical cycle, for example, as shown in FIG.
Px and the horizontal period S-shaped wave or sine wave HSx can be stored in a memory circuit in a time-division multiplexing manner.
In this manner, the number of constituent data included in one horizontal scanning time 1H is halved for each waveform, but two types of waveforms can be output simultaneously in synchronization with the horizontal cycle. FIG. 15 shows the parabola waveform and the S-shaped waveform obtained at this time.

FIG. 16 shows a specific example in which various types of correction waveform signals are output using the time division driving method. The operation of this circuit is basically similar to that of the circuit shown in FIG. 2, and therefore the following description will focus on the differences.
In this description, a timing chart showing an operation relating to a multiplexing portion of data in the horizontal direction is also referred to in FIG. 17 for easy understanding. First, data HPx of a horizontal period parabola wave and data HSx of a horizontal period S-shaped wave or sine wave are stored in the memory circuit 183. An n-times counter output signal S generated by the PLL circuit 181 and synchronized with the horizontal synchronization signal HD.
Data is read from the memory circuit 183 using the address signal 181 as an address signal. Read waveform data S1
83 is input to the digital-to-analog conversion circuits 185 to 188. In the read operation of the memory circuit 183, as understood from the data array of FIG. 14, the horizontal period parabola wave data HPx and the horizontal period S-shaped wave data HSx are alternately output sequentially. Therefore, the horizontal period parabola wave data HPx is input to the pair of digital / analog conversion circuits 185 and 187, and the horizontal period S-shaped wave data HSx is input to the digital / analog conversion circuits 186 and 188.
To the digital-to-analog conversion circuit selection signal D
The digital-analog conversion circuit is switched by AS1 and DAS2. Digital-to-analog conversion circuit 18
5, 186, the reference signal S1810 supplied to the output signals S185, S186
Are a parabolic wave signal having a one-dimensional horizontal cycle and an S-shaped wave signal having a one-dimensional horizontal cycle, respectively.

On the other hand, the memory circuit 184 stores parabolic wave data having a vertical cycle similar to that shown in FIG. The memory circuit 184 is addressed using the N-multiplied counter signal S182 synchronized with the vertical synchronization signal VD, and the parabolic wave data S184 is read. The read data S184 is converted to a digital / analog conversion circuit 189.
Is input to Here, the digital / analog conversion circuit 189
Since the reference signal S1810 is a DC voltage as described above, the output signal S189 is a one-dimensional vertical period parabolic wave signal.

This output signal S189 is input as a reference signal for digital-to-analog conversion circuits 187 and 188. Therefore, from the digital-to-analog conversion circuit 187,
An output waveform signal S187 obtained by multiplying the horizontal period parabola wave by the vertical period parabola wave is obtained. Similarly, the digital-to-analog conversion circuit 188 outputs an output waveform signal S18 obtained by multiplying the horizontal period S-shaped wave by the vertical period parabola wave.
8 is obtained. At this time, a time division operation is performed on the multiplexed portion of the data in the horizontal direction as shown in the timing chart of FIG.

In this way, a total of five types of waveforms including a two-dimensional waveform are obtained. If this is applied to a screen division type convergence correction circuit, a total of 15 division adjustments of three vertical divisions and five horizontal divisions can be performed as screen division points. In other words, as long as the number of constituent data for one cycle is sufficient to digitally represent a waveform, a plurality of waveforms can be read out in a time-sharing manner in synchronization with a common synchronization signal, and the number of screen divisions for convergence correction can be reduced. It can be increased and diversified. As described above, the present invention is effective for convergence correction, but the application range is not limited to this, and is useful for a wide variety of applications such as a focus circuit and an image distortion correction circuit.

Next, as a development example of the present invention, an embodiment in which a clamp pulse is inserted in a horizontal retrace period for a correction waveform signal corresponding to multi-scan will be described below. Prior to the description, a conventional clamp pulse insertion method will be briefly described. As shown in FIG. 20, in this conventional example, when a vertical component of a correction waveform is transmitted to a high voltage side by a diode clamp method using a transformer or the like in a correction waveform generating circuit for a television receiver, a clamp pulse is transmitted during a horizontal retrace period. Used to insert into In this method, a clamp pulse is inserted in an analog manner using the horizontal synchronizing signal HD and the monostable multivibrators 211 and 212. In describing the conventional method, a timing chart shown in FIG. 21 is also referred to. First, when the horizontal synchronizing signal HD is input to the first monostable multivibrator 211, a time constant τ1 determined by an external resistor R1 and a capacitor C1 =
Phase adjustment signal S2 according to A, R1, and C1 (A: constant)
11 is obtained. This phase adjustment signal S211 is input to the second monostable multivibrator 212. As a result, a clamp pulse timing signal S212 is obtained according to a time constant τ2 = A · R2 · C2 determined by the external resistor R2 and the capacitor C2. This timing signal S
Reference numeral 212 determines an appropriate width and phase of the clamp pulse inserted into the correction waveform. In response to the clamp pulse timing signal S212, the switch circuit 213
Switches between a horizontal correction signal S213 having a horizontal component of the correction waveform and a vertical correction signal S214 having a vertical component of the correction waveform, and outputs a correction waveform S215 into which a clamp pulse is inserted.
Is obtained.

In the conventional method described above, the absolute width of the clamp pulse timing signal S212 is determined by the resistors R1 and R2 and the capacitors C1 and C2 externally connected to the first and second monostable multivibrators 211 and 212. The phase is set in an analog manner with respect to the time axis. Therefore, if the horizontal frequency of the horizontal synchronization signal HD becomes different depending on the receiver system due to multi-scan correspondence,
In the clamp pulse timing signal S212 determined by the absolute width and phase with respect to the time axis, the relative positional relationship is shifted with respect to the correction waveform synchronized with the horizontal period, and the clamp pulse is shifted to the correct position. The inserted correction waveform cannot be obtained. To cope with this, the value of the externally connected resistors R1 and R2 and the capacitors C1 and C2 are adjusted every time the horizontal frequency changes depending on the system, so that the clamp pulse for absolutely determined with respect to the time axis is adjusted. The width and phase of the timing signal S212 must be adjusted to be correct for the correction waveform. Therefore, there is a problem that complicated adjustment work is required to support multi-scan.

In order to solve this problem, in the present invention, the width and the phase of the clamp pulse can be inserted relatively constant regardless of the difference in the selected horizontal system frequency. With reference to FIG. 22, a basic circuit configuration of such a system will be described. In this circuit configuration, the horizontal period (H)
And a setting circuit (digital switches 232, 233) that operates in synchronization with the clock signal and outputs a multiplied counter signal P, and sets a time position in the horizontal period and outputs a corresponding address signal (Q1, Q2). ), Comparing circuits 234 and 235 for comparing the counter signal P with the address signals Q1 and Q2 and outputting a timing signal S233 for sequentially designating the width and phase of the clamp pulse, and synchronizing in advance according to the timing signal S233. The switching circuit 237 switches between the horizontal period component S234 and the vertical period component S235 of the converted correction waveform and inserts a clamp pulse.

Next, the operation of the circuit configuration shown in FIG. 22 will be described. When the horizontal synchronizing signal HD having the selected horizontal cycle is input to the PLL circuit 231, a k-bit counter signal P multiplied by n by an internal counter circuit is obtained. That always horizontal period even after changing the horizontal frequency by the system is 2 ^k equally, to such relative positional relationship with respect to the horizontal period is represented by a counter signal P. On the other hand, desired k-bit data can be set by the first digital switch 232 and the second digital switch 233.
And the end address signal Q2. The first comparison circuit 234 compares the counter signal P and the start address signal Q1 with each other, and outputs a start point signal S231 according to a determination formula P ≧ Q1. Similarly, the second comparison circuit 235 compares the counter signal P and the end address signal Q2 with each other, and calculates the end point signal S in accordance with the determination formula P ≦ Q2.
232 is output. These pair of start point signals S23
1 and the end point signal S232 are processed by the AND circuit 236 to obtain a clamp pulse timing signal S233. Since the timing signal S233 is determined from the relative positional relationship assigned to the horizontal period, it always has the same width and phase relative to the correction waveform synchronized with the horizontal period even if the horizontal frequency changes. become. Therefore, in response to the clamp pulse timing signal S233, the switch circuit 237 switches between the horizontal correction signal S234 having the horizontal component of the correction waveform and the vertical correction signal S235 having the vertical component of the correction waveform, and the clamp pulse is inserted. A correction waveform S236 is obtained. First, if the insertion position of the clamp pulse is appropriately set by the first digital switch 232 and the second digital switch 233, a corrected waveform into which the clamp pulse corresponding to the multi-scan is inserted without adjustment is obtained.

An application example of the non-adjustable clamp pulse insertion method for multi-scan described above will be described below. Here, an example in which a convergence correction circuit compatible with multi-scan is applied to an electrostatic convergence system unique to Trinitron will be described. First, an electrostatic convergence system which is a feature of Trinitron will be described with reference to FIG. In the illustrated electron gun structure, the convergence control plate CP has a high voltage HV and a high resistance H.
A convergence voltage CV is applied through VR. Accordingly, the center beam G travels straight because no electric field is applied, while the side beams B and R are bent by the electric field between the convergence control plates CP.
By controlling the convergence voltage CV, the convergence point changes, and convergence correction by the electrostatic method becomes possible.

Here, the reason why horizontal misconvergence occurs in the horizontal direction will be described with reference to FIG. When a DC convergence voltage CV is applied to the convergence control plate CP so that the three electron beams converge at the screen center c, the convergence point is located on the spherical surface a. However, since the front panel b of the CRT has a shape that is almost flat, overconvergence occurs on both sides. In order to correct this, a correction waveform as shown in FIG. 25B may be applied as the convergence voltage CV. Similarly, the horizontal misconvergence in the vertical direction can be corrected by applying a correction waveform as shown in FIG. 25A as the convergence voltage CV. Therefore, as shown in FIG. 25 (C), these two combined waveforms are the convergence correction waveforms that are finally required as the convergence voltage CV.

Since the convergence voltage CV has a high voltage, a transformer is used to transmit the correction waveform, thereby achieving electrical insulation in the circuit. However, the voltage of the vertical period as shown in FIG. 25 (C) has a relatively low frequency, so that it is difficult to transmit the voltage only by the transformer. Therefore, in practice, as shown in FIG. 26, a DCT block 271 including a transformer DCT is used, and a waveform in which a pulse is inserted during a horizontal retrace period is transformed into a transformer D.
It is input to the primary side of CT. On the other hand, a diode clamp circuit composed of a capacitor 272 and a diode 273 is connected to the secondary side of the transformer DCT, and a peak is clamped to a static voltage VA determined by a static variable resistor 275 to realize transmission of a corrected waveform. . That is, the convergence correction is executed by changing the height of the pulse according to the horizontal misconvergence correction component in the vertical direction.

In this application example, the secondary correction waveform of the clamp pulse input to the primary side of the transformer DCT of the convergence system described above is obtained in multi-scan correspondence. Hereinafter, this application example will be described in detail with reference to the circuit diagram of FIG. 27 and the timing chart of FIG. Here, first, the horizontal synchronization signal HD is input to the PLL circuit 281. For example, assuming that the horizontal frequency is multiplied by 128 at the maximum, the horizontal frequency of 1, 2, 4, 8, 16, 32, 64, 12
An eight-times total 8-bit counter signal P is obtained. That is,
Even if the horizontal frequency differs depending on the system, the horizontal cycle is always divided into 256 equal parts, and addresses 0 to 255 are assigned to each horizontal cycle by the counter signal P. Therefore, the relative positional relationship within the horizontal cycle can be determined from the counter signal P. On the contrary,
By operating the first digital switch 282 of 8 bits, the start address signal Q1 is calculated according to the formula P in the data of 0 to 255.
Set to satisfy ≧ Q1. Similarly, the 8-bit second digital switch 283 is operated to set the end address signal Q2 so as to satisfy the expression P ≦ Q2 among the data of 0 to 255, respectively. The counter signal P and the start address signal Q1 are input to the first comparison circuit 284, and the equation P ≧
By performing a comparison process based on Q1, a start point signal S281 of a positive logic output is obtained. Similarly, the counter signal P and the end address signal Q2 are input to the second comparison circuit 285, and a comparison process is performed based on the equation P ≦ Q2 to obtain a positive logic output end point signal S282. This start point signal S
281 and the end point signal S282 are subjected to AND operation by the AND circuit 286 to obtain a clamp pulse timing signal S283. At this time, since the information on the appropriate width and phase with respect to the horizontal period is set relatively in advance, the clamp pulse timing signal S283
Is always a predetermined appropriate relationship to the horizontal period, even if the horizontal period varies from system to system.
Multi-scan support is possible.

On the other hand, the multi-scan compatible correction waveform generating circuit 2813 has the configuration described above with reference to FIGS. First, the horizontal synchronization signal HD is input to the horizontal period basic correction waveform generation circuit 289, and a horizontal period basic correction waveform S288 synchronized with the horizontal synchronization signal HD in multi-scan correspondence is obtained. Similarly, the vertical synchronization signal VD is input to the vertical period basic correction waveform generation circuit 2810, and a vertical period basic correction waveform S289 synchronized with the vertical synchronization signal VD in multi-scan correspondence is obtained. Further, the basic correction waveform S288 of the horizontal cycle and the basic correction waveform S289 of the vertical cycle are multiplied by each other by a multiplication circuit 2812 to obtain a two-dimensional basic correction waveform S2810.
The above configuration is similar to the circuit described with reference to FIG. Each of these basic correction waveforms S288, S289, S2
810 is a screen division type convergence correction circuit 2811
And a horizontal correction signal S284 having a horizontal component of the correction waveform and a vertical correction signal S285 having a vertical component of the correction waveform are obtained by the internal variable resistors. The screen division type convergence correction circuit 2811 has the same configuration as that shown in FIG.

Multi-scan compatible correction waveform generation circuit 2
The horizontal correction signal S284 and the vertical correction signal S285 output from the switch 813 are switched by the switching circuit 287 in response to the timing signal S283 for the multi-scan corresponding clamp pulse obtained by the method of the present invention, and the clamp pulse corresponding to the multi-scan is output. Is obtained. The correction waveform S286 into which the clamp pulse has been inserted is input to the DCT block 288. This DCT block 288 has the same structure as that shown in FIG. 26, and outputs a convergence correction waveform S287 effective for an electrostatic convergence system. This output is applied to the convergence control plate CP as the convergence voltage CV of the CRT. As understood from the above description, this method is effective for an electrostatic convergence system in which a vertical periodic component is transmitted using a transformer, but the application is not limited to this. For example, it is similarly effective for the focus circuit to have a configuration in which a vertical period component is transmitted using a transformer. In this method, even if the horizontal frequency changes depending on the system, a timing for inserting a clamp pulse following the horizontal frequency without adjustment is obtained. A clamp pulse can always be inserted relative to the original correction waveform with the same width and phase relationship. In the case where the waveform of the vertical cycle is transmitted to the secondary side of the transformer by the diode clamp method using the clamp pulse, a complementary waveform including a clamp pulse for multi-scan can be easily formed.

[0049]

As described above, according to the present invention, even if the horizontal synchronizing signal HD and the vertical synchronizing signal VD are different from time to time depending on the system, it is possible to arbitrarily apply the synchronizing signal by a simple means of reading data from the memory circuit. There is an effect that various synchronized correction waveforms can be generated. Moreover, the maximum amplitude and the minimum amplitude of the output waveform can be controlled to be constant without using an AGC circuit or the like as in the prior art, and there is an effect that a correction waveform corresponding to multi-scan can be formed very easily. In addition, there is an effect that various kinds of two-dimensional correction waveforms can be realized by using the digital-analog conversion circuit as a multiplier.

[0050]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a correction waveform generation circuit for a television receiver according to the present invention.

FIG. 2 is a block diagram showing a specific example of a correction waveform generation circuit for a television receiver according to the present invention.

FIG. 3 is a waveform data array diagram of a memory circuit used in the circuit shown in FIG. 2;

FIG. 4 is a schematic diagram showing a waveform read from the memory circuit.

FIG. 5 is an array diagram of waveform data similarly stored in a memory circuit.

FIG. 6 is a schematic diagram showing a waveform read from the memory circuit.

FIG. 7 is a schematic diagram showing a two-dimensional waveform obtained by multiplying horizontal waveform data and vertical waveform data by each other.

FIG. 8 is a block diagram showing a configuration of a convergence adjustment circuit connected to the correction waveform generation circuit shown in FIG.

FIG. 9 is a schematic diagram showing adjustment points for screen division convergence correction.

FIG. 10 is a schematic diagram illustrating a correction waveform used for screen division convergence correction.

FIG. 11 is a schematic diagram showing a correction waveform.

FIG. 12 is a schematic diagram similarly showing a correction waveform.

FIG. 13 is a schematic diagram similarly showing a correction waveform.

FIG. 14 is a schematic diagram showing two types of waveform data arrays stored in a memory circuit.

FIG. 15 is a schematic diagram showing a waveform read from the memory circuit shown in FIG. 14;

FIG. 16 is a block diagram showing another specific example of the correction waveform generation circuit for a television receiver according to the present invention.

17 is a timing chart of the correction waveform generation circuit shown in FIG.

FIG. 18 is a block diagram showing an example of a conventional multi-scan compatible correction waveform generation circuit.

FIG. 19 is a block diagram showing another example of a conventional correction waveform generation circuit for multi-scan.

FIG. 20 is a block diagram showing a conventional example of a correction waveform generator with a clamp pulse for multi-scan.

FIG. 21 is a signal waveform diagram for describing the operation of the conventional circuit shown in FIG. 20;

FIG. 22 is a block diagram showing a multi-scan compatible correction pulse-containing correction waveform generation circuit according to the present invention.

FIG. 23 is a schematic view showing a general structure of a trinitron electron gun.

FIG. 24 is an explanatory diagram of an electrostatic convergence viewed from above a Trinitron CRT.

FIG. 25 is an explanatory diagram of a correction waveform required for electrostatic convergence.

FIG. 26 is a circuit diagram of a transformer block used in the electrostatic convergence system.

FIG. 27 is a block diagram showing an embodiment of a correction waveform generating circuit with clamp pulse corresponding to multi-scan according to the present invention.

FIG. 28 is a signal waveform diagram for describing the operation of the circuit shown in FIG. 27;

[Explanation of symbols]

 31 PLL circuit 32 Memory circuit 33 Digital-to-analog conversion circuit 34 Phase comparison circuit 35 VCO 36 Counter

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/14-5/217

Claims (4)

(57) [Claims] At least an oscillation output of a predetermined frequency is controlled.
Includes a counter that count, receiving horizontal and first PLL circuit for outputting a first counter signal synchronized with the horizontal synchronizing signal, a storing predetermined horizontal correction waveform data of the first counter signal as an address a first memory circuit for correcting waveform data is output repeatedly reading <br/>, at least, Cau for counting the oscillation output of a predetermined frequency
Has a pointer, second and PLL circuit, a predetermined receiving the vertical correction waveform as storing vertical correction waveform data address the second counter signal for outputting a second counter signal synchronized with the vertical synchronizing signal a second memory circuit in which data is output repeatedly reading <br/>, the horizontal correction waveform data read out from the first memory circuit, a vertical correction waveform data read out from said second memory circuit And a digital-to-analog conversion circuit that performs a multiplication process between the signal and a converted analog signal and outputs the corrected analog signal. 2. The method according to claim 1, wherein the first memory circuit includes the predetermined water.
2. The correction waveform generation circuit for a television receiver according to claim 1 , wherein parabola waveform data and / or S-shaped waveform data is stored as the flat correction waveform data . 3. The method according to claim 2, wherein the second memory circuit includes the predetermined vertical
2. The correction waveform generation circuit for a television receiver according to claim 1 , wherein parabola waveform data and / or S-shaped waveform data is stored as the direct correction waveform data . 4. The first or second memory circuit stores two or more different horizontal correction waveform data or two or more different horizontal correction waveform data.
The vertical correction waveform data thus obtained are stored alternately, and the first or second counter signal is used in response to the first or second counter signal .
Horizontal correction waveform sequentially different from the first or second memory circuit
2. The correction waveform generating circuit for a television receiver according to claim 1, wherein data or vertical correction waveform data is read.