JP3337151B2 - Display device having digital convergence correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a digital convergence correction device capable of correcting image distortion and convergence on a screen with high accuracy.

[0002]

2. Description of the Related Art Convergence correction values at respective adjustment points are obtained in advance as convergence adjustment points, which are generated when a cathode ray tube screen is virtually divided into a grid in the horizontal and vertical directions, and stored as digital correction data. A digital memory that reads out the digital correction data in the memory and converts it into an analog signal by a digital / analog converter (D / A converter) when displaying an actual screen. The convergence yoke provided in the cathode ray tube 2. Description of the Related Art A display device having a digital convergence correction device for performing convergence correction by driving a convergence correction device is well known as disclosed in Japanese Patent Application Laid-Open No. 57-212492.

Hereinafter, the configuration of a display device having a conventional digital convergence correction device will be described with reference to FIG. FIG. 2 is a configuration diagram showing the configuration of a conventional digital convergence correction device.

In FIG. 2, reference numeral 1 denotes an input terminal of a synchronizing signal in a raster scan of a cathode ray tube screen. Reference numeral 2 denotes an address generator that generates an address signal synchronized with the raster scan based on the synchronization signal input from the input terminal 1. Reference numeral 3 denotes a memory for storing convergence correction data, which uses a volatile memory that loses data when the power is turned off. 4 is a digital / analog converter (D / A converter) for converting the digital data read from the memory 3 into an analog correction signal, 5 is an LPF (low-pass filter), 6 is an amplifier for driving a convergence yoke, 7, a convergence yoke; and 8, a cathode ray tube.

Reference numeral 9 denotes an instruction device such as a keyboard for an operator to instruct convergence adjustment, 10 a CPU (processing device) for reading and writing operations of the memory 3 and various arithmetic controls, and 11 correction data to be stored in the memory 3. Is a memory for storing correction data for storing data, and uses a non-volatile memory that does not lose data even when the power is turned off.
Reference numeral 12 denotes a display pattern generation circuit that generates a display pattern signal used for convergence adjustment such as cross hatching, and reference numeral 13 denotes a video signal processing circuit that amplifies the display pattern signal. 102 is a display device.

First, a normal screen display operation of the display device 102 will be described. Display device 1
Reference numeral 02 denotes that a video signal input from a video signal input terminal (not shown) is connected to the video signal processing circuit 13 and a video is displayed on the screen of the cathode ray tube 8.

At this time, the address generator 2 generates an address signal synchronized with the raster scan on the cathode ray tube screen, and reads the convergence correction data stored in the memory 3. The convergence correction data read from the memory 3 is converted into an analog correction signal by the D / A converter 4, then interpolated by the LPF 5, amplified by the amplifier 6, and drives the convergence yoke 7. The convergence correction on the screen of the cathode ray tube 8 is performed by the magnetic field generated by the convergence yoke 7.

Next, a description will be given of a circuit operation when performing convergence adjustment, which is an operation for obtaining convergence correction data to be stored in the memory 3 in advance. At the time of convergence adjustment, a cross hatch signal as a pattern necessary for the adjuster to look at the screen to determine whether the convergence state is appropriate and a cursor signal as a pattern required for the adjuster to confirm the adjustment position are provided. A display pattern signal is generated from a display pattern generation circuit 12 and supplied to a cathode ray tube 8 via a video signal processing circuit 13 to be displayed on the screen.

The coordinator judges the convergence state by looking at these patterns displayed on the screen of the cathode ray tube 8, and instructs the CPU 10 to adjust the convergence state by the indicating device 9 accordingly. Send to C
The PU 10 rewrites the correction data stored in the memory 3 according to the instruction received through the instruction device 9 and reflects the rewritten result on the screen of the cathode ray tube 8. Make any necessary adjustments and instructions,
Thus, the convergence is adjusted.

When the rewriting of the correction data stored in the memory 3 by the CPU 10 is completed and the coordinator sends an instruction to end the adjustment using the pointing device 9, the CPU 10 reads the correction data from the memory 3 and stores the correction data in the correction data storage memory 11. Write to. Since the correction data storage memory 11 is a non-volatile memory, the correction data can be stored even when the power is turned off.

The correction data stored in the memory 3 is lost when the power is turned off.
10 reads the correction data from the correction data storage memory 11 and writes it to the memory 3, and then performs convergence correction accompanying the screen display of the cathode ray tube 8.

[0012]

In the configuration of the conventional digital convergence correction device, the display pattern necessary for the adjuster to judge the convergence state is provided.
Since a cross-hatch signal and a display pattern generator (12 in FIG. 2) having a large circuit size for generating a cursor signal and the like as a display pattern necessary for the adjuster to confirm the adjustment position need to be provided. There is a problem that the cost of the display device having the digital convergence correction device is increased.

Further, a character pattern for improving operability at the time of convergence adjustment and a complex display pattern necessary for performing automatic convergence correction using detection and determination means for convergence state are generated. In the case of generation by a device, there is a problem that the circuit scale of the display pattern generator is further increased, and the cost is further increased.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a digital convergence correction capable of displaying a complicated pattern with a simple circuit configuration without providing a display pattern generator having a large circuit scale. It is an object to provide a display device having the device.

[0015]

In order to achieve the above object, according to the present invention, a display screen of a cathode ray tube is virtually divided into a plurality of regions, and a convergence correction value of each of the divided regions is obtained in advance to perform digital correction. In a display device having a digital convergence correction device for writing in a memory as data and reading the correction data from the memory to perform convergence correction of a display screen,

As digital correction data in the memory,
Find the convergence correction value to be written
When adjusting the convergence for
The lower bit area, which is
Instead of using convergence adjustment display pattern data
Used as a specific area to store,
From the lower bit area that is
Display the display pattern data for verence adjustment on the display screen.
On the display screen of the cathode ray tube
First route to display for convergence adjustment
And the original operation of displaying the screen as a display
In the lower bit area, which is a part of the memory,
Write digital correction data in the same way as the rest of the area
Raster scan of the display screen from both areas
Reads digital correction data in synchronization with
A second route for providing convergence correction of
Switching between the first route and the second route
Means.

[0017]

At the time of convergence adjustment , the lower-order video which is a part of the memory for storing the convergence correction data is processed by the CPU which controls the digital convergence correction device.
The convergence adjustment display pattern data is written in the cut area . Since the memory storing the convergence correction data is read out in synchronization with the raster scan,
The display pattern for convergence adjustment corresponding to the raster scan can be read and displayed on the cathode ray tube.

Also, by rewriting the convergence adjustment display pattern data, an arbitrary complicated pattern can be displayed. In this case, a piece of memory
Is lower bits area is used for storing display pattern data for adjusting convergence, (it becomes the scanning line density is somewhat irregular) because it does not store convergence correction data, convergence correction data lead to missing image quality deterioration portion However, there is no particular problem in the convergence correction accuracy.

[0019] After the convergence adjustment is completed, under the memory
The display pattern data written in the bit area is erased and convergence correction data is written. Therefore, during normal convergence correction, the scanning line density returns to uniform, and there is no deterioration in image quality. In the case where even when writing the display pattern data in the lower bit area of the memory does not occur image quality deterioration even after convergence adjustment completion, is required to erase the display pattern data written in the low-order bit area of the memory Absent.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing the configuration of one embodiment of the present invention.

In FIG. 1, reference numeral 20 denotes a switch for selecting whether to use the least significant bit data (LSB) of the memory 3 as convergence correction data or convergence adjustment display pattern data. Reference numeral 21 denotes a CPU that performs read / write operations of the memory 3 and various arithmetic controls, and is different from the CPU 10 in FIG. 2 (prior art) in the installed program. 101
Is a display device. Note that 1 to 9, 11, and 13 perform the same operations as those in FIG.

The operation of this embodiment will be described below. First, an operation at the time of convergence adjustment for obtaining a convergence correction value will be described. At the time of convergence adjustment, it is necessary to display a pattern such as a cross hatch on the screen of the cathode ray tube 8 to indicate the convergence adjustment state and the adjustment position.

Therefore, at the time of convergence adjustment, CP
By the operation of U21, the pattern data is written to the least significant bit of the memory 3. Also, by the operation of the CPU 21,
The switch 20 is switched to connect the least significant bit data of the memory 3 to the video signal processing circuit 13.

Since the memory 3 is read out in synchronization with the raster scan by the operation of the address generator 2, the display pattern data written in the least significant bit of the memory 3 is
The image is displayed on the screen of the cathode ray tube 8 via the switch 20 and the video signal processing circuit 13. Data other than the least significant bit of the memory 3 is sent to the D / A converter 4 and the LPF
5, convergence correction on the screen of the cathode ray tube 8 is performed via the amplifier 6, and the convergence yoke 7.

In this case, the least significant bit of the convergence correction data is lost and the image quality is degraded (the scanning line density is slightly irregular), but this does not cause any particular problem in the convergence correction accuracy. The coordinator operates the indicating device 9 while watching the display pattern displayed on the screen of the cathode ray tube 8,
A convergence adjustment operation is performed as in the conventional example (FIG. 2).

Next, the convergence correction operation at the time of normal screen display after the convergence adjustment is completed will be described. When the convergence adjustment is completed, the convergence correction data is written in the least significant bit of the memory 3 by the operation of the CPU 21. The switch 20 is switched by the operation of the CPU 21 to connect the least significant bit data of the memory 3 to the D / A converter 4 to perform convergence correction.

The display device 101 connects a video signal input from a video signal input terminal (not shown) to the video signal processing circuit 13 and displays a video on the screen of the cathode ray tube 8. Therefore, at the time of normal convergence correction, the scanning line density returns to uniform, and the image quality does not deteriorate.

According to this embodiment, a specific pattern (convergence adjustment display pattern) can be displayed on the screen of the cathode ray tube with a simple circuit configuration without providing a display pattern generator having a large circuit scale. . Also, by rewriting the display pattern data, it is possible to display an arbitrarily complicated display pattern.

Next, a description will be given of a second embodiment of the present invention in which no image quality deterioration occurs at the time of convergence adjustment. The present embodiment is applicable to a display device including three CRTs of R, G, and B, such as a projection television. FIG. 3 is a configuration diagram showing the configuration of the second embodiment of the present invention.

In FIG. 3, 33, 34, 35, 36,
37, 38, and 39 belong to the red system, 33 is a memory for storing convergence correction data of red (R), 34 is a D / A converter, 35 is an LPF, 36 is an amplifier, 37 is a convergence yoke, 38 Is a cathode ray tube, 3
Reference numeral 9 denotes a video signal processing circuit.

Similarly, 43, 44, 45, 46, 47,
48 and 49 belong to the blue system, 43 is a memory for storing convergence correction data of blue (B),
44 is a D / A converter, 45 is an LPF, 46 is an amplifier,
7 is a convergence yoke, 48 is a cathode ray tube, and 49 is a video signal processing circuit.

Reference numeral 50 denotes a switch for selecting whether to use the least significant bit data of the memory 33 as convergence correction data or display pattern data.
Is a switch for selecting whether to use the least significant bit data of the memory 43 as convergence correction data or display pattern data.

Reference numeral 53 denotes a CPU for reading and writing operations of the memories 33 and 43 and controlling various arithmetic operations.
It is. 103 is a display device. In addition, 1 to
2, 9, and 11 perform the same operation as that in FIG.

The operation for adjusting the convergence of red will be described below. At the time of red convergence adjustment, the pattern data is written to the least significant bit of the memory 43 by the operation of the CPU 53. The convergence correction data is written in the least significant bit of the memory 33.
The switches 50 and 51 are switched by the operation of the CPU 53, and the least significant bit data of the memory 43 is transferred to the video signal processing circuit 39 via the switch 51 and stored in the memory 33.
Of the least significant bit of D /
A converter 34 is connected to each.

Since the memory 43 is read out in synchronization with the raster scan by the operation of the address generator 2, the display pattern data written in the least significant bit of the memory 43 is displayed on the screen of the red cathode ray tube 38. . In addition,
Nothing is displayed on the screen of the blue cathode ray tube 48. In this case, the least significant bit of the red memory 33 is used as convergence correction data, so that red convergence adjustment can be performed without causing image quality deterioration.

Similarly, when performing the convergence adjustment for blue, the switches 50 and 51 are switched in the opposite direction, and the display pattern data written in the least significant bit of the memory 33 is displayed on the screen of the blue cathode ray tube 48. However, nothing is displayed on the screen of the red cathode ray tube 38. Therefore, since the least significant bit of the blue memory 43 is used as convergence correction data, it is possible to perform blue convergence adjustment without deteriorating image quality.

When the convergence adjustment is completed, the CPU
By the operation of 53, the convergence correction data is written to the least significant bits of both the memories 33 and 43. Also, CP
By operating U53, switches 50 and 51 are switched,
The least significant bit data of the memories 33 and 43 are connected to D / A converters 34 and 44, respectively. Then, the display device 103 connects the video signal input from the video signal input terminal (not shown) to the video signal processing circuits 39 and 49,
An image is displayed on the screens of the cathode ray tubes 38 and 39. Therefore, in the convergence correction operation at the time of normal screen display, the image quality does not deteriorate for both red and blue.

According to this embodiment, a specific pattern signal can be formed on the screen of the cathode ray tube with a simple circuit configuration without providing a display pattern generator having a large circuit scale and without deteriorating the image quality at the time of convergence adjustment. Can be displayed. Further, by rewriting the display pattern data, it is possible to display an arbitrary complicated pattern.

Next, a description will be given of a third embodiment of the present invention applied to automatic convergence correction for automatically performing a convergence adjustment operation for obtaining a convergence correction value. FIG. 4 is a configuration diagram showing the configuration of the third embodiment of the present invention.

In FIG. 4, reference numeral 60 denotes a convergence detector, such as a television camera or a photo sensor, for observing the display screen of the cathode ray tube 8 and detecting a convergence state on the screen. Reference numeral 61 denotes a CPU that performs reading and writing operations of the memory 3 and various arithmetic controls. 104 is a display device. Otherwise, the configuration is the same as that in FIG.

First, the operation at the time of automatic convergence adjustment will be described. During automatic convergence adjustment, C
By operating the PU 61, pattern data suitable for automatic convergence adjustment is written to the least significant bit of the memory 3. The switch 20 is switched by the operation of the CPU 61, and the least significant bit data of the memory 3 is connected to the video signal processing circuit 13.

Since the memory 3 is read out in synchronization with the raster scan by the operation of the address generator 2, the pattern data written in the least significant bit of the memory 3 and suitable for automatic convergence correction is displayed on the screen of the cathode ray tube 8. Is done. The data other than the least significant bit of the memory 3 is
As in the case of the first embodiment (FIG. 1) of the present invention, the signal is sent to the D / A converter 7 to correct the convergence of the cathode ray tube 8.

The CPU 61 determines the convergence state based on the result of the convergence detector 60 detecting the display pattern data suitable for automatic convergence correction displayed on the screen of the cathode ray tube 8, and thereby determines the memory 3
By automatically rewriting the convergence correction data in, the convergence adjustment is automatically performed.

After the automatic convergence adjustment is completed, the least significant bit data in the memory 3 is connected to the D / A converter 4 as in the case of the first embodiment (FIG. 1) of the present invention, and the normal video display is performed. Is performed. That is, the display device 104 converts the video signal input from the video signal input terminal (not shown) into the video signal processing circuit 13.
To display an image on the screen of the cathode ray tube 8.

According to the present embodiment, an automatic convergence correction device that needs to display a complicated pattern signal can be realized with a simple circuit configuration.

[0046]

According to the present invention, it is not necessary to provide a display pattern generator having a large circuit scale, so that a display device having an inexpensive digital convergence correction device can be provided. Further, it is possible to display a complicated pattern such as a character and improve operability at the time of convergence adjustment. Furthermore, a display device having an automatic convergence correction device that requires a complicated pattern display can be realized at a low cost with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a display device having a conventional digital convergence correction device.

FIG. 3 is a configuration diagram showing a configuration of a second example of the present invention.

FIG. 4 is a configuration diagram showing a configuration of a third example of the present invention.

[Explanation of symbols]

2 ... address generator, 3 ... memory, 4 ... D / A converter,
5 LPF (low-pass filter), 6 amplifier, 7 convergence yoke, 8 cathode ray tube, 20 switch
21 CPU, 101, 103, 104 display device according to the present invention, 102 display device according to the prior art.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasushi Noguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Video Media Research Laboratories (72) Michitaka Osawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (56) References JP-A-2-44988 (JP, A) JP-A-4-319895 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB (Name) H04N 9/28

Claims (3)

(57) [Claims] 1. A display screen of a cathode ray tube is virtually divided into a plurality of regions, a convergence correction value of each of the divided regions is obtained in advance and written as digital correction data in a memory. In a display device having a digital convergence correction device for reading convergence and performing convergence correction on a display screen , the digital
To obtain the convergence correction value
At the time of presence adjustment, the lower
The bit area is not the digital correction data but the
Store convergence adjustment display pattern data
Used as a specific area, the lower order being the specific area of the memory
Convergence stored in the bit area
Display pattern data for raster scan of display screen
Synchronized readout and convergence on display screen of cathode ray tube
During the first operation for displaying the screen for adjusting the screen and the original operation of displaying the screen as the display,
Other remaining bits are also stored in the lower bit area, which is a part of the memory.
Write digital correction data in the same way as
Synchronized with the raster scan of the display screen from both areas
To read the digital correction data and
A second route for providing variance correction, and switching between the first route and the second route.
Means, and a digital converter characterized by comprising:
A display device having a presence correction device. 2. A digital convertase according to claim 1,
In a display device having a capacitance correction device, the display device has at least two first and second cathode ray tubes.
To, and the memory, a first route, a second route, switching
Means for at least a first set and a second set corresponding to a cathode ray tube.
It has two sets, and when adjusting the convergence of the first cathode ray tube, the first shade
The memory belonging to the first set prepared for the pole tube is the second set.
Switch to the root route and use it for convergence adjustment.
And a menu belonging to the second set prepared for the second cathode ray tube.
Switch the Mori to the first route and get convergence
It as to display an integer for display pattern on the first cathode-ray tube, during convergence adjustment of the second cathode-ray tube, the second shade
The memory belonging to the second set prepared for the pole tube is the second set.
Switch to the root route and use it for convergence adjustment.
And a menu belonging to the first set prepared for the first cathode ray tube.
Switch the Mori to the first route and get convergence
Means for switching the routes so as to display the adjustment display pattern on the second cathode ray tube.
Display with digital convergence correction device
Play equipment. 3. The digital computer according to claim 1, wherein
In a display device having a verence correction device
To obtain the convergence correction value.
Observe the CRT screen when adjusting the convergence
Convergence adjustment operation automatically
Automatic convergence adjustment means
Features digital convergence correction device
Display device.