JP3338457B2 - Vertical synchronization signal generation device and vertical synchronization signal generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronizing signal generating apparatus and a vertical synchronizing signal generating method in video processing suitable for generating a vertical synchronizing signal for video signal processing of a video tape recorder.

[0002]

2. Description of the Related Art Conventionally, in a video tape recorder (hereinafter, referred to as VTR as necessary), a vertical synchronizing signal formed in a video signal (composite signal) is extracted by using a well-known vertical signal separator circuit. Video signal processing synchronized with the obtained vertical synchronizing signal is performed. For example,
It is used as a reference signal for communication latch processing or a character generator in a digital signal processing circuit. Further, it is also used for communication timing on an internal bus and communication timing on an external bus connected to an editing machine when video processing or the like is configured using a plurality of microcomputers (multi-microcomputers).

[0003]

However, when a vertical synchronizing signal extracted using a separator circuit or the like as in the conventional example is used as it is, if the level or the like of an input video signal fluctuates, the extracted vertical synchronizing signal is used. The signal also fluctuates, and for example, characters such as date and time may flicker on the screen during variable speed reproduction of the VTR. Further, when the editing machine is connected, the communication timing and the video signal cannot be synchronized with each other, which makes it difficult to perform a normal operation on the editing machine. Furthermore, the communication La of the IC or the like and the communication timing of the bus
If the pitch is not normal screen obtained deviation has drawbacks such as that occurs.

The present invention has been made in view of the above problems, and performs timing information processing of a vertical synchronizing signal by one microcomputer, thereby completely synchronizing with an output video signal and ensuring a period required by a bus. It is an object of the present invention to provide a vertical synchronizing signal generation device in excellent video processing which can secure the vertical synchronizing signal continuously.

[0005]

According to the present invention, a vertical synchronizing signal generating apparatus according to the present invention controls the input timing of a supplied vertical synchronizing signal by:
The timing obtained by adding the first predetermined value which is the predetermined value of the period when the input video signal is supplied in the period of the vertical synchronization signal is obtained by adding the lower limit of the communication cycle of the internal bus or the external bus to the output timing. A determining unit that determines whether or not the signal is within a confirmation range between the timing and the timing obtained by adding the upper limit; and, when the determining unit determines that the vertical synchronization signal is within the confirmation range, the determination unit determines whether the input vertical synchronization signal is present. A first vertical synchronizing signal at a timing to which a first predetermined value is added is generated and transmitted, and when the determination unit determines that the vertical synchronizing signal does not exist within the confirmation range, a request is made through an internal bus or an external bus. Of the first predetermined value that satisfies the upper and lower limits of the communication cycle to be performed and that gradually shifts the output timing with respect to the timing obtained by adding the first predetermined value to the input vertical synchronization signal. 2 of a predetermined value is made and a vertical synchronizing signal generating means for transmitting and generates a second vertical synchronizing signal timing in addition to the previous output timing. According to the vertical synchronizing signal generation method of the present invention, the input vertical synchronizing signal timing is T _vin and the output vertical synchronizing signal timing is T
_vout , the lower limit of the bus communication cycle is T _min , the upper limit of the bus communication cycle is T _max , and the predetermined value of the cycle when the input video signal is supplied in the cycle of the vertical synchronization signal is T _xa ,
When the timing T _vin + T _{xa obtained} by adding a predetermined value to the timing of the input vertical synchronization signal is after T _vout + T _min and is within the confirmation range before T _vout + T _max , the timing T _vout = T _vin + T _xa. When the timing T _vin + T _{xa obtained} by adding a predetermined value to the input vertical synchronization signal timing does not exist after T _vout + T _min and before T _vout + T _max , the bus communication is performed. _{Is not} less than the lower limit T _min of the cycle and not more than the upper limit T _max of the communication cycle,
The second vertical synchronization is performed at a timing obtained by adding a predetermined value T _xb of a period excluding the vicinity of the predetermined value T _xa to the previous output timing T _vout so as to gradually shift the output timing with respect to the timing T _vin + T _xa . This is to generate a signal.

[0006]

According to the vertical synchronizing signal generating apparatus and the vertical synchronizing signal generating method in the video processing of the present invention, a supplied vertical synchronizing signal, for example, a vertical synchronizing signal extracted from an input video signal, or a VTR or the like for variable speed reproduction. If the pseudo vertical synchronizing signal is within the predetermined checking range, a first vertical synchronizing signal having a timing obtained by adding the first predetermined value to the vertical synchronizing signal is generated and transmitted, and the vertical synchronizing signal is checked by the determination unit. If it is determined that the communication cycle does not exist within the range, the upper and lower limits of the communication cycle required by the internal bus or the external bus are satisfied,
And a timing obtained by adding a second predetermined value excluding the vicinity of the first predetermined value, which gradually shifts the output timing with respect to the timing obtained by adding the first predetermined value to the input vertical synchronization signal, to the previous output timing The second vertical synchronizing signal is generated and transmitted, so that the timing information processing of the vertical synchronizing signal is performed by one microcomputer, so that it is completely synchronized with the output video signal and required by the bus. A vertical synchronizing signal whose cycle can be reliably ensured is continuously obtained.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a vertical synchronizing signal generating apparatus and a vertical synchronizing signal generating method in video processing according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a composite synchronizing signal separating circuit, which receives a video signal, for example, a video signal output from a television camera. You. The output signal here is input to the vertical synchronization signal timing measurement circuit 12, where the vertical synchronization signal timing information (signal) _Stm obtained by measuring the continuous vertical synchronization signal is obtained. This vertical synchronization signal timing information _Stm is supplied to the system controller 20.

[0009] The system controller 2 constituting the determination unit
0 is inputted vertical synchronizing signal timing information S _tm from the vertical synchronizing signal timing measurement circuit 12, a vertical synchronization signal generation information generating unit 22 for creating a vertical synchronizing signal generation information S _da, used during variable speed reproduction vertical Synchronization signal creation information
Pseudo vertical synchronizing signal creation information generating section 24 for generating S _tr
The communication timing that satisfies the upper and lower limits of the communication cycle required by the restrictions on the microcomputer processing time, etc. between the microcomputer and the internal bus which is the communication bus between the microcomputer and the IC or the external bus which is the communication bus with the editing machine etc. And a communication information generating unit 26 for generating transmission / reception information by a software algorithm.

Furthermore, the vertical synchronizing signal created generated by the vertical synchronization signal generation information generating unit 22 of the system controller 20 information S _da is inputted, the vertical synchronizing signal Sa output from here (hereinafter, referred to as the output vertical synchronizing signal) Synchronization signal generating circuit 3 for sending the video signal to a video signal processing IC or the like
0 is provided. Further, pseudo vertical synchronizing signal generation information (signal) S for variable speed reproduction generated by the pseudo vertical synchronizing signal generation information generating unit 24 by a software algorithm.
_It has a pseudo vertical synchronizing signal creation circuit 32 that receives _tr and generates and sends out a pseudo vertical synchronizing signal Sb.

The operation of the vertical synchronizing signal generating apparatus and the vertical synchronizing signal generating method having the above-described configurations will be described. FIG. 2 is a timing chart relating to signal processing when the output vertical synchronization signal Sa is obtained by the system controller 20, and FIG.
It is the flowchart. In FIG. 2, here,
The input vertical synchronization signal timing of the vertical synchronization signal timing information _Stm from the vertical synchronization signal timing measurement circuit 12 or the pseudo vertical synchronization signal creation information _Str from the pseudo vertical synchronization signal creation information generation unit 24 is _Tvin . Further, T _vout is the output timing which is the falling point of the synchronization signal pulse for creating the output vertical synchronization signal Sa from the vertical synchronization signal creation circuit 30 by hardware, and the information created by the communication information generation unit 26, that is, The lower limit of the communication cycle of the internal bus or the external bus is T _min , and the upper limit is T _min.
and _max, further the period of the vertical synchronizing signal and T _x.

Next, a processing procedure for creating a vertical synchronization signal will be described. First, as shown in FIG. 3, when a vertical synchronization signal is supplied, in step 101, the vertical synchronization signal creation information generation unit 22 determines that the input timing T _{vin of} the supplied vertical synchronization signal is within a predetermined confirmation range (check). Window) (step 101). Here, the output timing T of the previously output vertical synchronization signal
_{The time when} the lower limit cycle T _{min of the} bus has elapsed from _vout is T
and _vout + T _min, when the time elapsed since the output timing of the previous output vertical synchronizing signal only limit period T _max of the bus and T _vout + T _max, the input timing T _vin,
If it is not _{less than} T _vout + T _min and not more than T _vout + T _max, it is determined that it is within the confirmation range (step 1).
01-YES), and conversely, the input timing T _vin is T _vout
If the time is before + T _min or after T _vout + T _max , it is determined that it is not within the confirmation range (step 101 -NO).

If it is determined in step 101 that the input timing T _vin is within the confirmation range, a predetermined period equal to the period T _x of the input vertical synchronizing signal as shown in FIG. T first vertical synchronizing signal _xa is, T of the previous output timing T _vout from the predetermined period T _xa only elapsed time [T _vout = previous value of the vertical synchronizing signal
_vout + _Txa ], the vertical synchronizing signal generation information generation unit 22 generates the vertical synchronizing signal generation information _Sda (step 102). That is, when the input timing T _vin of the vertical synchronization signal is within the confirmation range, the output vertical synchronization signal Sa is output at a period equal to the period T _x of the input vertical synchronization signal, and the output vertical synchronization signal Sa is output. Signal S
a is suitable for the vertical synchronization signal timing information _Stm or the pseudo vertical synchronization signal information _Str .

If it is determined in step 101 that the input timing T _vin is not within the confirmation range,
T of the second vertical synchronizing signal timing has elapsed from the output timing of the previous vertical synchronizing signal by a predetermined period T _xb [T _vout = previous value of a predetermined period T _xb as shown in (b) of FIG. 2 _vout + T _xb ], the vertical synchronizing signal generation information generation unit 22 generates the vertical synchronizing signal generation information _Sda (step 103). Here, the predetermined period T _xb of the second vertical synchronization signal is a value that satisfies T _min ≦ T _xb ≦ T _max and takes a value different from the period T _{xa of} the first vertical synchronization signal. That is, even when the input vertical synchronizing signal is not within the confirmation range, the output vertical synchronizing signal Sa that can reliably secure the timing required on the bus can be output without interruption.

In this manner, the timing information processing of the vertical synchronization signal is performed by one microcomputer, and the vertical synchronization signal completely synchronized with the output video signal can be continuously obtained. Eliminates flickering of characters on the display screen during variable speed playback. The data bus communication timing and the video signal when the editor is connected
Imming can be performed, and the inoperability of the editing machine can be prevented. Also, since the vertical synchronizing signal is created by a microcomputer program, the timing of the vertical synchronizing signal
This makes it easy to change the timing of the vertical synchronizing signal when performing processing of another television broadcasting system.

[0016]

As will be understood from the above description, the vertical synchronizing signal generating apparatus in the video processing according to the present invention uses the supplied vertical synchronizing signal, for example, the vertical synchronizing signal extracted from the input video signal, or predetermined timing when the pseudo vertical synchronizing signal for variable speed reproduction mode such as a VTR, it is determined whether present within the confirmation range of the predetermined timing, the vertical synchronization signal is present in the confirmation range of a predetermined timing <br/> of generating a vertical synchronizing signal and sent out, and when the vertical synchronizing signal is not in the check range, the vertical synchronizing signal is a predetermined Thailand
Since the vertical synchronization signal different from the predetermined timing when it is within the confirmation range of the video signal is generated and transmitted, by performing the timing information processing of the vertical synchronization signal by one microcomputer, the output video signal and the There is an advantage that a vertical synchronization signal that is completely synchronized and that can reliably secure the timing required on the bus can be continuously obtained.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing one embodiment of a vertical synchronizing signal creation device in video processing of the present invention.

FIG. 2 is a timing chart related to an output vertical synchronizing signal creation process for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a flowchart showing a vertical synchronizing signal creation process for explaining the operation of the embodiment shown in FIG. 1;

[Explanation of symbols]

REFERENCE SIGNS LIST 10 composite sync signal separation circuit 12 vertical sync signal timing measurement circuit 20 system controller 22 vertical sync signal creation information generation section 24 pseudo vertical sync signal creation information generation section 26 communication information generation section 30 vertical sync signal creation circuit 32 pseudo vertical sync signal creation Circuit Sa Output vertical synchronization signal Sb Pseudo vertical synchronization signal _Stm Vertical synchronization signal timing information S _tr Pseudo vertical synchronization signal creation information _Sda Vertical synchronization signal creation information

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-56-119578 (JP, A) JP-A-56-120268 (JP, A) JP-A-60-111577 (JP, A) JP-A-1- 133487 (JP, A) JP-A-1-292969 (JP, A) JP-A-2-194774 (JP, A) JP-A-2-202778 (JP, A)

Claims (2)

(57) [Claims] 1. A timing obtained by adding a first predetermined value which is a predetermined value of the above-mentioned period when an input video signal is supplied in the period of the vertical synchronization signal to the input timing of the supplied vertical synchronization signal. A determination unit that determines whether the output timing is within a confirmation range between the timing obtained by adding the lower limit of the communication cycle of the internal bus or the external bus and the timing obtained by adding the upper limit, and a vertical synchronization signal that is determined by the determination unit. Is determined to be within the confirmation range, a first vertical synchronizing signal having a timing obtained by adding the first predetermined value to the input vertical synchronizing signal is generated and transmitted, and the vertical synchronizing signal is determined by the determination unit. If it is determined that the signal does not exist within the confirmation range, the upper and lower limits of the communication cycle required by the internal bus or the external bus are satisfied, and a first predetermined value is added to the input vertical synchronization signal. The second predetermined value of said period excluding the vicinity of said first predetermined value that shifts the output timing gradually relative timing of timing plus the previous output timing 2
A vertical synchronizing signal generation device for video processing, comprising: a vertical synchronizing signal generating means for generating and transmitting the vertical synchronizing signal. 2. The input vertical synchronizing signal timing is T _vin ,
When the output vertical synchronization signal timing is T _vout , the lower limit of the bus communication cycle is T _min , the upper limit of the bus communication cycle is T _max , and the input video signal is supplied in the cycle of the vertical synchronization signal, the predetermined period is specified. _Assuming that the value is T _xa , the timing T _vin + T _{xa obtained} by adding the above predetermined value to the timing of the input vertical synchronization signal is T _vout + T _min or later,
And when it is within the confirmation range before T _vout + T _max ,
A first vertical synchronization signal at the timing T _vout = T _vin + T _xa is generated, and a timing T _vin + T _{xa obtained} by adding the above-described predetermined value to the input vertical synchronization signal timing is equal to or later than T _vout + T _min and T
_{When vout} + T _max not previously exist, not more than the upper limit T _max of the communication cycle is lower than the lower limit T _min of the communication cycle of the bus, and that shifts gradually output timing with respect to the timing T _vin + T _xa, the predetermined Excluding the vicinity of the value T _xa
A vertical synchronizing signal generation method , characterized in that a second vertical synchronizing signal is generated at a timing obtained by adding the predetermined value _{Txb of the} cycle to the previous output timing _Tvout .