JP3338899B2 - Method for manufacturing charged particle exposure mask - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved method for manufacturing a charged particle exposure mask.

In recent years, with the increase in the density of integrated circuits, exposure using charged particle beams, for example, electron beams or ion beams, or new exposure using X-rays has replaced the photolithography method, which has been the mainstream for forming fine patterns for many years. Methods have been studied and put to practical use. Of these, electron beam exposure, which uses electron beams to form patterns,
Since the beam itself can be reduced to a size of several Å, a significant feature is that a fine pattern of 1 μm or less can be formed. However, since electron beam exposure is a so-called "one-stroke" drawing method, the finer the pattern, the smaller the beam must be used for exposure, and the exposure time is extremely long.

In order to solve this problem, a stencil mask (hereinafter, referred to as a block mask) having a block pattern including a plurality of transmission hole patterns corresponding to various patterns repeatedly appearing in an exposure pattern is provided in an exposure apparatus. A block exposure method has been proposed in which a desired block pattern is selected from the patterns, and an electron beam having a large beam diameter is applied to the pattern to generate a shaped beam for exposure. The present invention relates to a method for manufacturing a charged particle exposure mask used in the block exposure method.

[0004]

2. Description of the Related Art Several methods have been proposed as methods for manufacturing a charged particle exposure mask. One of the methods will be described below.

As shown in FIG. 3A, _two silicon substrates 1 and 3 are bonded together via an SiO ₂ insulating layer 2 and one of the silicon substrates 1 is thinned to form a silicon-on-inductor (SOI) substrate. Form.

As shown in FIG. 3B, an SiO ₂ film 4 is formed on a thinned silicon substrate 1, and then a SiN film 5 is formed on the entire surface.

As shown in FIG. 4A, an opening 6 is formed in the SiN film 5 on the thick silicon substrate 3 using a dry etching method, and then the silicon substrate 3 is etched using KOH. I do. At this time, the SiO ₂ layer 2 functions as an etching stopper.

As shown in FIG. 4B, after removing the SiN film 5 using phosphoric acid, the SiO ₂ film 4 is patterned using a dry etching method, and an opening 7 is formed in a block pattern formation region. Form.

As shown in FIG. 5A, the thinned silicon substrate 1 is dry-etched using the SiO ₂ film 4 as a protective film to form a block pattern 8 on the thinned silicon substrate 1. .

As shown in FIG. 5B, the SiO ₂ film 4 and the exposed SiO ₂ insulating layer 2 are removed using hydrofluoric acid.

When manufacturing a block mask having a through-hole, not limited to the above-described manufacturing method, a dry etching step for forming the through-hole 8 in the thinned silicon substrate 1 is required. The thickness of the thinned silicon substrate 1 is generally 15 to 20 μm in consideration of the strength and the like. On the other hand, the thickness of the SiO ₂ film 4 used as a protective film for dry etching is preferably as large as possible, but there is a limit to the thickness of the resist film used to form the opening 7 in the SiO ₂ film 4. Considering this, it must be about 1 μm.

Therefore, the selectivity between SiO ₂ and silicon in the dry etching step for forming the through holes 8 in the thinned silicon substrate 1 needs to be 15 to 20 or more. There are several possible etching gases that satisfy this condition. However, bromination is judged based on the fact that the etching rate is high and the etching shape is not a taper type but a barrel type, which is convenient as a beam forming mask. Hydrogen (HBr) and the like are the most promising.

[0013]

When silicon is etched, a phenomenon called black silicon may occur in which foreign substances accumulate on the etched surface during the etching and the etching does not proceed.
HBr is a gas in which this phenomenon is most likely to occur.

Although the cause of the occurrence of black silicon has not yet been determined, its occurrence tends to depend on the size of the area of the pattern to be etched on the substrate, and if the total area of the pattern to be etched is different, The optimum etching conditions for preventing generation of black silicon vary. Therefore, in order to etch a plurality of substrates having different total areas of a pattern to be etched so that black silicon is not generated, an etching gas amount, an etching chamber pressure, a substrate temperature, and the like corresponding to the total area of the pattern are required. It is necessary to change each etching condition. As a method, several types of reference pattern areas are selected in advance, optimal conditions corresponding to the respective reference pattern areas are determined by experiments, and when actually etching a substrate having various pattern areas, the pattern area is determined. A method is conceivable in which a reference pattern having an area closest to the reference pattern is selected, and etching is performed using etching conditions corresponding to the reference pattern. However, there is a considerable difference in the area of the pattern to be etched depending on the substrate. Therefore, in order to cover all of them, it is necessary to select the worst + several types of reference patterns and find the etching conditions corresponding to them. Not a target. what if,
Even if the conditions are determined, it is difficult to use them properly during mass production.

On the other hand, when a block mask is manufactured using an SOI substrate in which two silicon substrates 1 and 3 are bonded via an insulating layer 2, the two silicon substrates are insulated from each other. When the electron beam is irradiated on the silicon substrate 1 which has been thinned to a thickness of about 20 μm and has a high resistance value, there is a drawback that the mask surface is easily charged up because there is no escape route of the electric charge.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate this drawback and to simplify the etching process by reducing the types of optimum etching conditions when forming block patterns having different areas on a thinned silicon substrate. Another object of the present invention is to provide a method for manufacturing a charged particle exposure mask that prevents charge-up from occurring on a mask surface when a block mask is formed using an SOI substrate.

[0017]

The above object is achieved by any of the following means.

The first means is to form a plurality of through-hole patterns (24) corresponding to a part of an integrated circuit on the thinned silicon substrate (12) by thinning a partial region of the silicon substrate. In a method of manufacturing a mask for particle exposure,
The difference の between the total area S of the plurality of through-hole patterns (24) and a predetermined reference area S ₀ (where S ₀ > S).
S = S ₀ -S is calculated, and the auxiliary pattern (15) having the same area as the difference ΔS is added to the thinned silicon substrate (1).
This is a method for manufacturing a charged particle exposure mask formed in a peripheral region of 2).

The second means is to manufacture a charged particle exposure mask for thinning a partial region of a silicon substrate and forming a plurality of transmission hole patterns corresponding to a part of an integrated circuit on the thinned silicon substrate. In the method, the silicon substrate is divided into a plurality of sections, and for each of the divided sections, a plurality of transmission hole patterns (19a or 19b or 19c or 19d) formed in the section.
And a predetermined reference area S ₀ ′ (however,
S ₀ ′> S ′) and a difference △ S ′ = S ₀ ′ −S ′, and an auxiliary pattern (20a or 20b or 20c or 20d) having the same area as the difference △ S ′ is divided into the respective sections. Thinned silicon substrate (17a or 1)
7b or 17c or 17d) is a method for manufacturing a charged particle exposure mask formed in the peripheral region.

The two silicon substrates (1 and 3) are bonded via the insulating layer (2) to make one of the silicon substrates (1) thinner. The transmission hole pattern (8) using the method for manufacturing a charged particle exposure mask described in the first means or the second means.
In the case of forming the auxiliary pattern (10), a conductive substance (20) is deposited on the inner surface of the auxiliary pattern (10) to make the two silicon substrates (1 and 3) conductive. , Charging up can be prevented.

If it is found that black silicon is generated when the total area S of the plurality of transmission hole patterns is larger than a certain size Slimit, a mask having the total area S of the transmission hole patterns larger than Slimit is used. Means that etching cannot be performed by the above-described means, and the number and area of transmission hole patterns arranged on the mask are limited. The solution to this problem is achieved by the following third to fifth means.

The third means is to form a thin film on a part of the silicon substrate and form a plurality of through-hole patterns (24) corresponding to a part of the integrated circuit on the thinned silicon substrate (12). In a method of manufacturing a mask for particle exposure,
A difference ΔS = S−S ₀ between the total area S of the plurality of through-hole patterns (24) and a predetermined reference area S ₀ (where S ₀ <S) is calculated, and the difference ΔS A plurality of island-shaped remaining patterns (23) having the same total area as the above are formed inside the plurality of through-hole patterns (24), and are used as etching through-hole patterns (22). This is a method for manufacturing a charged particle exposure mask that forms a plurality of transmission hole patterns (24).

[0023]

[0024]

[0025]

In the first and second means, the total area of the pattern to be etched on the substrate is reduced to one or several reference areas by forming an auxiliary pattern in addition to the originally required block pattern. Therefore, the etching conditions to be optimized can be suppressed to one or several types.

If the substrate is divided into a plurality of sections and the auxiliary patterns are formed so that the sum of the area of the block pattern and the area of the auxiliary pattern in each section becomes equal, the distribution density of the pattern to be etched is reduced. Averaging on the substrate prevents local black silicon from occurring.

In the case where the mask is manufactured using an SOI substrate, a conductive material is deposited on the inner surface of the auxiliary pattern so that the mask is bonded via an insulating layer.
The silicon substrates are brought into conduction, and charge-up on the mask surface is prevented.

In the third means, the total area of the etching through-hole patterns 22 is smaller than the total area S of the plurality of through-hole patterns 24 by forming an island-shaped residual pattern, and is arbitrarily set. can do.
Therefore, it is possible to select an etching area so that black silicon is not generated at the time of etching, and the problem that the number and area of the transmission hole patterns are restricted is avoided. Further, since the remaining pattern 23 is formed in an island shape, the etching through-hole pattern 2 is formed.
When the portion 2 is penetrated by etching, the portion of the remaining pattern 23 is removed at the same time, so that no extra unetched portion remains in the transmission hole pattern. Conversely, unnecessary patterns do not occur on the mask substrate.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a charged particle exposure mask according to one embodiment of the present invention will be described below with reference to the drawings.

First Example See FIG. 4 (a) The same steps as in the prior art are performed to form a shape shown in FIG. 4 (a).

Referring to FIG. 6A, the SiN film 5 is removed using phosphoric acid, and dry etching is performed.
SiO method using _TwoPattern the film 4 and block
The opening 7 is formed in the mask pattern forming area,
An opening 9 is formed in the formation region. The block pattern type
Area of opening 7 in formation region and opening 9 in auxiliary pattern formation region
Is the reference area S₀To be equal to
The size of the opening 9 in the auxiliary pattern formation region is determined.

Referring to FIG. 6B, the thinned silicon substrate 1 is dry-etched using the SiO ₂ film 4 as a protective film, and the thinned silicon substrate 1 is formed.
Then, a block pattern 8 and an auxiliary pattern 10 are formed.

Referring to FIG. 7A, the SiO ₂ film 4 and the exposed SiO ₂ insulating layer 2 are removed using hydrofluoric acid. As a result, the block pattern 8 is formed on the thinned silicon substrate 1, and the auxiliary pattern 10 is formed in the peripheral region.

FIG. 1 is a plan view of a block mask. In the figure,
Reference numeral 11 denotes a silicon substrate, 12 denotes a thinned region of the silicon substrate, 13 denotes a non-thinned region, 14 denotes a block pattern including a plurality of transmission hole patterns 24, and 15 denotes an auxiliary pattern. It is. The area of the auxiliary pattern 15 is selected such that the sum of the total area of the block pattern 14 and the area of the auxiliary pattern 15 becomes the reference area S ₀ .

Second Example See FIG. 2 A silicon substrate is divided into a plurality of sections, for example, four sections 16a.
It is divided into 16b, 16c and 16d. Four sections 16a
16b, 16c, 16d are respectively composed of thinned regions 17a, 17b, 17c, 17d and non-thinned regions 18a, 18b, 18c, 18d. Thinned regions 17a, 17b, 17c, 17d
Include block patterns 19a and 19a each having a different area.
19b, 19c, and 19d are formed, and auxiliary patterns 20a, 20b, 20c, and 20c having different sizes are formed on the thick film regions 18a, 18b, 18c, and 18d, respectively.
20d are formed. In this example, the area of the auxiliary pattern is changed by increasing or decreasing the number of rectangular patterns having the same size. However, this method is not necessarily required. As the total area of the block pattern and the auxiliary pattern in each compartment equal to each other, also, the total area of the block pattern and the auxiliary patterns of all compartments of the respective auxiliary patterns to be equal to the reference area S ₀ Select the area.

Third Example See FIG. 7B When a conductive material 21 such as tungsten, tantalum or gold is deposited on the block mask shown in FIG. 7A as shown in FIG. ₍₂ ) The upper and lower two silicon substrates 1 and 3 insulated from each other with the insulating layer 2 interposed therebetween are brought into a conductive state by the conductive substance 21 deposited on the inner surface of the auxiliary pattern 10, and when the charged particle beam is irradiated, the upper and lower silicon substrates 1 and 3 Is prevented from occurring.
Note that the conductive substance deposited on the thinned silicon substrate 1 does not need to be removed. This is because there is an effect of substantially lowering the resistance value of the silicon substrate 1 which has become thinner and has a larger resistance value, and also has an effect of preventing charge-up.

Fourth Example See FIG. 8 In the figure, 11 is a silicon substrate, 12 is a thinned region of the silicon substrate, and 14 is a block pattern comprising a plurality of transmission hole patterns 24. The shaded region 22 is a transmission hole pattern for etching,
There is an island-shaped remaining pattern 23 inside. The combination of the etching through-hole pattern 22 and the island-shaped remaining pattern 23 corresponds to the shape of the through-hole pattern 24 formed after etching. Since the total area of the etching through-hole patterns 22 only needs to be equal to the reference area S ₀ , the island-shaped residual pattern 23 is present in a case where a plurality of the inside of one through-hole pattern 24 is present, or when there is no present. There may be.

[0038]

[0039]

[0040]

[0041]

As described above, in the method of manufacturing a charged particle exposure mask according to the present invention, the size of the area to be etched can be adjusted to the reference area where black silicon is not generated. Is selected from one or several types, the etching conditions depending on the etching area can be suppressed to one or several types, and the etching process can be simplified. In addition, when forming an auxiliary pattern, a conductive material is deposited on the inner surface, so that charge-up on the mask surface can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view of a charged particle exposure mask.

FIG. 2 is a plan view of a charged particle exposure mask.

FIG. 3 is a manufacturing process diagram of a charged particle exposure mask according to the related art.

FIG. 4 is a manufacturing process diagram of a charged particle exposure mask according to a conventional technique.

FIG. 5 is a manufacturing process diagram of a charged particle exposure mask according to the related art.

FIG. 6 is a manufacturing process diagram of the charged particle exposure mask according to the present invention.

FIG. 7 is a manufacturing process diagram of the charged particle exposure mask according to the present invention.

FIG. 8 is a plan view showing a shape of a transmission hole pattern for etching.

[Explanation of symbols]

Reference Signs List 1 thinned silicon substrate 2 insulating layer 3 silicon substrate 4 SiO ₂ film 5 SiN film 6.7.9 opening 8 block pattern 10 auxiliary pattern 11 silicon substrate 12 thinned region 13 non-thinned region 14 block pattern 15 Auxiliary pattern 16a, 16b, 16c, 16d Divided section 17a, 17b, 17c, 17d Thinned area 18a, 18b, 18c, 18d Non-thinned area 19a, 19b, 19c, 19d Block pattern 20a, 20b, 20c・ 20d auxiliary pattern 21 conductive material 22 etching transmission hole pattern 23 island-shaped remaining pattern 24 transmission hole pattern

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-243118 (JP, A) JP-A-4-216613 (JP, A) JP-A-2-114512 (JP, A) JP-A-57- 162332 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/027 G03F 1/16

Claims (4)

(57) [Claims] 1. A charged particle exposure mask for thinning a partial region of a silicon substrate and forming a plurality of transmission hole patterns (24) corresponding to a part of an integrated circuit on the thinned silicon substrate (12). In the manufacturing method, the difference と between the total area S of the plurality of transmission hole patterns (24) and a predetermined reference area S ₀ (where S ₀ > S)
S = S ₀ −S is calculated, and an auxiliary pattern (15) having the same area as the difference ΔS is formed on the thinned silicon substrate (12).
Forming a charged particle exposure mask in a peripheral region of the mask. 2. A method of manufacturing a charged particle exposure mask, wherein a part of a silicon substrate is thinned and a plurality of transmission hole patterns corresponding to a part of an integrated circuit are formed on the thinned silicon substrate. The silicon substrate is divided into a plurality of sections, and for each of the divided sections, a total area S ′ of a plurality of transmission hole patterns (19a or 19b or 19c or 18d) formed in the section is predetermined. Difference △ S ′ from reference area S ₀ ′ (however, S ₀ ′> S ′)
= S ₀ '-S', and an auxiliary pattern (20a or 20b or 20c or 20c) having the same area as the difference ΔS 'is calculated.
d) is formed in a peripheral region of a thinned silicon substrate (17a or 17b or 17c or 17d) in each of the sections. 3. The two silicon substrates (1 and 3) are bonded together via an insulating layer (2) to make one of the silicon substrates (1) thinner. Claim 1 or 2
Forming a transmission hole pattern (8) and an auxiliary pattern (10) using the method for manufacturing a charged particle exposure mask described above, and depositing a conductive material (20) on the inner surface of the auxiliary pattern (10). A method for producing a charged particle exposure mask, comprising: 4. A charged particle exposure mask for thinning a partial area of a silicon substrate and forming a plurality of transmission hole patterns (24) corresponding to a part of an integrated circuit on the thinned silicon substrate (12). In the manufacturing method, the difference 総 between the total area S of the plurality of transmission hole patterns (24) and a predetermined reference area S ₀ (where S ₀ <S).
Calculates S = S-S _0, to form a said difference △ S and total area are equal plurality of island-like residual patterns (23) inside the plurality of transmission hole pattern (24), etching it Forming a plurality of through-hole patterns (24) by using the plurality of through-hole patterns (24) as a through-hole pattern (22).