JP3339215B2 - Thinned clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thinning clock generation circuit for generating a thinning clock for thinning out pixels in image data when, for example, a copying machine reduces read image data and records it on recording paper. It is about.

[0002]

2. Description of the Related Art For example, in a copying machine, when reading image data on a document is reduced in the main scanning direction and recorded on recording paper, pixel data constituting each line data in the reading image data is reduced at a reduction rate. The pixel data is decimated accordingly so as not to be recorded on the recording paper.

For example, in a case where read image data on a document is temporarily stored in a page memory and then transferred to a recording unit, the read image data in the page memory is read line by line as shown in FIG. Clock signal CLK for reading
Are sequentially read out one pixel at a time in synchronization with. Then, the transfer image data is sequentially input to the recording unit one pixel at a time in synchronization with the thinning-out clock signal SCLK for writing created by the thinning-out clock generation circuit based on the clock signal CLK.

[0004] The thinned clock signal SC for writing is
LK is obtained by thinning out the pulses of the read clock signal CLK at predetermined intervals. Pixel data transferred in synchronization with the thinned out pulses is not allowed to be input to the recording unit. Is thinned out. Then, by inputting the pixel data transferred from the page memory to the recording unit in a state where the pixel data is thinned out by the thinning clock signal SCLK, the read image data can be reduced and printed in the main scanning direction.

Conventionally, the following thinning clock generation circuit has been used to generate the above thinning clock signal SCLK. This conventional thinning clock generation circuit generates and outputs a thinning clock signal SCLK based on a pattern data for thinning as shown in FIG. 4 and a clock signal CLK for reading. The pattern data for thinning is stored in the memory in advance corresponding to each of the plurality of reduction ratios.
Then, the thinning clock generation circuit reads the pattern data corresponding to the designated reduction ratio from the memory, and thins out a signal which becomes H level only when both the read pattern data and the clock signal CLK become H level. Output as clock signal SCLK.

For example, FIG. 4 shows an example in which read image data of a B4 size document is reduced so that it can be recorded on A4 size recording paper. In this case, the reduction ratio is 27/32 (=
1728/2048). When such a reduction ratio is set, pattern data of L level is read out corresponding to five pulses of the 32 pulses of the clock signal CLK. Therefore, based on the pattern data and the clock signal CLK, five pulses of the 32 pulses of the clock signal CLK are thinned out and output as the thinned clock signal SCLK.

Conventionally, as a thinned-out clock generation circuit, there is a circuit using a decoder which thins out a predetermined pulse of an input clock signal CLK based on a count value of a counter and outputs the thinned clock signal SCLK. The counter performs a counting operation in synchronization with the clock signal CLK. For example, as described above, when 27/32 is set as the reduction ratio, 3
Use a binary counter. Then, the count value of the counter is set to “6, 13, 19, 26, 3” by the decoder.
In this case, the pulses of the clock signal CLK at the time of "2" are thinned out and output as the thinned clock signal SCLK.

[0008]

However, in the prior art, in the former case, it is necessary to store a plurality of thinning-out pattern data in a memory corresponding to a plurality of reduction ratios. For this reason, when there are many reduction ratios, there is a problem that a large-capacity memory is required for storing a large number of pattern data. In the latter case, the thinned-out clock signal SCLK corresponding to each of the plurality of reduction rates cannot be generated by only one counter or decoder. For this reason, if the reduction ratio increases, it becomes necessary to provide a plurality of counters and decoders, and there has been a problem that the circuit configuration becomes complicated.
As described above, conventionally, in order to be able to cope with a large number of reduction ratios, the capacity of the memory has to be increased and the configuration has been complicated, and the manufacturing cost has been increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to make it possible to easily create a thinned-out clock signal corresponding to an arbitrary reduction ratio, and to further obtain pattern data for thinning-out. It is an object of the present invention to provide a thinned-out clock generation circuit which does not need to be provided with a memory for storing the clock, and has a simple configuration.

[0010]

In order to achieve the above object, according to the first aspect of the present invention, when the value of the reduction ratio is n / m, mn is added in synchronization with the pulse of the clock signal. , And a calculating means for subtracting n from the addition result when the addition result becomes n or more, and a thinning means for thinning out the pulse of the clock signal at the time of the subtraction and outputting it as a thinning clock.

According to the second aspect of the present invention, the calculating means adds mn to its output value in synchronization with the pulse of the clock signal.
Is added as a new output value, and the thinning-out means thins out the next pulse of the clock signal when the output value from the arithmetic means becomes n or more, and issues a subtraction instruction to the arithmetic means, The calculating means subtracts n from the output value in synchronization with the next pulse of the clock signal based on the subtraction command.

According to a third aspect of the present invention, based on the input of the initial value, the calculating means performs the adding operation using the initial value as the first output value.

[0013]

Therefore, according to the first aspect of the present invention, when the value of the reduction ratio is n / m, the calculating means adds mn at a time in synchronization with the pulse of the clock signal, and the addition result is When it becomes n or more, n is subtracted from the addition result. The thinning means thins out the pulse of the clock signal at the time of the subtraction and outputs the thinned clock. For example, when the value of the reduction ratio is 3/5, the calculation unit synchronizes with the pulse of the clock signal and outputs the calculation result as “2.4”.
・ 2 ・ 4 ・ 2 ... 」. In the thinning means, the pulses of the clock signal are thinned out at the time of the subtraction by the arithmetic means, that is, when the operation result is subtracted from 4 to 2. As a result, a thinned clock in which two pulses out of five pulses of the clock signal are thinned out is output.

According to the second aspect of the present invention, the arithmetic means includes:
In synchronization with the pulse of the clock signal, the output value of
n is added and output as a new output value. In the thinning means, when the output value from the arithmetic means becomes n or more, the next pulse of the clock signal is thinned and a subtraction instruction is issued to the arithmetic means. Then, the arithmetic means subtracts n from the output value in synchronization with the next pulse of the clock signal based on the subtraction command.

According to the third aspect of the present invention, the pulse position to be thinned out can be arbitrarily shifted by changing the initial value input to the arithmetic means.

[0016]

An embodiment in which the present invention is embodied in a copying machine will be described below with reference to the drawings. As shown in FIG.
A U (central processing unit) 1 has a ROM (read only memory) 2 storing a program and the like for controlling the operation of the entire apparatus, and an RA for temporarily storing various information.
M (random access memory) 3 is connected. The reading unit 4 reads an image on a document set on a reading surface (not shown) of the apparatus. The page memory 5 temporarily stores image data for one page of the document read by the reading unit 4. The recording unit 6 prints on recording paper based on the image data of one page of the document transferred line by line from the page memory 5. The thinning clock generation circuit 7 thins out predetermined pixel data in the line data transferred from the page memory 5 and outputs the thinned clock signal SCLK to the recording unit 6 by outputting the thinning clock signal SCLK to the recording unit 6.

The operation unit 8 includes various operation keys such as a start key for starting a copying operation, a reduction ratio setting key 8a, and an initial value setting key 8b. A reduction ratio setting key 8a is used to input and set a reduction ratio of image data. In the present embodiment, the value of the reduction ratio is expressed as n / m, and the value of the difference (mn) between the value m of the denominator and the value n of the numerator is d. The value m of the denominator is a value representing the size of the image data before reduction, and the value n of the numerator is a value representing the size of the image data after reduction. The initial value setting key 8b is used to input and set an initial value K described later.

Once the image data for one page of the document read by the reading section 4 is once stored in the page memory 5, the CPU 1 outputs the clock signal CLK to the page memory 5 as a read signal. Then, the image data in the page memory 5 is sequentially read for each pixel, one line at a time in synchronization with the clock signal CLK, and transferred to the recording unit 6. At the same time, the CPU 1 outputs the clock signal CLK to the thinning clock generation circuit 7. Then, the thinning clock generation circuit 7 generates pulses of the clock signal CLK at predetermined intervals based on the value n / m and the initial value K of the reduction ratio input and set by the reduction ratio setting key 8a and the initial value setting key 8b. A thinned clock signal SCLK is created by thinning out the clock signal SCLK.
Is output to the recording unit 6 as a write signal. as a result,
Of the image data transferred from the page memory 5 one pixel at a time in synchronization with the clock signal CLK, pixel data corresponding to the thinned pulse of the thinned clock signal SCLK is allowed to be input to the recording unit 6. It is thinned out.

Here, the configuration of the thinned clock generation circuit 7 will be described in detail. As shown in FIG. 1, an arithmetic circuit 9 as arithmetic means has a reduction rate of n / m
Are input as d and n. That is, when the value of the reduction ratio n / m is input and set by the reduction ratio setting key 8a, C
The PU 1 outputs values d and n obtained from the set reduction ratio value n / m to the arithmetic circuit 9. Further, an initial value K input and set by the initial value setting key 8b is input to the arithmetic circuit 9 via the CPU 1. Then, every time the image data in the page memory 5 starts to be transferred to the line data recording unit 6, the arithmetic circuit 9 outputs this initial value K as the first output value OUT1. The output value OUT1 of its own is fed back to the arithmetic circuit 9, and an output signal O from a comparison circuit 10 described later is input to the arithmetic circuit 9.
UT2 is input.

When the output signal OUT2 input from the comparison circuit 10 is at L level, the arithmetic circuit 9 synchronizes the value d and the output value OUT1 with the rising edge of the clock signal CLK input from the CPU 1. And
The result of the addition is output as a new output value OUT1.
When the input output signal OUT2 is at the H level, the arithmetic circuit 9 subtracts the value n from the output value OUT1 in synchronization with the rise of the clock signal CLK, and outputs the result of the subtraction as a new output. Output as value OUT1.

The output value OUT1 from the arithmetic circuit 9 and the value n from the CPU 1 are input to the comparison circuit 10. The comparison circuit 10 outputs the output value O in synchronization with the fall of the clock signal CLK input from the CPU 1.
UT1 is compared with the value n. At this time, the comparison circuit 10
Outputs an L-level output signal OUT2 when the output value OUT1 is smaller than the value n, and outputs the output value OUT
When 1 is equal to or greater than the value n, the output signal OUT2 at H level as a subtraction command is output.

The output signal OUT2 from the comparison circuit 10 and the clock signal CLK are input to the AND circuit 11. The AND circuit 11 converts the signal which becomes H level only when the output signal OUT2 is at L level and the clock signal CLK is at H level into the thinned clock signal S.
CLK is output. In the present embodiment, the comparison circuit 10 and the AND circuit 11 constitute a thinning unit.

Next, the operation of the copying machine configured as described above will be described with reference to the time chart of FIG. Now,
If you want to reduce the image on the original and record it on paper,
First, the user operates the reduction ratio setting key 8a of the operation unit 8 to input and set the value of the reduction ratio n / m.
Is operated to input and set the initial value K. When the copying operation is started in this state, the image on the document set on the reading surface of the apparatus is read by the reading unit 4, and the read image data is stored in the page memory 5.

Here, for example, "13/16" is input and set as the reduction ratio value n / m by the reduction ratio setting key 8a, and "0" is set as the initial value K by the initial value setting key 8b.
Is set. In this case, “13” is input as the value n, “3 (= 16−13)” as the value d, and “0” as the initial value K to the arithmetic circuit 9 of the thinning clock generation circuit 7. The output value OUT1 from the circuit 9 becomes the initial value K “0”. Note that the output signal OUT2 from the comparison circuit 10 at the start of this operation is at the L level.

In this state, when the clock signal CLK from the CPU 1 is input to the arithmetic circuit 9, the arithmetic circuit 9 first outputs "0" of its own output value OUT1 in synchronization with the rise of the clock signal CLK. "3" with the value d
Are added, and “3” is output as a new output value OUT1. When "3" of the output value OUT1 is input to the comparison circuit 10, the comparison circuit 10 outputs the output value OU in synchronization with the fall of the clock signal CLK.
"3" of T1 is compared with "13" of the value n. At this time, since the output value OUT1 is smaller than the value n, the comparison circuit 1
The output signal OUT2 from 0 goes low. Therefore,
The arithmetic circuit 9 adds “3” of its own output value OUT1 and “3” of the value d in synchronization with the next rising of the clock signal CLK, and outputs “6” as a new output value OUT1. You.

As described above, the output value OU from the arithmetic circuit 9
When T1 is smaller than the value n, the output signal OUT2 from the comparison circuit 10 is held at the L level, so that the pulse of the clock signal CLK appears as it is in the thinned clock signal SCLK output from the AND circuit 11. In the arithmetic circuit 9, the output signal OU from the comparison circuit 10 is output.
While T2 is at the L level, the clock signal CLK
Is added to the output value OUT1, and the result of the addition is output as a new output value OUT1.

When the addition operation proceeds and the output value OUT1 from the arithmetic circuit 9 becomes "15", the output signal OUT2 of the comparison circuit 10 becomes H level in synchronization with the fall of the clock signal CLK. Becomes Then
In the arithmetic circuit 9, in synchronization with the next rising of the clock signal CLK, "13" of the value n is subtracted from "15" of the output value OU1, and "2" is output as a new output value OUT1. As a result, in the comparison circuit 10, the output signal OUT2 becomes L level in synchronization with the next falling of the clock signal CLK.

As described above, while the output signal OUT2 from the comparison circuit 10 is at the H level, the operation circuit 9
In, the subtraction operation is performed in synchronization with the rise of the clock signal CLK. However, since the output signal OUT2 is at the H level, the rising pulse of the clock signal CLK at the time of the subtraction does not appear in the thinned clock signal SCLK output from the AND circuit 11. That is, the thinned-out clock signal SCLK output from the AND circuit 11 is obtained by thinning out the rising pulse of the clock signal CLK at the time of the subtraction of the arithmetic circuit 9.

As described above, when the arithmetic operation by the arithmetic circuit 9 and the comparison operation by the comparison circuit 11 sequentially progress,
As shown in FIG. 3, a thinned clock signal SCLK in which three pulses indicated by a broken line among the 16 pulses of the clock signal CLK are thinned is generated. As a result, the image data for one line in the page memory 5 is sequentially transferred to the recording unit 6 by one pixel in synchronization with the clock signal CLK, and the transferred image data is synchronized with the thinned clock signal SCLK, When one pixel at a time is sequentially input to the recording unit 6, pixel data transferred in synchronization with the thinned pulse indicated by the broken line is thinned out without being allowed to be input to the recording unit 6.

That is, when one line of image data in the page memory 5 is input to the recording unit 6, three pixel data out of 16 pixel data are thinned out as uniformly as possible. Is entered. Therefore, when printing is performed on the recording paper by the recording unit 6 based on the input image data, the image on the recording paper is reduced to 13/16 in the main scanning direction as compared with the image on the document.

In the above description, only the reduction operation in the main scanning direction has been described. However, the reduction operation can be performed in the sub-scanning direction at the same reduction ratio as in the main scanning direction. In this case, the line data in the image data may be thinned out as uniformly as possible so that the reduction ratio becomes the same as that in the main scanning direction. At this time, if one line data corresponds to one pulse of the clock signal CLK, the reduction operation can be performed in the same manner as in the main scanning direction.

As described above, in this embodiment, only by inputting and setting the value of the reduction ratio n / m, the pulses of the clock signal CLK are thinned out at predetermined intervals and set based on the set value. Clock signal S corresponding to the reduced rate
CLK is created. Therefore, a thinned clock signal SCLK corresponding to an arbitrary reduction rate can be easily created. Moreover, in this case, unlike the conventional case, there is no need to provide a memory for storing the pattern data for thinning, and it is not necessary to change the circuit configuration in accordance with each of a plurality of reduction ratios. For this reason, in order to be able to cope with a large number of reduction ratios, problems such as an increase in the capacity of the memory and an increase in the complexity of the configuration do not occur, and the manufacturing cost can be reduced.

In this embodiment, by changing the initial value K input and set by the initial value setting key 8b, the pulse position to be thinned out of the clock signal CLK can be arbitrarily shifted to change the pixel data to be thinned out. . For example,
If the initial value K is set to “3”, compared to the example shown in FIG.
As a result, the pixel data to be thinned out is shifted by one. For this reason, the user can arbitrarily change and set which pixel data should be thinned out by changing the initial value K at the time of image reduction recording, and an optimal reduced image can be obtained.

The present invention is not limited to the above embodiment, but may be embodied by changing the configuration of each part as follows. (1) The present invention is embodied in a facsimile apparatus, a printer, or the like in addition to a copying machine. For example, when the present invention is embodied in a facsimile apparatus, the present invention can be applied to both cases in which read image data on a document is reduced and transmitted, or received image data is reduced and recorded on recording paper.

(2) In the above-described embodiment, image reduction is performed by using the thinned clock signal SCLK as a signal for writing image data to the recording unit 6. However, this thinned clock signal SCLK is used as the timing of image reduction processing. May be used as a timing signal for reducing the image.

(3) Using the thinned clock signal SCLK for image enlargement processing. For example, when the image data in the page memory 5 is transferred to the recording unit 6 as in the above-described embodiment, the thinned clock signal SCLK is used as a read signal for the page memory 5 and the clock signal CLK is used for the image data for the recording unit 6. , The image can be enlarged.
In this image enlargement, the thinning clock signal SCL
K may be used as a timing signal for timing image enlargement processing.

[0037]

As described in detail above, according to the first and second aspects of the present invention, it is possible to easily create a thinned-out clock signal corresponding to an arbitrary reduction ratio, and to obtain pattern data for thinning-out. It is not necessary to provide a memory for storing the information, and the excellent effect that the configuration is simple is exhibited.

According to the third aspect of the present invention, the pulse position to be thinned out can be arbitrarily shifted by changing the initial value.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment embodying the present invention.

FIG. 2 is a block circuit diagram showing a copying machine.

FIG. 3 is a time chart illustrating an operation of the thinned clock generation circuit.

FIG. 4 is a time chart for explaining a conventional technique.

[Explanation of symbols]

7: thinning clock generation circuit, 8a: reduction ratio setting key,
8b: Initial value setting key, 9: Arithmetic circuit as arithmetic means, 10: Comparison circuit forming thinning means, 11: AND circuit forming thinning means.

Claims (3)

(57) [Claims] 1. A circuit for generating a thinning clock for thinning out pixels in image data when the image data is reduced, wherein when a value of a reduction ratio is n / m, m is synchronized with a pulse of a clock signal. A calculation means for performing addition by -n and subtracting n from the addition result when the addition result is equal to or more than n, and a thinning means for thinning out a pulse of a clock signal at the time of the subtraction and outputting it as a thinning clock are provided. Thinned clock generation circuit. 2. The arithmetic means adds mn to its own output value and outputs a new output value in synchronization with a pulse of a clock signal, and the thinning means outputs an output value from the arithmetic means. When n becomes equal to or more than n, the next pulse of the clock signal is thinned out and a subtraction command is issued to the arithmetic means,
2. The thinning clock generation circuit according to claim 1, wherein the calculating means subtracts n from the output value in synchronization with a next pulse of the clock signal based on the subtraction command. 3. The thinning clock generation circuit according to claim 2, wherein said calculating means performs a calculating operation based on the input of the initial value and using the initial value as an initial output value.