JP3339397B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a hollow package.

[0002]

2. Description of the Related Art One of packages used for LSIs (large-scale integrated circuits) such as memories and microprocessors, which are known as representatives of semiconductor devices, is a hollow package made of an insulating material such as resin. It has been known.
Since this hollow package can reduce parasitic capacitance by arranging wiring such as bonding wires on a semiconductor chip or signal paths such as electrode pads in the hollow, it is particularly applied to a high frequency semiconductor device. It is effective.

FIG. 18 shows an example of this type of semiconductor device, and shows a structure disclosed in Japanese Patent Application Laid-Open No. 62-42440. The semiconductor device described in the publication is a lead frame 5 in which an IC chip 51 is die-bonded.
A primary sealing resin sheet 53 having a hollow shape is welded to the front and back surfaces of the second sealing resin sheet 53, and the primary sealing resin sheet 53 is molded with a secondary sealing resin 54. The thin metal wires 55 bonded between the electrode pads of the IC chip 51 and the lead portions of the lead frame 52 are arranged in the hollow of the primary sealing resin sheet 53.

However, the semiconductor device described in Japanese Patent Application Laid-Open No. Sho 62-42440 has a complicated structure because the package has a double structure of the primary sealing resin sheet 53 and the secondary sealing resin 54. Therefore, there is a disadvantage that the manufacturing cost increases.

[0005] Therefore, as a means for solving this drawback,
A semiconductor device described in JP-A-5-291322 is provided. The semiconductor device described in this publication is shown in FIG.
As shown in FIG. 7, a semiconductor chip 62 is face down bonded on a film carrier 61 composed of a lead pattern 61d attached to an insulating film 61s, and a concave portion 63 is formed on the surface (active surface) side of the semiconductor chip 62 for sealing. The resin sheet 63a is adhered, and another sealing resin sheet 63b is adhered to the back surface side. The electrode pad 62a of the semiconductor chip 62 is arranged in the hollow formed by the concave portion 63 of the sealing resin sheet 63a.

In order to manufacture the semiconductor device described in Japanese Patent Application Laid-Open No. 5-291322, first, as shown in FIG.
On the surface side of the semiconductor chip 62 which is face-down bonded onto the film carrier 61, the main surface facing the semiconductor chip 62 of the uncured resin is selectively irradiated with light in advance, and only a part of the resin is cured to form the concave portion 63. Is formed, and the sealing resin sheet 63b is arranged on the back side of the semiconductor chip. Next, after the sealing resin sheets 63a and 63b are respectively attached to the front side and the back side of the semiconductor chip 62, a compression molding process is performed to manufacture the above semiconductor device.

Here, in order to partially form the concave portion 63 in the sealing resin sheet 63a, in addition to the above-described light irradiation,
Partial cross-linking means such as ultraviolet irradiation, infrared irradiation, and hot air blowing are used.

[0008]

However, in the prior art described in Japanese Patent Application Laid-Open No. 5-291322, a semiconductor chip is face-down bonded to a lead pattern having poor mechanical strength, and an external force is easily applied to the semiconductor chip. Due to the structure, there is a problem that connection reliability is low. That is, as is clear from FIGS. 19 and 20, the lead pattern 61d to which the semiconductor chip 63 is bonded is only supported by the insulating film 61s, so that a decrease in mechanical strength is inevitable. In the bonding portion, a sealing resin sheet 63 is provided.
Since a is in contact, an external force due to this is easily applied to the bonding portion, so that the connection strength is affected. In the worst case, there is a possibility that the bonding portion is peeled off due to these factors.

There is another problem that it is difficult to apply to a semiconductor device using a semiconductor chip of a minute size. That is, in the prior art described in JP-A-5-291322, as a method of forming the concave portion 63 in the sealing resin sheet 63a, a partial cross-linking means such as light irradiation is used.
Such a method has no problem when applied to a semiconductor chip having a relatively large size of about 10.times.10 mm as described in the above publication. However, when it is intended to apply to a semiconductor chip of a small size of about several mm, for example, about 1 × 1 mm or less, since the formation of the concave portion corresponding to the semiconductor chip becomes strict with the above means, It becomes difficult to apply.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device which can improve connection reliability and can be applied to a small-sized semiconductor chip. And

[0011]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a plurality of hollow portions in a sheet-shaped insulating substrate; An insulating substrate forming step of forming a wiring pattern corresponding to an electrode pad of a semiconductor chip on one principal surface; and a position where the package substrate is thermocompression-bonded in a state where a region including the wiring pattern of the insulating substrate is masked. Forming a rough surface portion, and connecting the semiconductor chip on the one main surface of the insulating substrate, and then sealing the corresponding semiconductor chip with the hollow portion. A package substrate thermocompression bonding step of thermocompression bonding the package substrate to a rough surface portion on one main surface; and a substrate separation step of separating the package substrate and the insulation substrate into individual semiconductor chips. It is characterized in that it comprises and.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein one of the main surfaces is formed in an uneven shape, and a wiring pattern corresponding to an electrode pad of a semiconductor chip is formed on the concave portion. Forming a rough surface portion at a position where the package substrate is thermocompression-bonded while masking a region including the wiring pattern of the insulating substrate; and forming a rough surface portion on a concave portion of one main surface of the insulating substrate. After connecting the semiconductor chip, to seal the semiconductor chip,
A package substrate thermocompression bonding step of thermocompression bonding a package substrate made of a resinous sheet to a rough surface on a convex portion of one main surface of the insulating substrate; and separating the package substrate and the insulating substrate into individual semiconductor chips. And a substrate separating step.

[0013]

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. First Embodiment FIG. 1 is a diagram showing a configuration of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device. FIG. 2B is a cross-sectional view taken along line AA of FIG. 2A, FIG. 2 is a process diagram showing a method of manufacturing the semiconductor device in the order of processes, and FIGS.
FIG. 3 is a process chart showing replacement of some steps of the method for manufacturing the semiconductor device of FIG. 2. In the semiconductor device manufactured by the method for manufacturing a semiconductor device of this example, as shown in the figure, a wiring pattern 2 is formed on one main surface of an insulating substrate 1 such as a plastic substrate or a ceramic substrate. A semiconductor chip 3 is formed by face-down bonding on the top. As an example, the semiconductor chip 3 is approximately 1 × 1 mm
Has a very small size. Specifically, the semiconductor chip 3 has its electrode pad 4 connected to the wiring pattern 2 through a ball-shaped conductor 5 such as solder or gold.

On one main surface of the insulating substrate 1, a hollow package 6 made of a thermosetting resin such as a polyimide resin or an epoxy resin, for example, having a square planar shape is provided so as to seal the semiconductor chip 3. Is fixed at a position approximately 50 μm away from the connection position of the semiconductor chip 3. Package 6
The thermocompression bonding method can be used as a means for fixing the adhesive.

The package 6 on one main surface of the insulating substrate 1
Is formed at a position where the package 6 is adhered with good adhesion. As a means for forming the rough surface portion 7, a surface processing method using an abrasive can be mentioned. The wiring pattern 2 on one main surface of the insulating substrate 1 is formed so as to extend to the outside of the package 6, and is used as an external terminal.

Next, a method of manufacturing the semiconductor device of this embodiment will be described in the order of steps with reference to FIG. First, as shown in FIG. 1A, for example, a cresol novolak type thermosetting resin, which is a type of epoxy resin, is used.
It is set between the upper mold 8 and the lower mold 9 using a resin sheet having a thickness of about 0.5 mm. Next, while heating to approximately 175 ° C., vacuum suction is performed in the direction of the arrow to form a plurality of hollow portions 6 a having a square planar shape, thereby forming the package substrate 6 b. According to such a vacuum suction molding method, it is easy to form the hollow portion 6a with high precision, so that it is possible to form a hollow package applicable to a small-sized semiconductor chip.

Alternatively, instead of the vacuum suction molding method, FIG.
The package substrate 6b can be formed by a press molding method as shown in FIG. In the figure, the resin sheet is pressed by an upper mold 8a in a state where it is set on a lower mold 9a in advance, so that a plurality of hollow portions 6 are formed.
The package substrate 6b having a is formed. The hollow portion 6a can be formed with high precision also by this press molding method.

Next, as shown in FIG. 2B, approximately 0.1 to 0.2 made of a plastic substrate, a ceramic substrate or the like.
A wiring pattern 2 is formed on one main surface of the insulating substrate 1 having a thickness of mm by a screen printing method or the like. Next, the insulating substrate 1
In a state where the region including the wiring pattern 2 on one main surface is covered with a mask 10 such as a resin, a rough surface portion 7 for fixing the package substrate 6b with good adhesion is provided at a position where the package substrate 6b is fixed. To form The rough surface portion 7 is formed by performing a special processing, and for example, an alumina (♯)
320, a polishing agent 12 composed of a mixture of water (volume concentration: 17 ± 1%) with water (maximum particle size: 98 μm, average particle size: 40 μm, minimum particle size: 27 μm). It is formed by spraying on the main surface. Thus, a rough surface portion 7 having a surface roughness Rmax of 3 to 4 μm is formed.

Alternatively, in order to fix the package substrate 6b with good adhesion, an adhesive can be used instead of the rough surface portion 7. In this case, as one method, FIG.
As shown in (1), an adhesive 14 is partially applied from the needle 13 to the fixing position of one main surface of the insulating substrate 1.
As another method, first, as shown in FIG.
As shown in (b), after covering a portion other than the fixing position of one main surface of the insulating substrate 1 with a mask 10a of resin or the like, an adhesive 14a is applied to the fixing position by a screen printing method or the like as shown in FIG. To do it. Adhesive 14, 1 by any method
4a can also play the same role as the above-mentioned rough surface portion 7.

Next, as shown in FIG. 1C, a minute semiconductor chip 3 of approximately 0.35 × 0.35 × 0.16 mm is face-down bonded on one main surface of the insulating substrate 1. . In this face-down bonding, the electrode pads 4 of the semiconductor chip 3 are connected to the wiring patterns 2 through ball-shaped conductors 5 such as solder and gold.

Next, as shown in FIG. 2D, the base 6e of the package substrate 6b is bonded to the rough surface 7 of the insulating substrate 1 by a thermocompression bonding method so that the hollow portion 6a seals the semiconductor chip 3. Stick. This thermocompression bonding method is performed at a temperature of about 175 ° C., a pressure of 70 to 120 g / cm ² , and a curing time of 15 to 25 seconds. The package substrate 6b is fixed at a position approximately 50 μm away from the connection position of the semiconductor chip 3.

Next, as shown in FIG. 1E, the package substrate 6b and the insulating substrate 1 are cut and separated into individual semiconductor chips 3 using a dicing blade, thereby obtaining the structure shown in FIG. A semiconductor device is manufactured.

As described above, according to the configuration of this embodiment,
The semiconductor chip 3 is connected to one main surface of the insulating substrate 1 having excellent mechanical strength, and a position away from the connection position of the semiconductor chip 3 so that the hollow package 6 seals the semiconductor chip 3. Is fixed on one main surface of the insulating substrate 1, no external force from the package 6 is applied to the semiconductor chip 3, so that the connection reliability of the semiconductor device can be improved. In addition, since the hollow portion 6a of the package 6 can be formed with high precision, it can be applied to the semiconductor chip 3 having a very small size. Furthermore, since the rough surface portion 7 is formed at a position on one main surface of the insulating substrate 1 where the hollow package 6 is fixed, the package 6 can be fixed with good adhesion. In addition, the hollow package 6
Is provided only on one main surface of the insulating substrate 1,
Since the material cost of the package 6 is reduced, productivity can be improved.

FIG. 6 is a sectional view schematically showing the structure of a semiconductor device according to a first embodiment of the present invention. The configuration of the semiconductor device of the first reference example is greatly different from that of the first embodiment in that the semiconductor chip 3 is face-up bonded on one main surface of the insulating substrate 1. That is,
The semiconductor chip 3 is connected to one main surface of the insulating substrate 1 by an adhesive, and the electrode pads 4 are connected to the wiring pattern 2 of the insulating substrate 1 through bonding wires 15 such as gold wires and aluminum wires. Except for the points described above, the configuration is substantially the same as that of the first embodiment described above. Therefore, in FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

As described above, according to the structure of this embodiment, substantially the same effects as described in the first embodiment can be obtained. In addition, since the bonding wire 15 is arranged around the semiconductor chip 3 as compared with the case of the above-described first embodiment, the possibility that the bonding wire 15 touches the package 6 and receives an external force is increased. Since the hollow portion 6a of the package 6 can be formed with high precision, such a possibility can be eliminated.

Second Embodiment FIG. 7 is a sectional view schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention. The configuration of the semiconductor device of the second reference example is significantly different from that of the above-described first embodiment in that the wiring pattern 2 on one main surface of the insulating substrate 1 is not extended outside the package 4. The point is that it is connected to the wiring pattern 2a formed on the other main surface of the insulating substrate 1. That is, the wiring pattern 2 on one main surface of the insulating substrate 1 is formed by the through-hole wiring 16 formed on the insulating substrate 1.
Through the wiring pattern 2a on the other main surface. The wiring pattern 2a is connected to a ball-shaped external terminal 17 made of solder, gold, or the like, serving as an external terminal. It has a so-called BGA (Ball Grid Array) terminal structure.

As described above, according to the structure of this embodiment, substantially the same effects as described in the first embodiment can be obtained. In addition, a ball-shaped external terminal 17 acting as an external terminal is provided in
Since it is arranged not on the outside but on the other main surface of the insulating substrate 1, when it is mounted on a printed circuit board as a component, the mounting area can be saved.

Third Embodiment FIG. 8 is a sectional view schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention. The configuration of the third embodiment is greatly different from that of the second embodiment in that a pin-shaped external terminal 18 is connected to the wiring pattern 2a on the other main surface of the insulating substrate 1. is there. So-called PG
A (Pinl Grid Array) terminal structure. As described above, even with the configuration of this example, substantially the same effects as those described in the second reference example can be obtained.

Fourth Embodiment FIG. 9 is a sectional view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention. The configuration of the fourth embodiment is largely different from that of the second embodiment in that the semiconductor chip 3 is face-up bonded on one main surface of the insulating substrate 1.

As described above, according to the structure of this embodiment, substantially the same effects as described in the second embodiment can be obtained. In addition, since the bonding wire 15 is arranged around the semiconductor chip 3 as compared with the case of the above-described second reference example, the possibility that the bonding wire 15 touches the package 6 and receives an external force is increased. Since the hollow portion 6a of the package 6 can be formed with high precision, such a possibility can be eliminated.

FIG. 10 is a sectional view schematically showing the structure of a semiconductor device according to a fifth embodiment of the present invention. The configuration of the fifth reference example is
A major difference from the third embodiment is that the semiconductor chip 3 is face-up bonded on one main surface of the insulating substrate 1.

As described above, according to the structure of this embodiment, substantially the same effects as described in the third embodiment can be obtained. In addition, since the bonding wire 15 is arranged around the semiconductor chip 3 as compared with the case of the above-described third reference example, the possibility that the bonding wire 15 touches the package 6 and receives an external force increases. Since the hollow portion 6a of the package 6 can be formed with high precision, such a possibility can be eliminated.

Second Embodiment FIG. 11 is a view showing a configuration of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
14A is a plan view of the semiconductor device, FIG. 14B is a cross-sectional view taken along the line AA of FIG. 14A, and FIG. FIG. A semiconductor device manufactured by the method for manufacturing a semiconductor device of this example includes:
As shown in the figure, one main surface of an insulating substrate 21 such as a plastic substrate or a ceramic substrate
It is formed in an uneven shape having b. The wiring pattern 22 is formed on the concave portion 21a on one main surface of the insulating substrate 21, and the semiconductor chip 23 is face-down bonded on the concave portion 21a. As an example, the semiconductor chip 23 has a very small size of approximately 1 × 1 mm. Specifically, the semiconductor chip 23 has its electrode pads 2
4 is connected to the wiring pattern 22 through a ball-shaped conductor 25 such as solder or gold.

A rough surface portion (not shown) corresponding to the rough surface portion 7 in the first embodiment is formed on the convex portion 21b on one main surface of the insulating substrate 21, and the semiconductor chip 23 is formed on the rough surface portion. A resin sheet 26 made of a thermosetting resin such as a polyimide resin or an epoxy resin and having a square planar shape is fixed by thermocompression bonding or the like so as to be sealed. And
A hollow package 27 is configured by the convex portion 21b of the insulating substrate 21 and the sheet 26. Insulating substrate 21
The wiring pattern 22 on the concave portion 21a on one main surface is formed so as to extend to the outside of the package 27, and is used as an external terminal.

Next, a method of manufacturing the semiconductor device of this example will be described in the order of steps with reference to FIG. First, as shown in FIG. 1A, a main surface is formed in a concave and convex shape having a concave portion 21a and a convex portion 21b, and a wiring pattern 22 is formed on the concave portion 21a. The prepared insulating substrate 21 is prepared. In this case, similarly to the first embodiment, the convex portion which is a position where the resin sheet 26 is fixed in a state where the region including the wiring pattern 22 on one main surface of the insulating substrate 21 is covered with a mask such as resin. 2
A rough surface portion (not shown) is formed on the surface of 1b. Recess 21a
Has a thickness of about 0.1 to 0.2 mm, and the projection 21b has a thickness of about 0.2 mm.
It is formed to a thickness of 0.3 mm. Such an insulating substrate 2
1 can be easily formed by using a well-known ceramic substrate forming technique, and thus a detailed description thereof will be omitted. Also, the recess 2 is formed by the ceramic substrate forming technique.
1a can be formed with high precision.

Next, as shown in FIG. 3B, approximately 0.35 × 0.35
A semiconductor chip 23 of a minute size of 0.16 mm is face-down bonded. In this face-down bonding, an electrode pad 24 of a semiconductor chip 23 is connected to a wiring pattern 22 through a ball-shaped conductor 25 such as solder or gold.
Connect to

Next, as shown in FIG. 3C, a semiconductor sheet 26 having a thickness of about 0.5 mm and made of, for example, a cresol novolac type thermosetting resin, which is a kind of epoxy resin, is used. The chip 23 is fixed on the convex portion 21b on one main surface of the insulating substrate 21 by a thermocompression bonding method or the like so as to seal the chip 23. Thus, the hollow package 27 is configured by the concave portion 21a of the insulating substrate 21 and the resin sheet 26. Next, as shown in FIG. 4D, the insulating substrate 21 and the resin sheet 26 are separated into individual semiconductor chips 23 using a dicing blade, whereby
The semiconductor device as shown in FIG. 11 is manufactured.

As described above, according to the structure of the second embodiment, the semiconductor chip 24 is made of the insulating substrate 2 having excellent mechanical strength.
1 is connected to the concave portion 21a on one principal surface, and the resin sheet 26 has its convex portion 2 so as to seal the semiconductor chip 23.
1b, the hollow package 27 is constituted by the projection 21b and the resin sheet 26. Therefore, the hollow package 27 is separated from the connection position of the semiconductor chip 23 by the insulating substrate. Since it is formed on one main surface of the semiconductor chip 21, the external force of the package 27 is not applied to the semiconductor chip 23, so that the connection reliability of the semiconductor device can be improved.

Further, since the concave portion 21a serving as the hollow portion of the package 27 can be formed with high precision, it can be applied to the semiconductor chip 23 of a minute size. Further, since the hollow package 27 is provided only on one main surface of the insulating substrate 21, the material cost of the package 27 is reduced, so that productivity can be improved.

Sixth Embodiment FIG. 13 is a sectional view schematically showing a configuration of a semiconductor device according to a sixth embodiment of the present invention. The configuration of the semiconductor device of the sixth reference example is greatly different from that of the above-described second embodiment in that the semiconductor chip 23 is face-up bonded on the recess 21a on one main surface of the insulating substrate 21. . That is, the semiconductor chip 23 is connected to the concave portion 21a on one main surface of the insulating substrate 21 by an adhesive, and its electrode pad 24 is connected to the wiring pattern 2
2 are connected.

As described above, according to the structure of this embodiment, substantially the same effects as described in the second embodiment can be obtained. In addition, compared to the case of the above-described second embodiment, since the bonding wires 28 are arranged around the semiconductor chip 23, the bonding wires 28
Although the possibility of receiving an external force by touching the touch panel 7 becomes larger, such a possibility can be eliminated because the concave portion 21a serving as the hollow portion of the package 27 can be formed with high precision.

Seventh Embodiment FIG. 14 is a sectional view schematically showing a configuration of a semiconductor device according to a seventh embodiment of the present invention. The configuration of the semiconductor device of the seventh reference example is significantly different from that of the above-described second embodiment in that the wiring pattern 22 on the recess 21 a on one main surface of the insulating substrate 21 is extended outside the package 27. Instead, it is connected to the wiring pattern 22a formed on the other main surface of the insulating substrate 21. That is, the wiring pattern 22 on the concave portion 21a on one main surface of the insulating substrate 21 is connected to the wiring pattern 22a on the other main surface through the through-hole wiring 29 formed in the concave portion 21a of the insulating substrate 21. The wiring pattern 22a has a ball-shaped external terminal 30 made of solder, gold, or the like, serving as an external terminal.
It is connected to the. It has a so-called BGA terminal structure.

As described above, according to the structure of this embodiment, substantially the same effects as described in the second embodiment can be obtained. In addition, as compared with the case of the above-described second embodiment, a ball-shaped external terminal 30 serving as an external terminal is provided in the package 2.
7 is arranged on the other main surface of the insulating substrate 21 and not on the outside of the insulating substrate 21.
The mounting area can be saved.

Eighth Embodiment FIG. 15 is a sectional view schematically showing a configuration of a semiconductor device according to an eighth embodiment of the present invention. The configuration of the semiconductor device according to the eighth embodiment is significantly different from that of the seventh embodiment in that the wiring pattern 22a on the other main surface of the insulating substrate 21 is provided.
In addition, a pin-shaped external terminal 31 is connected. It has a so-called PGA terminal structure. As described above, according to the configuration of this example, substantially the same effects as described in the seventh reference example can be obtained.

Ninth Embodiment FIG. 16 is a sectional view schematically showing a configuration of a semiconductor device according to a ninth embodiment of the present invention. The configuration of the semiconductor device according to the ninth embodiment is largely different from that of the above-described seventh embodiment in that the semiconductor chip 23 is face-up bonded onto the concave portion 21a on one main surface of the insulating substrate 21. . As described above, according to the configuration of this example, substantially the same effects as described in the seventh reference example can be obtained.

FIG. 17 is a sectional view schematically showing a configuration of a semiconductor device according to a tenth embodiment of the present invention. The configuration of the semiconductor device according to the tenth embodiment is largely different from that of the ninth embodiment in that the wiring pattern 2 on the other main surface of the insulating substrate 21 is different.
The point is that a pin-shaped external terminal 32 is connected to 2a. It has a so-called PGA terminal structure. As described above, even with the configuration of this example, substantially the same effects as described in the ninth reference example can be obtained.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are changes in the design without departing from the gist of the present invention. Is also included in the present invention. For example, wiring patterns 2, 2a, 22, 2 formed on the wiring substrates 1, 21
The number of 2a, the number of ball-shaped external terminals, the number of pin-shaped external terminals, and the like can be arbitrarily increased or decreased. Further, the planar shape of the hollow packages 6 and 27 is not limited to a square, but can be changed to a circle, a polygon, or the like.

The means for fixing the package substrates 6b and 6d, the resin sheet 26, and the like on one main surface of the insulating substrates 1 and 21 is not limited to the thermocompression bonding method, but also uses an ultrasonic combined thermocompression bonding method. be able to. When the adhesives 14 and 14a are applied to the position where the package 6 is fixed on the insulating substrate 1, the package 6 can be fixed by curing the adhesives 14 and 14a using light irradiation.

The size of the semiconductor chips 3 and 23, the thickness of the insulating substrates 1 and 21, the thickness of the package substrates 6b and 6d, the thickness of the resin sheet 26, etc., the conditions of special processing, the conditions of the thermocompression bonding method, etc. Can be changed as needed.

[0060]

As described above, according to the structure of the present invention, a semiconductor chip is connected to one main surface of an insulating substrate having excellent mechanical strength, and a hollow package seals the semiconductor chip. The semiconductor chip is fixed to one main surface of the insulating substrate at a position away from the connection position of the semiconductor chip so that external force due to the package is not applied to the semiconductor chip, thereby improving the connection reliability of the semiconductor device. Can be. Further, since the hollow portion of the package can be formed with high precision, it can be applied to a semiconductor chip having a very small size. In addition, since a special treatment is applied to a position on one main surface of the insulating substrate where the hollow package is fixed, the package can be fixed with good adhesion. Further, since the hollow package is provided only on one main surface of the insulating substrate, the material cost of the package does not increase, and therefore, the productivity can be improved.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a configuration of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of the semiconductor device, and FIG. FIG. 2 is a sectional view taken along the line AA in FIG.

FIG. 2 is a process chart showing a method for manufacturing the semiconductor device in the order of steps.

FIG. 3 is a process chart showing replacement of some steps of the method for manufacturing the semiconductor device.

FIG. 4 is a process chart showing replacement of some steps of the method for manufacturing the semiconductor device.

FIG. 5 is a process chart showing replacement of some steps of the method for manufacturing the semiconductor device.

FIG. 6 is a sectional view showing a configuration of a semiconductor device according to a first reference example of the present invention;

FIG. 7 is a sectional view showing a configuration of a semiconductor device according to a second reference example of the present invention;

FIG. 8 is a sectional view showing a configuration of a semiconductor device according to a third reference example of the present invention;

FIG. 9 is a sectional view showing a configuration of a semiconductor device according to a fourth reference example of the present invention;

FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a fifth reference example of the present invention;

FIG. 11 is a diagram showing a configuration of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a second embodiment of the present invention;
2A is a plan view of the semiconductor device, and FIG. 2B is a cross-sectional view taken along the line AA in FIG.

FIG. 12 is a process chart showing a method of manufacturing the same semiconductor device in the order of steps.

FIG. 13 is a sectional view showing a configuration of a semiconductor device according to a sixth reference example of the present invention;

FIG. 14 is a sectional view showing a configuration of a semiconductor device according to a seventh reference example of the present invention;

FIG. 15 is a sectional view showing a configuration of a semiconductor device according to an eighth embodiment of the present invention;

FIG. 16 is a sectional view showing a configuration of a semiconductor device according to a ninth embodiment of the present invention;

FIG. 17 is a sectional view showing a configuration of a semiconductor device according to a tenth embodiment of the present invention;

FIG. 18 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

FIG. 19 is a cross-sectional view showing a configuration of another conventional semiconductor device.

FIG. 20 is a cross-sectional view showing the method for manufacturing the same semiconductor device.

[Explanation of symbols]

 7 Rough surface

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-153059 (JP, A) JP-A-1-134956 (JP, A) JP-A-62-242440 (JP, A) JP-A-57-1979 128948 (JP, A) JP-A-3-224251 (JP, A) JP-A-4-116852 (JP, A) JP-A-3-101538 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 23/02-23/10 H01L 23/28

Claims (2)

(57) [Claims] A package substrate forming step of forming a plurality of hollow portions in a sheet-shaped insulating substrate; an insulating substrate forming step of forming a wiring pattern corresponding to an electrode pad of a semiconductor chip on one main surface; A rough surface portion forming step of forming a rough surface portion at a position where the package substrate is thermocompression-bonded while masking a region including a wiring pattern of the substrate; and connecting the semiconductor chip to the one main surface of the insulating substrate. A package substrate thermocompression bonding step of thermocompression bonding the package substrate to a rough surface portion on the one main surface of the insulating substrate so that the hollow portion seals a corresponding semiconductor chip; A substrate separating step of separating a substrate into individual semiconductor chips. An insulating substrate forming step of forming a wiring pattern corresponding to an electrode pad of a semiconductor chip on the concave portion, and masking a region including the wiring pattern of the insulating substrate. In the state, a rough surface portion forming step of forming a rough surface portion at a position where the package substrate is thermocompression-bonded, and after connecting the semiconductor chip to a concave portion on one main surface of the insulating substrate, sealing the semiconductor chip A package substrate thermocompression bonding step of thermocompression bonding a package substrate made of a resin sheet to a rough surface portion on a convex portion of one main surface of the insulating substrate; and bonding the package substrate and the insulating substrate together with each individual semiconductor chip. A method of manufacturing a semiconductor device, the method comprising: