JP3341464B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to time-series data such as video data and audio data, for example, IEEE-
P1394-compliant serial bus (hereinafter referred to as “P1394
A data transfer device suitable for transmission using a communication control bus such as a serial bus.

[0002]

2. Description of the Related Art A system is considered in which a plurality of devices are connected by a communication control bus such as a P1394 serial bus which can mix control signals and information signals, and the information signals and control signals are communicated between these devices. Have been.

FIG. 24 shows an example of such a system.
This system includes devices A, B, C, D, and E.
Then, between devices A and B, between A and C, between C and D, and between C and D
E is connected by a twisted pair cable of a P1394 serial bus. These devices are, for example, digital VTRs, tuners, monitors, and the like. Since each device has a function of relaying information signals and control signals input from a twisted pair cable, this system is equivalent to a system in which each device is connected to a common communication control bus as shown in FIG. .

Data transmission between the devices A to E sharing the communication control bus is performed by time division multiplexing every predetermined communication cycle (for example, 125 μsec) as shown in FIG. The management of the communication cycle on the communication control bus is performed by a predetermined device that manages the communication system, for example, device A.
Is transmitted to another device connected to the communication control bus by transmitting a synchronization packet (cycle start packet: hereinafter referred to as "CSP") indicating that the communication is synchronized, that is, at the start of the communication cycle. Data transmission is started.

[0005] The data format transmitted in one communication cycle includes synchronous data such as video data and audio data (hereinafter referred to as "Iso data") and asynchronous data such as connection control commands (hereinafter referred to as "Async data"). ). Then, the Iso data packet is transmitted before the Async data packet. By assigning channel numbers 1, 2, 3,... N to each of the Iso data packets,
o Data can be distinguished. After the transmission of the Iso data packet of all channels is completed, the next CS
The period up to P is used for transmitting Async data.

[0006]

In the communication system described above, video data and audio data (hereinafter "A") output from a digital VTR are used as Iso data.
V data) to another digital VTR.

When transmitting Iso data such as AV data through a transmission line having a speed different from the speed of the data, the transmitting side adjusts the AV data generated by the digital VTR to the transmission speed of the transmission line. Further, on the receiving side, in order to return the received AV data to the data speed of the digital VTR, a FIFO for temporarily holding the data is required.

According to the present invention, when writing / reading data to / from the FIFO at different speeds, the transmission / reception-side equipment and the transmission speed of the transmission path are matched, the data writing / reading is performed. It is an object of the present invention to provide a data transfer device in which data does not overflow from the FIFO or data in the FIFO does not become empty.

[0009]

In order to solve the above-mentioned problems, a data transfer apparatus according to the present invention, on the transmitting side, writes periodically generated data packets at a first rate to a temporary storage means. At least after a first predetermined time, the data packet is read at a second speed different from the first speed, and a first time obtained by adding the first predetermined time to the absolute time at which the data packet was generated is added to the data packet. The data packet written to the temporary storage means at the second speed is transmitted to the receiving side by a second time obtained by adding a second predetermined time to the first time.
At the first speed from the time.

It is preferable that the first time added to the received data packet is read before the received data packet is written to the temporary storage means. When the data packet generated on the transmitting side is a header packet and a plurality of types of packets having different lengths such as a video data packet and an AV data packet following the header packet, these packets are fixed-length by the temporary storage means. Convert to packets and transmit.

In this case, on the transmitting side, every time a data packet of a fixed length is written to the temporary storage means, a write confirmation signal is input to the temporary storage means, and the write confirmation signal is input. The data packet is read from the temporary storage unit after the writing is performed, and the first predetermined time is determined so that the timing of reading the data packet does not come before the timing of inputting the write confirmation signal.

In this case, on the receiving side, every time a fixed-length data packet is written to the temporary storage means, a write confirmation signal is input to the temporary storage means, and after the write confirmation signal is input, the reception side temporarily stores the write confirmation signal. A plurality of types of data packets having different lengths are read from the storage means, and the second predetermined time is determined so that the timing for reading the data packets does not come before the timing for inputting the write confirmation signal. .

[0013] When the video data packet or the AV data packet is read from the temporary storage means on the receiving side, the timing of the second time is set by the phase locked loop used for generating the frame synchronization pulse in the receiving side AV equipment. Preferably, it is generated.

[0014]

According to the present invention, on the transmitting side, the generated data is stored in the temporary storage means at the first speed, and is read out at the second speed at least after a first predetermined time, and the absolute data generated at the second speed is generated. A time obtained by adding a first predetermined time to the time, that is, a time when data is read out earliest is added and transmitted. Then, on the receiving side, the data is stored in the temporary storage means at the second speed, and is read out at the first speed from a second time obtained by adding a second predetermined time from the first time.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. [1] Overall Configuration and Operation of Data Transfer Device [2] Operation on Transmission Side [2]-(1) Packet Format and Transmission Timing [ 2]-(2) Operation of the transmitting circuit [3] Operation of the receiving side [3]-(1) Packet format and transmission timing [3]-(2) Operation of the receiving circuit will be described in detail.

[1] Overall Configuration and Operation of Data Transfer Apparatus FIG. 1 shows AV data between two digital VTRs (hereinafter, "digital VTR" is simply referred to as "VTR") connected via a P1394 serial bus. 1 is an embodiment of a data transfer device when transmitting data.

The VTR 1 outputs a write signal (write enable) a to the FIFO 2 and outputs the AV data b to the F
When writing to the FIFO2 is started and when the AV data for one transmission packet is written, the confirm signal c is sent to the FIFO2.
Output to 2. Further, a track pulse d, which is a signal indicating the timing at which the writing of the AV data b into the FIFO 2 is started, is output to the transmission circuit 3. Upon receiving the confirm signal c, the FIFO 2 changes the signal e indicating the state of the FIFO 2 from “empty” to “full”. Upon receiving the track pulse d, the transmission circuit 3 waits for a certain time, outputs a read signal f to the FIFO 2, and reads data g. This waiting time is referred to as ITF (Initial Tran
(smit FIFO) delay.

A header is added to the read data g in the transmission circuit 3, and the data g is transmitted in accordance with a read request h from a transmission line interface (hereinafter, “interface” is referred to as “I / F”) 4. Sent to here,
In the header, a time obtained by adding an ITF delay to the time at which the transmission circuit 3 receives the track pulse d output from the VTR 1 (hereinafter referred to as “sync time”) is written. In the transmission path I / F4, the data i has a C for detecting a packet error.
RC is added, converted to a state where it can be transmitted on the P1394 serial bus 5, and output.

On the receiving side, the transmission path I / F 6 converts the signal received via the P1394 serial bus 5 into a packet state, and outputs data k to the receiving circuit 7 together with the write signal j. The receiving circuit 7 removes the header from the received packet, and stores the data m together with the write request 1 in the FIFO 8
Output to Then, when one packet of data has been written, a confirm signal n is output to the FIFO 8.
At the same time, the reception circuit 7 reads out the sync time written at the time of transmission from the header, and outputs a track pulse r to the VTR 9 when a certain time is added to the sync time. When the FIFO 8 receives the confirm signal n,
The signal o indicating the state of the FIFO 8 is changed from “empty” to “full”.

The track pulse r is output from the PLL 1 in the VTR 9.
0, and the output of the PLL 10 is locked to the track pulse r. Then, the output of the PLL 10 is used as a read signal
Output to O8 and read data q. Since the output of the PLL 10 is used for generating the frame synchronization signal of the VTR 9, the reading of data from the FIFO 8 is synchronized with the reproduced image.

[2] Operation on Transmission Side [2]-(1) Packet Format and Transmission Timing FIG. 2 shows the format of data b output from the VTR 1 in FIG. 1 and data g output from the FIFO 2. Here, the left side is data b, and the right side is data g.

The data b constitutes one packet in a state of either 120 quadlets (= 6 sync blocks) or 100 quadlets (= 5 sync blocks). One quadlet is 4 bytes. Data b includes a header and a buffering unit (hereinafter "BU").
And audio data).

The header includes control information on the entire AV data, and a segment header is provided with one quadlet. The segment header is special data indicating the beginning of a segment. The BU contains video data of 5 sync blocks, and BU0 to B
There are 27 to U26. Audio data from A0 to A8, with one sync block for every three packets,
There are nine in all. 28 packets are collected and 1
It is a unit called a segment.

The above described AV data b is written into the FIFO 2 at the timing inside the VTR 1. This is P1
It has nothing to do with the communication timing on the 394 serial bus 5.

The data b written in the FIFO 2 has been described above. Next, the data f read from the FIFO 2 will be described. The data f read from the FIFO2 is a packet composed of all 120 quadlets, and there are 25 packets DP0 to DP24. These packets are read from the FIFO 2 at the timing of the communication cycle of the P1394 serial bus 5. The read speed and VTR1 are equal to FIFO2.
Therefore, the speed conversion is performed by the FIFO2.

Further, the data must be transmitted on the P1394 serial bus 5 in packet units. Therefore, when the transmission circuit 3 reads a packet from the FIFO 2, at least one packet (= 120 quadlets) must be written in the FIFO 2. VTR1 is 1
In order to prevent the transmission circuit 3 from reading data when writing a packet in the middle of the FIFO 2, the VTR
1 outputs a confirm signal c to the FIFO 2 when one packet is written. The FIFO 2 receives the confirm c, and the transmitting circuit 3 changes the state of the FIFO 2 to “full”.
1 ”until the transmission circuit 3 notifies the data g
Cannot be read.

FIG. 3 shows the above operation on the time axis.
And FIG. In FIG. 3, (a), (b),
(C) is a packet that the VTR 1 writes to the FIFO 2, a confirm signal, and a packet that the transmission circuit 3 reads from the FIFO 2. (D), (e),
(F),... (J), (k), (l) correspond to (a),
(B) and (c) are temporally continued. further,
FIG. 4 is a continuation of FIG. 3 in time.

The confirm signal is written with data for 6 sync blocks (120 quadlets), such as the end of the header, then the end of BU0, and then the time when the first sync block of BU2 is written. It is done at the time.

As shown in FIGS. 3 and 4, the speed at which the VTR 1 writes data to the FIFO 2 and the transmission circuit 3
As for the speed at which data is read from O2, the speed at which the transmission circuit 3 reads data is faster. Therefore, while the transmission circuit 3 is reading data from the FIFO 2,
In order to prevent O2 from becoming empty, the transmission circuit 2 starts reading at a time t1 delayed from the time t0 when the track pulse d is received by an ITF delay.

It is desirable that the ITF delay is the shortest time to prevent the FIFO 2 from being emptied while the transmission circuit 3 is reading data. Figure 3 is ITF
This is an example when the delay is the shortest. If it is shorter than this, DP
18 cannot be read. Because DP18 is BU2
If the first sync block of 0 is not completely written, DP18
This is because no confirm signal indicating that the data to be transmitted has been written is not received.

Next, the ITF delay at this time will be described with reference to FIG. Packet writing is performed in 18.1
One packet is written in units of 2160 cycles with a clock of 259 MHz. That is, the packet is about 1
The data is written in a cycle of 19 μs (FIG. 5)
(A)). On the other hand, in the packet reading, after the ITF delay, one packet is read in units of 3072 cycles using a clock of 24.576 MHz. That is, the packet is read out at a period of about 125 μs (FIG. 5).
(B)).

In order to obtain the ITF delay, T0 and T1 in FIG. 5 are calculated, and the difference between them may be obtained. Since one header, 20 BUs of BU0 to BU19, and the first sync block of BU20 are exactly included between T0,
BU cycle × 21 + 80 (the number of clocks for one sync block) may be calculated. However, this time includes an error of 1% due to the circuit on the VTR side. If there is an error in the ITF delay, it is necessary to determine it so as to be longer, so 1% is added. If the above description is expressed as an equation, T0 = 21 × BU cycle + 1 sync block = (21 × 2160 + 80) × (1 / 18.1259M
Hz) × 1.01 = 2532 μs.

Similarly, since 18 DPs are inserted between T1, T1 = 18 × DP cycle = (18 × 3072) × (1
/24.576 MHz) = 2250 μs.

Therefore, ITF delay = T0−T1 = 282 μs.

Next, F which needs FIFO2 on the transmission side is required.
Find the IFO capacity. Before that, the timing at which the packet is actually read will be described. Packets are not always read immediately after the ITF delay. This is based on the IEEE-P1394 standard, and has three factors. One is based on the timing of a new cycle, the second is based on an Async packet, and the third is based on another Iso packet.

First, the operation based on the new cycle will be described with reference to FIG. The new cycle is the transmission path I in FIG.
/ F4, 6 are pulses regularly generated at a cycle of 125 μs, and communication is performed according to this cycle.

FIG. 6A shows a case where a new cycle has come immediately after the end of the ITF delay. in this case,
Since the new cycle has come immediately after the time t1 at which the ITF delay has ended, the packet is read out earliest as shown in FIG. 6B. On the other hand, FIG. 6C shows a case where the new cycle comes immediately before the ITF delay end time t1. In this case, the timing at which the packet is transmitted is 125 μs later than the end time t1 of the ITF delay as shown in FIG. Thus, in the case of the earliest case and the latest case, there may be a difference of 125 μs due to the timing relationship between the new cycle and the end time of the ITF delay.

Next, the packet delay due to the Async packet or another Iso packet will be described with reference to FIG. In the P1394 serial bus, IEEE-P1394 determines transmission of Async data such as computer data in addition to Iso data such as video data and audio data. In this embodiment, connection control commands and the like are transmitted. I do. The Async packet is allowed to protrude from the next new cycle by a maximum of 41 μs in the IEEE-P1394 standard (FIGS. 7A and 7B). In this case, like DPn,
When there is no Async packet, the packet is read at a maximum of 41 μs later than the timing at which the packet is read.

In the P1394 serial bus, a plurality of Iso packets can be transmitted on one bus in a time-division manner. When an Iso packet is transmitted from another device before an Iso packet that the user is trying to transmit, his / her own Iso packet is transmitted with a corresponding delay. In the case of this embodiment, the length of the Iso packet is 40 μs. Therefore, another Iso packet occupies the bus for a maximum of 125 μs−40 μs = 85 μs.

When all of the above three factors overlap, that is, a new cycle occurs immediately before the end of the ITF delay, the Async packet extends beyond 41 μs, another Iso packet occupies 85 μs, and occupies the front of the own Iso packet. , 251 μs.

The required FIFO capacity can be determined from this time. The data is accumulated most in the FIFO immediately before the reading starts. Reading starts the latest after 2 seconds since the packet was written.
Since 82 μs + 251 μs = 533 μs, the capacity of the FIFO at this time can be obtained.

The packets written up to this point have a header of 120 quadlets, audio data of 40 quadlets, video data of 400 quadlets, and a segment header of 1 quadlet.
61 quadlets is the capacity required for the FIFO.

[2]-(2) Operation of Transmitting Circuit Next, the operation of the transmitting circuit 3 will be described. The transmission circuit 3 performs the processing shown in FIG. The transmission circuit 3 is on the left side of FIG.
Is a packet read from the FIFO2, and the right side is a packet output from the transmission circuit 3 to the transmission path I / F4.

The packet read from the FIFO 2 has a segment header added to the beginning, and after that,
There are 25 quadlet data. The dc bit is 1 only at the beginning and 0 otherwise. This dc bit is used for synchronization. On the other hand, the data to be output to the transmission path I / F4 has a P1394 header and an AV header added to the beginning of each packet, and the dc bit is 1 at the beginning of each packet and 0 otherwise.

Therefore, the processing of the transmission circuit 3 is to remove the segment header, add the P1394 header and the AV header, and replace the dc bit. 9 and 10 show the format of the packet output from the transmission circuit 3.
Shown in Here, FIG. 9 shows the first packet in the segment, and FIG. 10 shows other packets.

As shown in FIG. 9, the data length is written in the upper 16 bits of the P1394 header of the first packet in the segment. In the present embodiment, 484 is obtained by adding 4 to the length (480 bytes) of the data portion of the packet. Next, the channel number is written over 8 bits. This is used to distinguish a plurality of Iso packets when they are transmitted on one bus. Following two reserved bits (reserved), a speed code is written over two bits. IEEE-1394 defines a plurality of transmission rates, and a speed code is used to specify the transmission rates.

A track number and a packet number are written in the AV header from the top. The VTR of this embodiment is 52
When recording video data of the 5/60 system, one screen is composed of 10 segments. Inside the VTR, each segment is numbered from 0 to 9, and this number is called a track number. Therefore, the number of the currently transmitted track is written in the AV header.
The packet number is from 0 to 2 for each packet in the segment
It has been shaken up to four.

After 7 reserved bits, 16 sync times are allocated. This is the time at which the ITF delay is added to the time at the beginning of the first packet of the segment, that is, the earliest time at which data is read from FIFO2. This time is F
It is used to generate a timing for reading data from the IFO 6.

Following the AV header, 120 quadlets of video data and audio data are written. FIG.
As shown in the above, the format of the second to 24th packets is obtained by removing the sync time from the format of the first packet.

FIG. 11 shows an internal block of the transmission circuit 8. First, a track pulse d indicating the start of data writing is output from the VTR to the latch 37. The latch 37 latches the cycle number when the track pulse d is input and the output from the cycle offset generator 39.

The cycle number / cycle offset generator 39 has an absolute time, and the value of the cycle offset continues to increase at 24.576 MHz and returns to 0 at 3072. Therefore, one cycle is performed in 125 μs. The cycle number increases by one when the cycle offset goes around. Therefore, it increases by one every 125 μs.

It is determined by IEEE-1394 that the cycle number and the cycle offset are always transmitted once every 125 μs by the CSP. Since this packet is generated by the transmission path I / F, it will not be particularly described here. Also, since the length of the packet is as short as 5 quadlets, there is almost no effect on the actual transmission of data, so that it is not considered when calculating the timing on the bus.

The value latched by the latch 37 is added to the adder 36.
Is output to The adder 36 adds the value of the register 35. In the register 35, an ITF delay is written. The value of the adder 36 is equal to the AV header generator 33 and the comparator 3
8 is output.

The AV header generator 33 writes the input from the adder 36 as a sync time in the AV header. On the other hand, the comparator 38 compares the output of the adder 36 with the output of the cycle number and the cycle offset generator 39 to obtain the cycle number and the cycle offset generator 39.
Output from the adder 36 outputs an instruction to read data to the data read control circuit 32.

Next, the processing in the data read control circuit 32 will be described with reference to FIGS.
The data read control circuit 32 first clears the packet counter 31 to 0 (S1). Next, the comparator 38
When there is an input from (S2), a read request h from the transmission path I / F4 is waited (S3). Then, when the read request h comes, the quadlet counter in the data read control circuit 32 is cleared to 0 (S4), and P1
The P1394 header generated by the 394 header generator 36 is output to the transmission path I / F4 (S5).

Further, when the read request h comes (S6),
The AV header generated by the AV header generator 123 is output to the transmission path I / F4 (S7). Then, when the next read request h comes (S8), the read signal f is sent to the FIFO2.
Is output, and the data g is read (S9).

If the read data is a segment header (S10), the packet counter is cleared to 0 (S11), the process returns to step S9, a read signal f is output to FIFO2, and data g is read (S9). ).
If the read data g is not a segment header, the read data is output to the transmission path I / F4, and 1 is added to the quadlet counter (S12).

If the result of the addition indicates that the quadlet counter is less than 120, the process returns to step S8, and if it is 120, 1 is added to the packet counter 31 (S13, S1).
4). As a result, if the value of the packet counter 31 is 25, the transmission of one segment is terminated, and the same processing is repeated from the processing S1 again. If it is less than 25, the process S4
Starts the process again (S15). Transmission is completed by the above operation.

[3] Operation on the Receiving Side [3]-(1) Packet Format and Reception Timing Next, reception will be described. The state of reception is shown in FIG. 14 and FIG. In FIG. 14, (a), (b), (c)
Are a packet written to the FIFO 8, a confirm signal, and a packet read from the FIFO 8, respectively. (D), (e), (f),... (J),
(K) and (l) are time series of the above (a), (b) and (c). FIG. 15 is a continuation of FIG. 14 in time.

The packet written in the FIFO 8 is the packet itself transmitted on the transmitting side. Also, while data is being read from the FIFO 8 on the receiving side,
In order to prevent the FIFO 8 from being emptied, the reading of the packet is started with a certain delay after the writing of the packet is started. A method of obtaining the delay time will be described later. The confirmation is performed in sync block units. And
Since a packet to be written is always transmitted with six sync blocks fixed, a confirm signal always occurs at the end timing of the packet.

Next, the receiving circuit 7 will be described with reference to FIG. The right side of FIG. 16 is a packet input to the receiving circuit 7 from the transmission line I / F 6, and the left side is a packet written to the FIFO 8.

The input packets constitute one segment with 25 packets. A P1394 header and an AV header are added to the head of each packet, and a footer is added following the data portion. Details of the footer will be described later. The dc bit is 1 at the beginning and end of the packet,
Otherwise it is zero.

On the other hand, the packet output from the receiving circuit 7 to the FIFO 8 has a segment header added to the beginning of the segment, and the data portion follows the segment header.
It continues five. The dc bit is 1 only at the beginning of the segment and is 0 at other than the beginning.

That is, the processing of the receiving circuit 7 is to remove the P1394 header, the AV header and the footer, add a segment header, and replace the dc bit. FIGS. 17 and 18 show the format of a packet output from the transmission path I / F 6 to the receiving circuit 7. Here, FIG. 17 shows the first packet in the segment, and FIG. 18 shows other packets.

The format of the packet output by the transmission path I / F 6 is almost the same as the format of the packet output by the transmission circuit 3 because the transmission path I / F 4 operates the packet, but is slightly different. Also, the format of the packet differs between the beginning and the rest of the segment.

First, the part of the packet shown in FIG. 17 that is different from the format of the transmission packet will be described. In the P1394 header at the head of the packet, there is no speed code added in the transmission packet, and tco
de is given. In tcode, the type of packet is written, and in the case of Iso data, 10 is written. The AV header and the data part are the same as the transmission packet. The speed code assigned to the P1394 header of the transmission packet is written in the footer. Also, CR
If C is written over the lower 4 bits and an error occurs in the data section during transmission, an error is written in the CRC. The format of the second to last packets shown in FIG. 18 is the same as the format of the first packet except for the sync time.

[3]-(2) Operation of Receiver Circuit Next, the configuration and operation of the receiver circuit will be described. FIG. 19 is a block diagram of the receiving circuit. When the write request j and data k output from the transmission path I / F 6 reach the P1394 header detector 73, the P1394 header detector 73
The 1394 header is removed, and the data excluding the P1394 header is output to the AV header detector 72. The AV header detector 72 extracts the sync time from the AV header and outputs the sync time to the adder 75. Also, the write signal s, P139
The data t and the packet number u excluding the 4 headers and the AV header are output to the data write control circuit 71.

The adder 75 adds a register 74 to the sync time.
, And outputs the result to the comparator 76. Register 7
Reference numeral 4 describes an IRF delay to be described later. The comparator 76 compares the cycle number, the cycle number generated by the cycle offset generator 77, and the cycle offset with the output value of the adder 75. If the cycle number and the cycle offset are larger than the output values of the adder 75, The track pulse r is output to the VTR.

As described above, within the VTR, the PLL 10 is synchronized based on the track pulse r input from the receiving circuit 7. Then, the read signal p is output to the FIFO 8 using the output signal of the PLL 10, and
From the data q.

As described above, in the receiving circuit 7 of this embodiment,
Since the AV header detector 72 extracts the sync time from the AV header before writing the received data to the FIFO 8, the track pulse r is output to the VTR 9 at the time when the IRF delay is added to the sync time, and the PLL 10 in the VTR 9 The data can be read from the FIFO 8 using the output signal of. On the other hand, if the sync time is extracted after reading from the FIFO 8, data is read out at a constant speed for the time being, and after checking the sync time, the PLL is synchronized, so that the processing becomes complicated.

Next, the operation of the data write control circuit 71 will be described with reference to FIG. The data read control circuit 71 receives the write signal s from the AV header detector 73, writes the packet number u, and if the packet number u is 0 (S21,
(S22, S23), the write signal 1 is output to the FIFO 8, the segment header is written, and the confirm signal n is output (S24).

Further, when the write signal s is input from the AV header detector 73 (S25), the dc bit of the written data is checked (S26). If the dc bit is 1, ie, the end of the packet, a confirm signal n is output (S28), and the same processing is performed again from step S21. If the dc bit is 0, the written data is output to the FIFO 8, and the data is written (S27). Then, the same processing is performed again from processing S25. With the above processing, the packet is received and
O8 can be written.

Next, a delay from when the data is written to the FIFO 19 on the receiving side to when the data is read is obtained. By calculating the delay, the minimum capacity required by the FIFO 8 can be calculated.

On the receiving side, the receiving circuit 7 outputs the track pulse r to the VTR 9 so that the VTR 9
The reading of the data q is started from O8. However, as described above, even if the track pulse r is output to the VTR 9, the data q is actually read by the signal p locked by the PLL 10 inside the VTR 9, so that the timing of the track pulse r and the data q Are not necessarily coincident with each other.

FIG. 21 shows this state. In this figure, (a) is a track pulse on the transmission side, (b) is a packet written from the VTR 1 on the transmission side to FIFO2,
(C) is a transmission packet when the transmission timing is the earliest, and (d) is a transmission packet when the transmission timing is the latest.

As shown in FIGS. 21C and 21D, 282 μs after 282 μs of the track pulse 101 on the transmission side.
Data packet DP0 is transmitted after μs + 251 μs = 533 μs. The sync time is written in DP0, which is the first packet in the segment, and the absolute time of the track pulse 101 + the time of the ITF delay is written here. That is, this time is the time when the receiving side receives the first data earliest.

On the receiving side, after the sync time, the VTR 9
, And starts reading data. Assuming that a track pulse is generated at this time, the timing of the virtual track pulse 102 is as shown in FIG.
(E). In practice, the receiving side
As shown in (f), a track pulse 103 is generated at the time obtained by adding the IRF delay to the sync time, and is output to the VTR 9. However, due to the accuracy of the PLL 10 inside the VTR 9, the track pulse inside the VTR is shown in FIG.
As shown in (1), the maximum deviation is ± 60 μs from the track pulse 103 on the receiving side. Then, data is read from the FIFO 8 at the timing of the track pulse inside the VTR. Therefore, the IRF delay is VTR
Even if the internal track pulse is output at the earliest timing (in the case of 104), the FIFO is read during packet reading.
You must decide that 8 will not be empty.

The reception timings shown in FIGS. 14 and 15 indicate timings at which the FIFO is most likely to be empty. If the read timing is further advanced, the BU
7 cannot be read. Because the DP8 including the last sink of the BU7 is read out from the FIFO
And a confirm signal needs to be output.

How to determine the IRF delay will be described with reference to FIG. In this figure, (a) is a track pulse on the transmission side, (b) is a packet written from the VTR 1 on the transmission side to the FIFO 2, (c) is a transmission packet when the transmission timing is the earliest, and (d) is a transmission packet. The transmission packet at the latest time, (e) is a track pulse on the receiving side, (f) is a track pulse inside the VTR, and (g) is a packet read from the FIFO.

This figure shows the case where data is read from the FIFO earliest, that is, the timing when the FIFO is most likely to be empty. Therefore, in this case, the IRF delay may be determined so that the FIFO does not become empty while data is being read.

To find the IRF delay, use T2 in FIG.
And T3 may be calculated and their difference may be taken. T2 is 40 μs of the last DP8 and DP0 in the time for eight DPs.
T2 = 8 × DP cycle + 251 μs + 40 μs = (8 × 3072) × (1 / 24.576 MHz) +2
51 μs + 40 μs = 1129 μs.

Then, T3 is equal to P from the time of eight BUs.
Since 60 μs due to the delay of LL10 is subtracted and a clock error of 1% when reading the BU is further taken into account, T3 = 8 × BU cycle−60 μs = (8 × 2160) × (1 / 18.1259 MHz) ×
0.99−60 μs = 893 μs. The clock error of 1% is multiplied by 0.99 so as to reduce it by 1%, since it is necessary to consider that the packet is read out earliest.

Therefore, IRF delay = T2-T3 = 398 μs.

Next, the required minimum capacity of the FIFO 8 will be described with reference to FIG. Data is stored in the FIFO 8 most when data is written at the earliest timing and read at the latest timing. In this case, the data is accumulated most immediately after the DP 24 is written. This is because the writing speed is faster than the reading speed on the receiving side.

To find the required minimum capacity of the FIFO 8,
T4 in FIG. 23 is obtained and T is calculated from the data amount for one segment.
What is necessary is to subtract the amount of data read during the period of 5. T4 is D
Since P is the time obtained by adding the time of the last DP24 to the time for 24 pieces, T4 = 24 × DP cycle + 40 μs = (24 × 3072) × (1 / 24.576 MHz) +
40 μs = 3040 μs.

Further, T5 is an IRF delay and P
T5 = 3040 μs−398 μs−60 μs = 2582
μs.

The data amount of one segment is 1 + 25 × 12 since one quadlet of the segment header and 25 DPs including 120 quadlets in one packet.
0 = 3001 quadlets.

The amount of data read during time T4 is 1 quadlet of the segment header and 1
2 BUs including 20 quadlets and 100 quadlets
Since there are seven pieces of audio data including one and 20 quadlets, 1 + 120 + 100 × 21 + 7 × 20 = 2
361 quadlets.

Therefore, the minimum necessary FIFO capacity is
This is a 640 quadlet obtained by subtracting 2361 quadlets from 3001 quadlets.

As described above, in the system shown in FIG. 1, the ITF delay is 282 μs, and the IRF delay is 3
Using a FIFO with a capacity of 98 μs and 561 quadlets on the transmitting side and 640 quadlets on the receiving side, it is possible to construct a data transfer device that does not overflow or become empty during transmission. It is.

As described above, the VT of the 525/60 system
The case where the reproduced data of R is transmitted to another VTR via the P1394 serial bus has been described.
It can also be applied to 25/50 systems and HD systems. Further, as long as the bus can transmit the Isync packet and the Async packet in a time division multiplexed manner, the present invention can be applied to a bus other than the P1394 serial bus. Further, the present invention provides data other than video data and audio data,
For example, the present invention can be applied to data transmission of a computer. The present invention can also be applied to a system in which the speed of data generated on the transmission side is higher than the speed of the transmission path.

[0092]

As described above in detail, according to the present invention, data is written to and read from the FIFO at different speeds, thereby making it possible to reduce the transmission speed between the transmission side device and the reception side device and the transmission line. When matching, data overflows from the FIFO during data writing / reading,
Data in the IFO can be prevented from being emptied. Further, it is possible to construct a data transfer device having a required minimum amount of FIFO found in advance.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transfer device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a format of data written to a FIFO and data read from the FIFO.

FIG. 3 is a diagram illustrating a packet transmission timing.

FIG. 4 is a diagram illustrating transmission timing of a packet following FIG. 3;

FIG. 5 is a diagram illustrating an ITF delay.

FIG. 6 is a diagram illustrating a packet delay due to a new cycle on the transmission side.

FIG. 7 is a diagram illustrating packet delay due to an Async packet or another packet on the transmission side.

FIG. 8 is a diagram illustrating a process performed by a transmission circuit.

FIG. 9 is a diagram illustrating a format of a packet of a first segment output by a transmission circuit.

FIG. 10 is a diagram illustrating a format of a packet after a second segment output by a transmission circuit.

FIG. 11 is a block diagram of a transmission circuit.

FIG. 12 is a diagram illustrating a part of the processing of the data read control circuit.

FIG. 13 is a diagram illustrating another part of the processing of the data read control circuit.

FIG. 14 is a diagram showing reception timing of a packet.

FIG. 15 is a diagram illustrating a reception timing subsequent to FIG. 14;

FIG. 16 is a diagram illustrating a process performed by the receiving circuit.

FIG. 17 is a diagram illustrating a format of a first segment packet input to the receiving circuit.

FIG. 18 is a diagram illustrating the format of a packet after the second segment input to the receiving circuit.

FIG. 19 is a block diagram of a receiving circuit.

FIG. 20 is a diagram illustrating the processing of the data write control circuit.

FIG. 21 is a diagram illustrating the timing of a track pulse on the receiving side.

FIG. 22 is a diagram illustrating the timing when the FIFO is most likely to be empty on the receiving side.

FIG. 23 is a diagram illustrating the timing at which data is accumulated most in the FIFO on the receiving side.

FIG. 24 is a diagram illustrating an example of a communication system using a P1394 serial bus.

FIG. 25 is a diagram equivalently describing the communication system of FIG. 24;

FIG. 26 is a diagram illustrating an example of a communication cycle in a communication system using a P1394 serial bus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission side VTR, 2 ... Transmission side FIFO, 3 ... Transmission circuit, 4 ... Transmission side transmission line I / F, 5 ... P1394 serial bus, 6 ... Reception side transmission line I / F, 7 ... Receiving circuit, 8 ... Reception side FIFO, 9 ... Reception side VTR

Claims (5)

(57) [Claims] A transmitting unit that writes the generated data packet to the temporary storage unit at a first speed and reads the data packet at a second speed different from the first speed after at least a first predetermined time; A first time obtained by adding a first predetermined time to the absolute time at which the data packet was generated is added to the data packet, and the data packet is transmitted. On the receiving side, the data packet written to the temporary storage means at the second speed is transmitted. A data transfer device, wherein data is read at the first speed from a second time obtained by adding a second predetermined time to the first time. 2. The data transfer device according to claim 1, wherein the first time added to the received data packet is read before writing the received data packet to the temporary storage means. 3. The transmitting side converts a plurality of types of data packets having different lengths into a fixed-length data packet by a temporary storage unit and transmits the fixed-length data packet. 3. The data transfer device according to claim 1, wherein the data transfer device converts the data packet into a plurality of different types of data packets. 4. The transmitting side receives a write acknowledgment signal from the temporary storage means every time a data packet of a fixed length is written to the temporary storage means. After that, the data packet is read from the temporary storage means,
4. The data transfer device according to claim 3, wherein the first predetermined time is determined so that a timing for reading the data packet does not come before a timing for inputting the write confirmation signal. 5. On the receiving side, each time a fixed-length data packet is written to the temporary storage means, a write confirmation signal is input to the temporary storage means, and after the write confirmation signal is input, the temporary storage means receives the write confirmation signal. A plurality of data packets having different lengths are read from the storage means, and the second predetermined data packet is read so that the data packet is not read before the write confirmation signal is input. Claim 3 where the time is set
A data transfer device according to claim 1.