JP3342385B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving a method for forming a contact hole.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described. In FIG. 11, an element isolation film 52 having a thickness of about 5000 ° is formed on a semiconductor substrate 51 of one conductivity type, for example, a P-type by a LOCOS method.
The gate insulating film 53 having a thickness of about 100 ° is formed in the active region except for the gate insulating film 2.
The gate electrode 54 is formed by forming and patterning a polysilicon film having a thickness of 0 °, for example.

In FIG. 12, an N-type impurity, for example, arsenic ion is accelerated with an acceleration voltage of about 100 KeV, about 5 × using the gate electrode 54 and the element isolation film 52 as a mask.
By implanting at a dose of 10 @ 15 / cm @ 2, the source / drain regions 55, 5
6 is formed. Then, an SiO 2 -based interlayer insulating film 57 is formed so as to cover the gate electrode 54.

In FIG. 13, after forming a resist film 58 having openings on the gate electrode 54 and the source / drain regions 55 and 56, the gate electrode 54 is wet or dry etched using the resist film 58 as a mask. Contact holes 59 and 60 are formed in contact with the upper and source / drain regions 55 and 56.

At this time, when dry etching is used, as shown in FIG. 13, a contact hole 59 contacting on the gate electrode 54 and a contact hole 6 contacting on the source / drain regions 55 and 56 on the substrate.
Since the depth is different from 0, the contact holes on the source / drain regions 55 and 56 do not open unless the etching is carried out at the same time and the gate electrode 54 is considerably over-etched 61.

There is also a method of masking twice. That is, after forming the interlayer insulating film 57 so as to cover the gate electrode 54 as shown in FIG. 12 described above, a first resist film 62 having an opening on the gate electrode 54 is formed as shown in FIG. After that, a first contact hole 63 is formed on the gate electrode 54 by wet or dry etching using the resist film 62 as a mask. Then, as shown in FIG. 15, the first resist film 62 is removed.

In FIG. 16, the first contact hole 63 is closed and the source / drain regions 55,
After a second resist film 64 having an opening is formed on the substrate 56, a second contact hole 65 that contacts the source / drain regions 55 and 56 is formed using the resist film 64 as a mask. However, in this case, a first resist film 62 is formed to form the contact holes 63 and 65, and after removing the resist film 62, a second resist film 64 is formed and removed. In addition, there is a problem that the photolithography process needs to be performed twice and the operation time naturally increases.

[0008]

Therefore, according to the present invention, it is possible to improve a method of forming contact holes when forming contact holes in regions having different thicknesses of an interlayer insulating film covering the gate electrode. An object of the present invention is to provide a method for manufacturing a device.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and comprises forming a gate insulating film on a semiconductor substrate of one conductivity type and then forming a gate electrode on the gate insulating film. Forming a source / drain region adjacent to the gate electrode by ion-implanting impurities of the opposite conductivity type using the gate electrode as a mask; and forming an interlayer insulating film so as to cover the gate electrode. Forming and forming a first resist film having an opening on the source / drain region while substantially opening a projection formed by the interlayer insulating film covering the gate electrode, and then using the resist film as a mask to form a gate. Forming a first contact hole in contact with the source / drain region while flattening a convex portion of the interlayer insulating film on the electrode; After forming a second resist film having an opening on the gate electrode and covering the first contact hole from above, a second contact hole for contacting the gate electrode is formed using the second resist film as a mask. And a forming step.

According to a second aspect of the present invention, after forming a gate insulating film on a semiconductor substrate of one conductivity type, a gate electrode is formed on the gate insulating film. Next, after the source / drain regions are formed adjacent to the gate electrode by ion-implanting impurities of the opposite conductivity type using the gate electrode as a mask, an interlayer insulating film is formed so as to cover the gate electrode. I do. Subsequently, after forming a first resist film having an opening substantially on the source / drain region and substantially opening a projection formed by an interlayer insulating film covering the gate electrode, the gate electrode is formed using the resist film as a mask. A first contact hole for contacting the source / drain region is formed while flattening the projection of the upper interlayer insulating film. Then, after forming a second resist film having an opening on the gate electrode while closing the first contact hole from above the first resist film, a contact is formed on the gate electrode using the resist film as a mask. Forming a second contact hole to be formed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, after an element isolation film 2 having a thickness of about 5000 ° is formed on a semiconductor substrate 1 of one conductivity type, for example, a P-type by a LOCOS method, a film thickness of about 100 ° is formed in an active region excluding the element isolation film 2. The gate electrode 4 is formed by forming, for example, a polysilicon film having a thickness of about 2000 ° on the gate insulating film 3 and patterning the same.

In FIG. 2, an N-type impurity such as arsenic ion is accelerated by using the gate electrode 4 and the element isolation film 2 as a mask at an acceleration voltage of about 100 KeV and about 5 × 10 15.
The source / drain regions 5 and 6 are formed adjacent to the gate electrode 4 by implanting at an implantation amount of / cm <2>. Then, the SiO 2 is coated so as to cover the gate electrode 4.
A two-system interlayer insulating film 7 is formed.

In FIG. 3, after forming a first resist film 8 having openings on the gate electrode 4 and the source / drain regions 5 and 6, the resist film 8 is used as a mask to perform wet or dry etching. A first contact hole 9 that contacts the gate electrode 4 is formed, and a second contact hole 10 that is partially opened in the interlayer insulating film 8 on the source / drain regions 5 and 6 is formed.

At this time, as shown in FIG.
A first contact hole 9 contacting the upper portion and a second contact portion contacting the source / drain regions 5 and 6 on the substrate.
Since the contact hole 10 has a depth different from that of the contact hole 10, the contact hole on the source / drain regions 5 and 6 is not opened. In FIG. 4, after forming a second resist film 11 having an opening on the source / drain regions 5 and 6 while covering the first contact hole 9 from above the first resist film 8, Using the film 11 as a mask, a third contact hole 12 that contacts the source / drain regions 5 and 6 is formed.

As a result, as shown in FIG. 5, the contact holes 9 and 12 contacting the gate electrode 4 and the source / drain regions 5 and 6 are optimal without significantly overetching the gate electrode as in the prior art. It can be formed with a large over-etching amount. Further, the second resist film 11 is formed on the first resist film 8 from above.
By overlapping, the first step of removing the resist film as in the related art can be omitted, and the number of working steps can be reduced.

Further, another embodiment of the present invention will be described in detail with reference to the drawings. 6, a gate insulating film 22 having a thickness of about 100 ° is formed on a semiconductor substrate 21 of one conductivity type, for example, a P-type, and a polysilicon film having a thickness of about 2000 ° is formed on the gate insulating film 22. Then, the gate electrode 23 is formed by patterning.
By using the gate electrode 23 as a mask, an N-type impurity such as arsenic ion is implanted at an acceleration voltage of about 100 KeV and an implantation amount of about 5 × 10 15 / cm 2, so that the source is adjacent to the gate electrode 23. -Form drain regions 24 and 25. Then, an SiO2 based interlayer insulating film 26 is formed so as to cover the gate electrode 23. At this time, as shown in FIG. 6, the interlayer insulating film 26 covering the gate electrode 23 is formed by the thickness of the gate electrode 23.
Is formed with a convex portion 27.

Referring to FIG. 7, a first resist film 28 is formed, which substantially has an opening in the projection 27 of the interlayer insulating film 26 covering the gate electrode 23 and has openings on the source / drain regions 24 and 25. Thereafter, as shown in FIG. 8, the projection 27 on the gate electrode 23 is flattened by wet or dry etching using the first resist film 28 as a mask to form a flattened film 29,
A first contact hole 30 is formed on the source / drain regions 24 and 25 to make contact.

In FIG. 9, the first resist film 28
Forming a second resist film 31 having an opening on the gate electrode 23 while covering the first contact hole 30 from above, and then contacting the gate electrode 23 with the resist film 31 as a mask. A contact hole 32 is formed. As a result, as shown in FIG. 10, the contact holes 30, 32 contacting the gate electrode 23 and the source / drain regions 24, 25 are optimally over-etched without considerably over-etching the gate electrode as in the prior art. It can be formed by quantity. Also, the second resist is applied from above the first resist film 28.
By forming the resist film 31 in a stacked manner, the first step of removing the resist film as in the conventional case can be omitted, and the number of working steps can be reduced. Further, the protrusion 27 can be flattened by the interlayer insulating film 26 covering the gate electrode 23.

[0019]

As described above, according to the present invention, a contact hole contacting a gate electrode and a source / drain region can be formed with an optimum amount of over-etching. Further, by forming the second resist film over the first resist film, the first step of removing the resist film as in the related art can be omitted, and the number of working steps can be reduced.

Further, the protrusions can be made flat by the interlayer insulating film covering the gate electrode.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a first sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a second sectional view illustrating the method for manufacturing the semiconductor device according to another embodiment of the present invention;

FIG. 8 is a third sectional view illustrating the method for manufacturing the semiconductor device according to another embodiment of the present invention;

FIG. 9 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to another embodiment of the present invention;

FIG. 10 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to another embodiment of the present invention;

FIG. 11 is a first cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 12 is a second cross-sectional view illustrating the conventional method for manufacturing a semiconductor device.

FIG. 13 is a third cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 14 is a first diagram illustrating a method of manufacturing another conventional semiconductor device.
FIG.

FIG. 15 is a second view showing another conventional method for manufacturing a semiconductor device.
FIG.

FIG. 16 is a third view showing another conventional method for manufacturing a semiconductor device.
FIG.

Claims (1)

(57) [Claims] A step of forming a gate insulating film on a semiconductor substrate of one conductivity type and then forming a gate electrode on the gate insulating film; and ion-implanting impurities of the opposite conductivity type using the gate electrode as a mask. This allows the source
Forming a drain region; forming an interlayer insulating film so as to cover the gate electrode; and substantially opening a projection formed by the interlayer insulating film covering the gate electrode, and forming the interlayer insulating film on the source / drain region. After forming a first resist film having an opening, the resist film is used as a mask to planarize a convex portion of an interlayer insulating film on a gate electrode and to form a first contact hole for contacting a source / drain region. step and the first resist film first of said gate electrode and said second resist film as a mask after forming the second resist film having an opening over the gate electrode with closing the contact hole from the top of Forming a second contact hole to be in contact therewith.