JP3343573B2 - Radio equipment with variable modulation / demodulation characteristics - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio device capable of changing a modulation characteristic in a programmable manner used in a mobile communication system or the like, and more particularly to a radio device realizing a radio function by software.

[0002]

2. Description of the Related Art In general, a conventional radio apparatus is designed and manufactured exclusively for a predetermined modulation scheme and transmission rate, and cannot cope with different modulation schemes and transmission rates.

[0003] However, with the rapid development of mobile communication systems in recent years, the usage of users has been diversified from conventional voice calls to mail and data fax communications. With the diversification of such use forms, for example, a so-called multi-mode terminal in which a PHS and a PDC are housed in one housing and both systems can be used has been emerging.

[0004] In order to cope with such multi-mode operation, it is necessary to enable transmission and reception corresponding to a plurality of modulation and demodulation schemes having different specifications with one radio. However, since the conventional wireless device was specially made for one modulation and demodulation method and transmission rate as described above, in order to generate signals of different modulation methods, a plurality of modulation and demodulation units and filter units were prepared. It was necessary to switch between them and use them.

[0005] A radio apparatus realized by combining such a plurality of modulation / demodulation units is configured as shown in FIG. Blocks 101 and 10 having modulation and demodulation units and filter units respectively corresponding to modulation schemes A, B and C
2 and 103 are provided, and are switched by switches 104 and 105 according to the modulation method to be used, and a communication operation is performed. In practice, before and after the device shown in FIG.
An F analog section, an AD / DA conversion section, an audio codec and a channel codec section are connected, but are omitted here.

Block 10 of a modulation / demodulation unit and a filter unit
In 1, 102 and 103, a receiving filter for filtering a received signal, a detector for returning a received signal to an original data sequence, and a modulator for generating a modulated signal from an original transmission data sequence according to a desired system A function of a transmission filter for filtering extra frequency components is realized, but since these functions are usually realized by a dedicated LSI (random logic), it is impossible to change the functions and characteristics. .

As described above, in the conventional radio apparatus, the filtering and modulation / demodulation functions are realized by fixed hardware such as random logic. Therefore, when a plurality of radio systems are supported, a plurality of modulation / demodulation sections and filter sections are provided. Had to be prepared, and they had to be switched.

In the case of transmitting and receiving signals of a plurality of different modulation / demodulation schemes and transmission rates in such a conventional configuration, there is a serious drawback that the circuit becomes large-scale and power consumption increases. There is also a drawback that communication cannot be performed at other than the prepared modulation and demodulation method and transmission rate. That is, the conventional wireless device has no versatility with respect to the modulation / demodulation method and the transmission rate.

[0009]

As described above, in a conventional radio apparatus, a plurality of modulation / demodulation circuits and filter circuits corresponding to a plurality of modulation schemes and transmission rates are required to support a plurality of modulation schemes and transmission rates. There is a problem that the scale of the wear becomes large, and there is a problem that it can cope only with a limited modulation and demodulation method and a transmission rate, and is poor in versatility.

The present invention solves such a problem,
It is an object of the present invention to provide a wireless device capable of changing modulation / demodulation characteristics which can be generally used for a plurality of modulation / demodulation methods and transmission rates.

[0011]

In order to solve the above-mentioned problems, in a radio apparatus according to the present invention, which can change modulation and demodulation characteristics, a predetermined transmission data is modulated based on a set modulation and demodulation method to modulate a modulated signal. DSP for performing modulation processing to be generated and demodulation processing to demodulate a received signal to generate original data
Unit, an FPGA unit for performing a filtering process on a transmission signal and a reception signal, and a unit for converting an input to the DSP unit and the FPGA unit into a digital signal, and converting an output from the DSP unit and the FPGA unit into an analog signal. An AD / DA conversion unit; and a CPU unit that controls the DSP unit, the FPGA unit, and the AD / DA conversion unit via a bus, and based on control from a personal computer connected to the CPU unit via a predetermined interface. The basic feature is that the DSP section and the FPGA section are controlled to change the modulation / demodulation scheme, the transmission rate, and the filter characteristics in the filter processing.

More specifically, for changing the modulation / demodulation method, for example, the CPU reads out a default modem program having modulation and demodulation processing functions based on a plurality of modulation / demodulation methods from a storage device when the power is turned on, and reads the internal modem inside the DSP unit. And rewrites the value in the data memory inside the DSP unit via the bus with reference to a table in which the correspondence between the value in the data memory and the modulation / demodulation method is described in advance. Is realized by:

For the change of the transmission rate, for example, FP
The frequency ratio of the sampling clock applied to the digital filter inside the GA unit to the transmission rate, and the tap length and symbol length of the digital filter are all set to constant values, and the CPU unit changes the frequency of the sampling clock. This is realized by changing the bandwidth of the digital filter.

To change the digital characteristics, for example, the CPU section calculates a tap coefficient based on a desired transfer function of a digital filter inside the FPGA section, and downloads the tap coefficient to the digital filter via a bus. Is realized by:

In addition, the FP is provided by a personal computer.
A tap coefficient is calculated based on a desired transfer function of a digital filter inside the GA section, and the tap coefficient is supplied to the CPU section via the interface, and then downloaded to the digital filter via the bus. Also, a change in filter characteristics is realized.

According to another aspect of the present invention, there is provided a radio apparatus capable of changing modulation / demodulation characteristics, which modulates predetermined transmission data to generate a modulation signal based on a set modulation / demodulation method, and demodulates a reception signal. A DSP unit that performs demodulation processing for generating original data by performing a filtering process on a transmission signal and a reception signal;
An AD / DA conversion unit for converting an input to the PGA unit into a digital signal, and converting an output from the DSP unit and the FPGA unit into an analog signal; a DSP unit, an FPGA unit, and an A / DA conversion unit;
A CPU for controlling the D / DA conversion unit via a bus, wherein the CPU operates according to a control program read from the ROM at the time of start-up, and operates in accordance with a control signal externally supplied via an external I / O port. And FPGA
By controlling the unit, the modulation / demodulation method, the transmission rate, and the filter characteristics in the filter processing are changed.

As described above, according to the present invention, a wireless device capable of transmitting and receiving at various modulation / demodulation schemes and transmission rates without a plurality of modulation / demodulation units and filter units is realized. Therefore, by using the wireless device of the present invention, it is possible to cope with various wireless systems, and it is possible to extremely easily realize multi-mode operation.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. (Basic Configuration of Radio Apparatus) FIG. 1 shows a basic configuration of a radio apparatus capable of changing modulation / demodulation characteristics according to an embodiment of the present invention. This wireless device is a DSP (Digital Signal Proces).
sor) board 11 and FPGA (Field Programmable Gate)
Array) board 12, AD / DA conversion board 13,
CPU board 14 and bus 1 for connecting these
6 and an interface 17 for connecting the CPU board 14 and a PC (personal computer) 15.

A DSP board 11, an FPGA board 12,
The AD / DA conversion board 13 and the CPU board 14 each include a DSP, a PGA, an AD / DA converter, a CPU chip, and respective peripheral circuits.

The DSP board 11 modulates transmission data according to a predetermined modulation scheme based on a set modulation / demodulation scheme, generates a modulation signal, and transmits the modulated signal to an antenna (not shown) via a transmission circuit. A demodulation processing function of demodulating a signal received from an antenna to generate original data is realized. According to this configuration, the modulation and demodulation functions are realized by the software of the DSP. Therefore, these modulation and demodulation functions can be switched by changing the software while using the same hardware.

The FPGA board 12 implements a digital filter (in particular, an FIR filter) that implements a filtering process on a reception signal and a transmission signal. In this case, since the digital filter is realized by the programmable logic by the FPGA, the filter characteristics can be switched while using the same hardware as in the case of the modulation / demodulation function of the DSP unit 11.

The main object of the present invention is to provide a method for efficiently changing the modulation / demodulation function of the DSP board 11 and the filter function of the FPGA board 12.

(Basic Operation of Wireless Device) Next, a basic operation of the wireless device according to the present embodiment will be described. At the time of reception, a reception signal in a radio frequency band output from an antenna (not shown) is appropriately amplified, input to the AD / DA conversion board 13, sampled by an appropriate sampling clock, and converted into a digital signal. The received signal converted to a digital signal is
Input to the board 12. In the FPGA board 12, the input received signal is subjected to filtering (filtering) by a digital filter. FPGA board 2
Is further input to the DSP board 11 and subjected to demodulation processing.

Next, at the time of transmission, the transmission data is D
A transmission signal is generated by being input to the SP board 11 and subjected to modulation processing. This transmission signal is FPGA
The signal is filtered by the board 12 and converted into an analog signal by the AD / DA conversion board 13 to become a transmission signal in a predetermined radio frequency band, which is transmitted as a radio wave by an antenna via a transmission circuit (not shown).

At the time of reception and transmission described above, the CP
The U board 14 controls the DSP board 11 and the FP under the control of the PC 15 connected via the interface 17.
The GA board 12 and the AD / DA conversion board 13 are connected to the bus 1
6 is controlled.

The bus 16 includes, for example, a VME bus and a PCI
A general-purpose bus such as a bus or a bus of a unique specification can be used. As the interface 17, for example, RC232C or Ethernet can be used.

(Modification of Modulation / Demodulation Parameters) Next, an outline of a method of modifying modulation / demodulation parameters (modulation / demodulation method, transmission rate and filter characteristics) which is a feature of the present invention will be described.

First, a command for changing the modulation / demodulation method is sent from the PC 15 to the CPU board 14. The change command is sent from the CPU board 14 to all or a part of the DSP board 11, the FPGA board 12, and the AD / DA conversion board 13 via the bus 16.

DSP board 1 receiving this change command
1. FPGA board 12 and AD / DA conversion board 13
The modulation and demodulation parameters are changed by changing the characteristics of the wireless device by changing a predetermined operation parameter. Hereinafter, a method of changing the modulation / demodulation method, the transmission rate, and the filter characteristics (also referred to as filter type and filter shape) will be described.

First, when changing the modulation / demodulation method, the PC 15
Sends a modulation / demodulation method change command to the CPU board 14. CPU board 1 receiving this change command
4 sends a change command in a predetermined form via the bus 16 to the DSP board 11 that performs the modulation / demodulation processing. The DSP board 11 that has received this change command changes the modulation / demodulation method used for the actual operation.

On the other hand, when the transmission rate is changed, the PC 15
Sends a command to change the transmission rate to the CPU board 14. CPU board 1 receiving this change command
4 sends a change command in a predetermined form to the DSP board 11 and the FPGA board 12 via the bus 16.
DS receiving the change command from the CPU board 14
The P board 11 and the FPGA board 2 change the transmission rate.

Next, when changing the filter characteristics, the PC1
5 sends a transmission rate change command to the CPU board 14. The CPU board 14 that has received this change command sends a predetermined form of change command to the FPGA board 12 via the bus 16. This CPU board 1
The FPGA board 12 that has received the change command from the
Change the filter characteristics used for the actual operation.

(Regarding DSP Board 11) FIG.
FIG. 3 is a functional block diagram showing a detailed configuration of an SP board 11; As shown in FIG.
21, a program memory 22, a data memory 23, a program bus 24, a data bus 25, and other peripheral circuits 26.

The program memory 22 is an area for loading a program operating on the DSP 21.
1 is a program memory 22 via a program bus 24
It reads the above program and performs signal processing operations according to its contents.

The data memory 23 is an area for temporarily storing input data processed by the DSP 21 and output data after processing from the DSP 21. The data memory 23 is read and written via a data bus 25. The data memory 23 uses the peripheral circuit 26 to
It is possible to access indirectly from the U board 14 via an external bus (the bus 16 shown in FIG. 1).

However, these functions are the same as those of the conventional general-purpose D
The feature of the present invention, which is an extension of the device equipped with the SP, is that the modulation / demodulation function is efficiently switched using these functions.

Next, the operation of the wireless device based on the configuration of the DSP board 11 of FIG. 2 will be described. First, a default program operating on the DSP board 11 is read from a storage device, for example, a hard disk device connected to the CPU board 14 when the power of the entire device is turned on, and the program is sent to the DSP board 11 via the bus 16. . This default program is downloaded to the program memory 22 via the peripheral circuit 26 in FIG. The DSP 21 performs a modulation / demodulation process based on the program loaded in the program memory 22.

The major feature of this default program is that it has a plurality of modulation / demodulation functions in advance, which is significantly different from the modulation / demodulation unit of a conventional radio apparatus having only one modulation / demodulation function. For example, this default program is π / 4-QPSK, QPSK, BPSK, 2
It has a modulation / demodulation function of various modulation / demodulation methods such as values FSK and GMSK, and the function is variable by parameter setting from the outside, so that the modulation / demodulation method can be changed.

(How to change the modulation / demodulation method)
With reference to FIGS. 3 and 4, a method of changing the modulation / demodulation method will be described in detail. First, it is assumed that when a modulation / demodulation operation is being performed by a certain modulation / demodulation method (step 41), a change command instructing to change the modulation / demodulation method is generated from the PC 15. This change command is sent to the CPU board 15 and the bus 1
6 to the DSP board 11. In the DSP board 11, the peripheral circuit 26 receives a change command,
Based on this, the contents of the predetermined address 31 (modulation scheme determination memory address) shown in FIG. 3 on the data memory 23 are rewritten (step 42).

Next, the CPU board 15 is the DSP board 1
An interrupt is issued by sending an interrupt command to the DSP 21 on the step 1 (step 43). The interrupted DSP 21 reads the value of the modulation scheme determination memory address 31 on the data memory 23 (step 44).

The correspondence between the value on the data memory 23 (the value of the modulation scheme determining memory address 31) and the modulation / demodulation scheme is defined (described) in advance as a table as shown in the following table. The modulation / demodulation method is changed according to the value on 23 (step 45), and thereafter, the process returns to step 41 to perform the modulation / demodulation operation based on the changed modulation / demodulation method.

[0042] For example, if the modulation and demodulation operation is currently performed by GMSK,
The value of the modulation / demodulation scheme determination address 31 on the data memory 23 is “0001”. At this time, when the modulation / demodulation method is changed to QPSK, the value of the modulation / demodulation method determination address 31 is rewritten to “1001” in accordance with the procedure shown in FIG. It is changed to perform the modulation / demodulation operation. In this way, the modulation / demodulation method can be changed without stopping the DSP program.

(Regarding FPGA Board 12) FIG.
FIG. 3 is a functional block diagram illustrating a detailed configuration of the FPGA board 12. As shown in the figure, the FPGA board 12 receives the input data 51, generates a sampling clock 54 synchronized with the input data 51, filters the input data 54 using the sampling clock 54, and outputs the output data 55 From the digital filter 53 that generates

The digital filter 53 is composed of an FIR filter for filtering the input data 51 based on a given tap coefficient. The clock generation unit 52 generates a sampling clock 54 having an appropriate frequency in accordance with an instruction from the CPU board 14 in FIG.

(About the method of changing the transmission rate)
A method of changing the transmission rate based on the configuration in FIG. 5 will be described. The frequency ratio of the sampling clock 54 to the transmission rate is a constant value regardless of the transmission rate.
Specifically, this frequency ratio is set to a predetermined value (for example, 8) necessary to obtain a desired error rate characteristic and modulation accuracy. The tap length of the digital filter 53, that is, the number of tap coefficients is fixed. This means that the impulse response length of the digital filter 53 with respect to the symbol rate of the input data 51 is fixed.

With such a configuration, the bandwidth of the digital filter 53 can be changed only by changing the frequency of the sampling clock 54 applied to the digital filter 53 without rewriting the tap coefficients.

That is, when only the transmission rate is changed without changing the filter characteristics (filter shape) of the digital filter 53, the parameters having a large amount of information, such as tap coefficients, to be given to the digital filter 53 are particularly required. There is no need to re-apply, and the bandwidth is changed simply by changing the sampling clock 54 to be applied to the digital filter 53. Therefore, the transmission rate can be changed extremely easily and with a small amount of information.

For example, if the frequency ratio (oversampling ratio) of the sampling clock 54 to the transmission rate is 8
And the digital filter 53 has a tap coefficient α = 0.5
If the transmission rate is 1 kbaud (= 1 ksymbol / sec) and the sampling clock 54 is set to 8 ksymbol / sec, the cutoff frequency of the root roll-off filter is automatically set. Is set to 1 kHz. The transmission rate is 10kbaud
If the sampling clock 54 is changed to
By simply changing the frequency to kHz, the cutoff frequency of the root roll-off filter is set to 10 kHz.

The digital filter (FIR filter) 53 shown here can be realized with programmable logic such as FPGA and PLD.
The present invention is not limited to this. For example, the filter may be realized by a filter in which tap coefficients are stored in a RAM, a ROM, or the like, and the tap coefficients are read out according to the sampling clock 54. Also, the digital filter 53 can be realized by using a dedicated LSI whose shape can be changed by externally giving a tap coefficient as a parameter, for example, a DDC (Digital Down Converter). Of course, if the digital filter 53 is a DSP or M
Even if realized by software such as a PU, the features of the present invention are not impaired at all.

(Method of Changing Filter Characteristics) Next, a method of changing the characteristics (filter characteristics) of the digital filter 53 will be described with reference to FIG. According to the example shown in FIG. 6, the desired transfer function 62 of the digital filter 53 is given to the CPU board 14. The CPU board 14 calculates a necessary tap coefficient 61 based on the given transfer function 62. The data of the tap coefficient 61 is supplied to the FPGA board 12 that realizes the digital filter 53 through the bus 16, and the tap characteristic of the digital filter 53 is rewritten, thereby changing the filter characteristics.

When the tap coefficient 61 is directly supplied from the outside, it is necessary to obtain a tap coefficient from a transfer function desired by a designer in advance, and to convert the tap coefficient into necessary data by a digital filter 53 and supply the data. According to the configuration of the embodiment, it is possible to change the filter characteristics of the digital filter 53 extremely easily by externally providing only the required shape of the digital filter 53, that is, only the transfer function 62.

(Other Methods of Changing Filter Characteristics)
Next, another method for changing the filter characteristics of the digital filter 53 will be described with reference to FIG. In this example, the transfer function 6 of the digital filter 53 is
The necessary tap coefficients are calculated based on the data of the CPU board 1 through the interface 17.
Once sent to 4. From the CPU board 14,
The received tap coefficient data is transferred to the FP
The digital filter 53 is supplied to the GA board 12 and the tap coefficients are rewritten by this.
Of the filter characteristic is realized.

Therefore, the digital filter 53 can be very easily formed by this method as in the method described with reference to FIG.
Can be changed.

(Other Embodiments) In the above embodiment, as shown in FIG. 1, the CPU board 14 and the PC 15 are connected via the interface 17, and the CPU board 14 is a control program operating on the PC 15. The configuration that operates according to the above is shown.

On the other hand, as shown in FIG. 8, these control programs are stored in the ROM 81 or the like as boot programs instead of the PC 15 and the control programs operating thereon, and the CPU board 14 It is possible to read the boot program and control itself. In FIG. 8, P in FIG.
There is no C15, and a ROM 81 and an external I / O port 82 are added instead.

When the wireless device is started, the boot program is read from the ROM 81 to the CPU board 14, and the control program is automatically executed. Changes in the modulation method, transmission rate, and filter characteristics after startup are performed by a control signal based on a button operation or the like via the external I / O port 82.
A board 14 is provided, and is realized by the CPU board 14 controlling the DSP board 11 and the FPGA board 12 according to the control signal. As described above, also in the present embodiment, basically the same effects as in the first embodiment can be obtained.

[0057]

As described above, according to the present invention, signals of a plurality of modulation / demodulation schemes and transmission rates can be transmitted / received by one radio apparatus, so that a plurality of systems can be handled by one radio. When used for various applications, a plurality of modulation / demodulation methods and transmission rates can be obtained without providing a plurality of modulation / demodulation units and filter units, and there is an effect that the change can be made very easily.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a wireless device capable of changing a modulation / demodulation characteristic according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a detailed configuration of a DSP board.

FIG. 3 is a diagram for explaining a modulation / demodulation method determination address on a data memory in a DSP board;

FIG. 4 is a flowchart showing a procedure for changing a modulation / demodulation method;

FIG. 5 is a block diagram showing a detailed configuration of the FGPA board.

FIG. 6 is a block diagram.

FIG. 7 is a block diagram.

FIG. 8 is a block diagram showing a schematic configuration of a wireless device capable of changing modulation / demodulation characteristics according to another embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a wireless device that supports a plurality of modulation and demodulation schemes based on the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... DSP board 12 ... FPGA board 13 ... AD / DA conversion board 14 ... CPU board 15 ... Personal computer 16 ... Bus 21 ... CPU 22 ... Program memory 23 ... Data memory 24 ... Program bus 25 ... Data bus 26 ... Peripheral circuit 31 ... Memory address for determining modulation / demodulation method 52... Clock generator 53... Digital filter 81... ROM 82.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Harada 3-4 Hikarinooka, Yokosuka City, Kanagawa Prefecture Within the Yokosuka Radio Communications Research Center, Communications Research Laboratory, Ministry of Posts and Telecommunications (56) References JP-A-8-56185 (JP, A) JP-A-7-135447 (JP, A) JP-A-6-6390 (JP, A) JP-A-8-107427 (JP, A) JP-A-2001-189675 (JP, A) JP-A-6-343085 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (6)

(57) [Claims] 1. A modulation process for modulating predetermined transmission data based on a set modulation and demodulation method to generate a modulation signal and a demodulation process for demodulating a reception signal and generating original data.
An SP unit, an FPGA unit for performing a filtering process on the transmission signal and the reception signal, and converting an input to the DSP unit and the FPGA unit into a digital signal, and converting an output from the DSP unit and the FPGA unit into an analog signal. An AD / DA conversion unit for conversion; and a CPU unit that controls the DSP unit, the FPGA unit, and the AD / DA conversion unit via a bus, and the CPU unit is connected via a predetermined interface. D based on control from a personal computer
A modulation and demodulation characteristic changeable radio apparatus characterized in that the modulation and demodulation method, the transmission rate, and the filter characteristic in the filter processing are changed by controlling an SP unit and an FPGA unit. 2. The CPU section reads a default modem program having a modulation and demodulation processing function based on a plurality of modulation and demodulation schemes from a storage device when power is turned on, and reads the DSM.
A table in which the values in the data memory inside the DSP unit are downloaded to the program memory inside the P unit via the bus, and the correspondence between the values in the data memory and the modulation / demodulation method is described in advance. 2. The wireless device according to claim 1, wherein the modulation / demodulation method is changed by rewriting with reference to FIG. 3. The FPGA section has a digital filter therein, and a frequency ratio of a sampling clock applied to the digital filter to the transmission rate, and a tap length and a symbol length of the digital filter are all constant values. 2. The modulation / demodulation characteristic according to claim 1, wherein the CPU changes the transmission rate by changing a bandwidth of the digital filter by changing a frequency of the sampling clock. Possible wireless device. 4. The CPU section calculates a tap coefficient based on a desired transfer function of a digital filter inside the FPGA section, and downloads the tap coefficient to the digital filter via the bus. The wireless device according to claim 1, wherein the filter characteristic is changed by changing the modulation / demodulation characteristic. 5. The computer according to claim 1, wherein
A tap coefficient is calculated based on a desired transfer function of a digital filter inside the PGA section, and the tap coefficient is supplied to the CPU section via the interface. The wireless device according to claim 1, wherein the filter characteristic is changed by downloading. 6. A modulation process for modulating predetermined transmission data based on a set modulation and demodulation method to generate a modulation signal and a demodulation process for demodulating a reception signal and generating original data.
An SP unit, an FPGA unit for performing a filtering process on the transmission signal and the reception signal, and converting an input to the DSP unit and the FPGA unit into a digital signal, and converting an output from the DSP unit and the FPGA unit into an analog signal. An AD / DA conversion unit for conversion; and a CPU unit for controlling the DSP unit, the FPGA unit, and the AD / DA conversion unit via a bus, wherein the CPU unit operates according to a control program read from a ROM at startup. Operating, controlling the DSP unit and the FPGA unit in accordance with a control signal given via an external I / O port, thereby changing the modulation / demodulation method, the transmission rate, and the filter characteristics in the filter processing. A wireless device whose modulation and demodulation characteristics can be changed.