JP3344181B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving I / O device on one of two transparent insulating substrates which are superposed via a liquid crystal layer.
The present invention relates to a liquid crystal display device having a flip-chip type liquid crystal display element directly mounted with C.

[0002]

2. Description of the Related Art For example, in a liquid crystal display element (that is, a liquid crystal display panel) of an active matrix type liquid crystal display device, of two transparent insulating substrates made of glass or the like which are arranged to face each other via a liquid crystal layer, A gate line group extending in the x direction and juxtaposed in the y direction on a surface of the one glass substrate facing the liquid crystal layer; and a gate line group insulated from the gate line group and extending in the y direction; Are formed in parallel with each other.

Each region surrounded by the group of gate lines and the group of drain lines becomes a pixel region, and the pixel region includes, for example, a thin film transistor (T) as a switching element.
FT) and a transparent pixel electrode.

When a scanning signal is supplied to the gate line, the thin film transistor is turned on, and a video signal from the drain line is supplied to the pixel electrode via the turned on thin film transistor.

It is to be noted that not only each drain line of the drain line group, but also each gate line of the gate line group is extended to the periphery of the transparent insulating substrate to form external terminals. A plurality of driving ICs (semiconductor integrated circuits) constituting the video driving circuit and the gate scanning driving circuit which are connected to each other are externally mounted around the transparent insulating substrate. That is, a plurality of tape carrier packages (TCPs) each mounting these driving ICs are externally provided around the substrate.

However, since the transparent insulating substrate has a configuration in which a TCP on which a driving IC is mounted is externally mounted, a gate line group and a drain of the transparent insulating substrate are formed by these circuits. The area occupied by a region (usually called a frame) between the outline of the display region formed by the intersection region with the line group and the outline of the outer frame of the transparent insulating substrate increases, and the liquid crystal display This is contrary to the desire to reduce the external dimensions of the module.

Therefore, in order to solve such a problem as much as possible, that is, in response to a demand to increase the density of the liquid crystal display element and to reduce the outer shape of the liquid crystal display module as much as possible, TCP components are not used. There has been proposed a configuration in which an image driving IC and a gate scanning driving IC are directly mounted on a transparent insulating substrate. Such a mounting method is called a flip chip method or a chip-on-glass (COG) method.

The present invention is applicable to the flip-chip mounting method.

By the way, in the conventional flip-chip type connection structure, a bump (protruding electrode) BUMP is formed on the lower surface of the driving IC, and for example, the input terminal IP and the output terminal OP on the transparent insulating substrate are connected to, for example, , Anisotropic conductive film A
It is electrically connected via CF2. In other words, the conductive particles in the anisotropic conductive film ACF are in a state of being crushed between the bump BUMP and the terminal patterns IP and OP, or are in a state of being fitted into the bump BUMP, thereby enabling electrical connection. . There is also a method in which a resin that is cured by light or ultraviolet light is used instead of the anisotropic conductive film, and the bump BUMP is directly electrically connected to the terminal pattern.

Further, in order to supply an external signal to the input wiring pattern Td connected to the input terminal IP, for example, a flexible substrate (FPC) is used as a peripheral circuit substrate.
The wiring pattern on the FPC (usually gold-plated on the copper pattern) is electrically connected to the input wiring pattern Td using the anisotropic conductive film ACF1.

[0011]

An input wiring portion T between the peripheral circuit board and a driving IC mounted on a transparent substrate is used.
Reducing the wiring resistance of d is an important issue for preventing a voltage drop of an input signal and an input power supply voltage at this portion and obtaining good display quality in a liquid crystal display device.

As a document describing a solution to such a problem, there is Japanese Patent Application Laid-Open No. 7-92479.

Although not a conventionally known technique, there is a prior application (Japanese Patent Application No. Hei 7-115583) by the same applicant.

In Japanese Patent Application Laid-Open No. Hei 7-92479, a plurality of scanning signal driving ICs are mounted on one substrate in a line, and extend in a column direction formed from a wiring layer on the substrate. Input signals and power are supplied from the outside by the flexible substrate FPC via the common wiring. At this time,
The arrangement pitch of the scanning signal driver ICs is made smaller than the width of the display area assigned to the scanning signal driving ICs. It is configured to be reduced.

However, in this configuration, since the elongated common wiring formed substantially in parallel with the edge of the substrate exists on the substrate, the wiring between the flexible substrate and the driving IC, and the driving IC
It is structurally difficult to reduce the wiring resistance difference between them to several tens of ohms or less. In particular, in a liquid crystal display device for multi-gradation display, a gradation reference voltage for gradation display is applied to each drain line driving IC.
Therefore, it is necessary to minimize the voltage drop at the input wiring portion because it is necessary to accurately supply the voltage from the outside.

Also, the prior application (Japanese Patent Application No. Hei 7-115583)
Then, the common wiring portion is formed by a low-resistance wiring of a flexible substrate, and the input wiring Td portion is formed of a transparent conductive film.
By using a low-resistance metal film, excellent low-resistance wiring can be realized. However, the configuration of the input terminal IP, which is the tip of the input wiring Td, was not described in detail, and measures for lowering the resistance were insufficient.

Therefore, an object of the present invention is to provide a configuration of an input terminal portion IP which is a tip portion of the input wiring Td portion.
An object of the present invention is to provide an input terminal structure with high connection reliability by reducing the wiring resistance to a necessary degree.

[0018]

In order to solve the above-mentioned problems, a liquid crystal display device according to the present invention is provided so as to be electrically connected to a pattern portion of a transparent conductive film which is a connection portion with a bump of a driving IC. A liquid crystal display device comprising a flip-chip type liquid crystal display element, characterized by having an input terminal portion in which a wiring of a low-resistance metal layer is partially protruded.

Further, in the liquid crystal display device of the present invention, the bumps of the driving IC divided into two or more regions to which the same signal is input and the pattern portions of the transparent conductive film which are the connection portions with the bumps are electrically connected. A flip-chip type liquid crystal display device, characterized by having an input terminal portion formed by projecting a wiring of a low-resistance metal layer in a gap between the region-divided bumps so as to be electrically connected. Liquid crystal display device.

Further, the liquid crystal display device of the present invention comprises a driving IC bump divided into two or more regions to which a power supply voltage and a gradation reference voltage are inputted, and a transparent conductive film which is a connection portion between the bumps. To be electrically connected to the pattern part of
A liquid crystal display device comprising a flip-chip type liquid crystal display element, characterized by having an input terminal portion in which a wiring of a low resistance metal layer is formed so as to protrude in a gap between the region-divided bumps.

Further, the wiring of the low resistance metal layer is composed of two layers, a metal layer forming a gate wiring and a metal layer forming source and drain wirings, and forms a gate wiring below the transparent conductive film. The metal layer is formed with an area larger than the connection portion with the bump, and the metal layer forming the source and drain wirings above the transparent conductive film is electrically connected to the pattern portion of the transparent conductive film which is the connection portion with the bump. This is a liquid crystal display device comprising a flip-chip type liquid crystal display element having an input terminal portion formed to partially protrude so as to be connected to the liquid crystal display device.

Further, the wiring of the low-resistance metal layer is formed simultaneously with a metal layer mainly composed of aluminum or chromium, which forms source and drain wirings. Liquid crystal display device.

Further, the wiring of the low resistance metal layer is formed simultaneously with a metal layer mainly composed of aluminum or chromium, which forms source and drain wirings, and a protective film is formed on the wiring of the low resistance metal layer. A liquid crystal display device comprising a flip-chip type liquid crystal display element characterized by being coated with a liquid crystal display device.

Further, the wiring of the low resistance metal layer is formed simultaneously with a metal layer mainly composed of aluminum, chromium or tantalum forming a gate wiring, and is formed under the transparent conductive film. A liquid crystal display device comprising a flip-chip type liquid crystal display element.

[0025]

According to the present invention, the wiring of the low resistance metal layer is formed so as to be partially protruded so as to be electrically connected to the pattern portion of the transparent conductive film which is the connection portion with the bump of the driving IC. By having the terminal portion, the size of the input terminal portion can be reduced and the resistance can be reduced.

Further, the bumps of the driving IC divided into two or more regions to which the same signal is inputted, and the pattern portions of the transparent conductive film which are the connection portions with the bumps are electrically connected to each other. By providing the input terminal portion in which the wiring of the low-resistance metal layer protrudes and is formed in the gap between the divided bumps, it is possible to reduce the input terminal portion and further reduce the resistance.

A driving IC bump divided into two or more regions to which a power supply voltage and a gradation reference voltage are inputted;
An input terminal portion in which a wiring of a low-resistance metal layer is formed so as to be electrically connected to a pattern portion of the transparent conductive film, which is a connection portion with the bump, in a gap between the region-divided bumps; With this arrangement, it is possible to reduce the size of the input terminal portion and sufficiently reduce the resistance without deteriorating the display quality of the multi-tone display liquid crystal display device.

Further, the low resistance metal layer wiring is composed of two layers, a metal layer forming a gate wiring and a metal layer forming source and drain wirings, and forms a gate wiring below the transparent conductive film. The metal layer is formed with an area larger than the connection portion with the bump, and the metal layer forming the source and drain wirings above the transparent conductive film is electrically connected to the pattern portion of the transparent conductive film which is the connection portion with the bump. , The input terminal portion is formed to be partially protruded so that the input terminal portion can be reduced in size and the resistance can be further reduced.

Further, since the wiring of the low-resistance metal layer is simultaneously formed of a metal layer mainly composed of aluminum or chromium which forms source and drain wirings, the size of the input terminal portion can be reduced and the resistance can be reduced. And simplification of the manufacturing process.

Further, the wiring of the low-resistance metal layer is formed simultaneously with a metal layer mainly composed of aluminum or chromium, which forms source and drain wirings, and a protective film is formed on the wiring of the low-resistance metal layer. By coating
It is possible to reduce the size of the input terminal, reduce the resistance, improve the reliability, and simplify the manufacturing process.

Further, the wiring of the low-resistance metal layer is formed simultaneously with a metal layer mainly composed of aluminum, chromium, or tantalum which forms a gate wiring, and is formed under the transparent conductive film. In addition, the size of the input terminal can be reduced, the resistance can be reduced, the reliability can be improved, and the manufacturing process can be simplified.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to embodiments.

FIG. 6 is a plan view showing a state in which a driving IC is mounted on a transparent insulating substrate SUB1 made of, for example, glass. FIG. 17 is a sectional view taken along the line AA.
Shown in In FIG. 6, one transparent insulating substrate SUB2
Is indicated by an alternate long and short dash line, is positioned above the transparent insulating substrate SUB1, and includes a liquid crystal L including an effective display portion (effective screen area) AR by a seal pattern SL (see FIG. 6).
C is enclosed. Electrode CO on transparent insulating substrate SUB1
M is a wiring that is electrically connected to the common electrode pattern on the transparent insulating substrate SUB2 via conductive beads, silver paste, or the like. The wiring DTM (or GTM) supplies an output signal from the driving IC to a wiring in the effective display unit AR. The input wiring Td supplies an input signal to the driving IC. The anisotropic conductive film ACF has an elongated shape common to a plurality of driving IC portions arranged in a line. The anisotropic conductive film ACF has an elongated shape common to an input wiring pattern portion to the plurality of driving ICs. What became A
Paste CF1 separately. Although the passivation films (protective films) PSV1 and PSV are also shown in FIG. 17, the wiring portions are covered as much as possible to prevent electrolytic corrosion, and the exposed portions are covered with the anisotropic conductive film ACF1.

Further, the periphery of the side surface of the driving IC is filled with a silicone resin or an epoxy resin SIL (see FIG. 17), and protection is multiplexed.

In this example, as shown in FIG. 6, on the liquid crystal display panel, an input wiring portion for supplying input signals to a plurality of driving ICs mounted on the gate side and the drain side is a substrate cut surface. Input wiring portion T in a direction substantially perpendicular to
Only d is formed. A common wiring portion for supplying a power supply voltage and a clock between the plurality of driving ICs is formed in the multilayer conductor layer portion FML of the flexible substrate, and the common wiring exists in a direction substantially parallel to the cut surface of the substrate. Therefore, the input wiring portion occupying the liquid crystal display panel is minimized, the outermost shape of the liquid crystal display module can be reduced, and the wiring resistance value of the common wiring portion can be reduced so that there is no problem in driving.

<< Liquid Crystal Display Element and Circuit Arranged on Its Outer Peripheral >> FIG. 21 shows an active matrix type TFT using a thin film transistor TFT as a switching element.
FIG. 2 is a block diagram showing a TFT liquid crystal display element of a liquid crystal display module and circuits arranged on an outer peripheral portion thereof. In this example,
Each of the drain drivers IC1 to ICM and the gate drivers IC1 to IC1 arranged only on one side of the liquid crystal display element, respectively.
As shown in FIG. 17, the ICN includes a drain-side lead line DTM and a gate-side lead line GTM formed on one transparent insulating substrate SUB1 of the liquid crystal display element and an anisotropic conductive film ACF2 or a silicone resin or epoxy. Chip-on-glass mounting (COG mounting) using resin SIL or the like. In this example, the SVGA specification 800
The present invention is applied to a liquid crystal display element having × 3 × 600 effective dots. For this reason, on the transparent insulating substrate of the liquid crystal display element, there are ten drain driver ICs with 240 outputs on the long side (M = 10) and six gate driver ICs with 101 outputs on the short side (N = 6). And COG mounting. From the number of pixels, it is sufficient for the gate driver to output a total of 600 outputs.
It has a configuration of 0 outputs × 4 and the lowermost 101 outputs. In addition, 100, 1
01 output can be used properly.

A drain driver section 103 is disposed above the liquid crystal display element, a gate driver section 104 is provided on the side face, and a controller section 10 is provided on the other side face.
1. The power supply unit 102 is provided. Controller 1
01, a power supply unit 102, a drain driver unit 103,
The gate driver unit 104 is provided with an electric connection unit J
They are interconnected by N1 and N3.

In this example, the SVGA panel is 800 ×
10.4-inch screen size TFT with 3 x 600 dots
We designed a liquid crystal display module. Therefore, red (R),
The size of each of the green (G) and blue (B) dots is 264 μm
(Gate line pitch) × 88 μm (Drain line pitch)
And one pixel is a combination of three dots of red (R), green (G), and blue (B), and has a size of 264 μm square. Therefore, the drain line lead-out wiring DTM is set to 80
If the number is 0 × 3, the lead line pitch will be 80 μm or less, which is below the connection pitch limit of currently available tape carrier package (TCP) mounting. CO
In the G mounting, although it depends on the material of the anisotropic conductive film to be used, the pitch of the bump BUMP of the driving IC chip is about 70 μm and the crossing area with the underlying wiring is about 40 μm.
The μm square can be said to be the minimum value currently available. For this reason, in this example, the drain driver ICs are arranged in one line on one long side of the liquid crystal panel, the drain line is drawn out to the long side, and the pitch of the drain line drawing wiring DTM is 88.
μm. Therefore, the bump B of the driving IC chip
The UMP (see FIG. 17) pitch can be designed to be about 70 μm and the intersection area with the underlying wiring can be designed to be about 40 μm square, so that connection with the underlying wiring can be achieved with higher reliability. Since the gate line pitch is 264 μm, which is sufficiently large, the gate line lead GTM is drawn on one short side. However, when the definition is further increased, it is possible to alternately draw out the gate line lead lines GTM to the two opposing short sides, similarly to the drain line side. However, in the method of alternately extracting the drain line or the gate line, the connection between the extraction wiring DTM or GTM and the output side BUMP of the driving IC becomes easy, but the peripheral circuit substrate is connected to the liquid crystal panel PN.
L needs to be arranged on the outer periphery of two opposing sides of L, and therefore, there is a problem that the outer dimensions are larger than in the case of single-side drawing.

When the number of display colors increases, the number of data lines of display data increases, and the outermost shape of the information processing apparatus increases. For this reason, in this example, the conventional problem was solved by using a multilayer flexible substrate.

The driving IC employed in this example has a rough appearance as shown in FIG. 6. However, in order to make the module outer shape as small as possible, the driving IC has a very elongated shape. Side dimensions are about 11-17mm,
The short side dimension is about 1.0 to 2.5 mm, and the long side dimension is about 11 to 20 mm and the short side dimension is about 1.0 to 2.0 mm for the drain side driving IC. Further, in this example, the gate output wiring pattern GTM between the effective display section AR and the output-side bump BUMP section of the driving IC extends in three directions of the long side and the short side of the driving IC. ing. On the other hand, the drain output wiring pattern DTM extends from one direction of the long side direction of the driving IC.

For example, in this embodiment, the gate driving IC
Then, out of 101 outputs, 21 wires are output from the two short sides and about 80 are output from the one long side. In the drive IC on the drain side, the drive IC is designed to be slender, and output wiring is provided only in the long side direction, and 240 outputs are output from one long side.

FIG. 23 shows the common voltage applied to the common electrode, the drain voltage applied to the drain, the level of the gate voltage applied to the gate electrode, and the waveform thereof. Note that the drain waveform indicates a drain waveform when displaying black.

For example, the gate-on level waveform (DC) and the gate-off level waveform change between -9 to -14 volts, and the gate turns on at 10 volts. The level of the drain waveform (during black display) and the waveform of the common voltage Vcom change between 0 and 3 volts. For example, in order to change the drain waveform of the black level every horizontal period (1H), logical inversion is performed bit by bit by a logic processing circuit and input to the drain driver. The gate off-level waveform is V
It operates with substantially the same amplitude and the same phase as the com waveform.

FIG. 22 is a diagram showing a flow of display data and a clock signal for the gate driver 104 and the drain driver 103 in the TFT liquid crystal display module of this embodiment.

The display control device 101 receives a control signal (clock, display timing signal, synchronization signal) from the main computer, and as a control signal to the drain driver 103, a clock D1 (CL1) and a shift clock D2.
(CL2) and display data are generated, and at the same time, a frame start instruction signal FLM, a clock G (CL3) and display data are generated as control signals to the gate driver 104.

The carry output at the preceding stage of the drain driver 103 is directly used as the drain driver 103 at the next stage.
Is input to the carry input.

<< Gradation Voltage Generation Method >> Next, a conventional typical gradation voltage generation method and an embodiment of the present invention will be described.
This will be described with reference to FIG.

As shown in FIG. 22, the display control device 101
Receives display data from the computer body, for example, a total of 18 bits of 6 bits for each color and a display control signal, and drives the drain driver 103 and the gate driver 104 based on this signal.

As shown in FIG. 14, the drain driver 103 applies, for example, 9-level gradation reference voltages (V0 to V8) generated from a power supply circuit inside the liquid crystal display module.
A gradation voltage for 64 gradations is supplied from the connection terminal 10 with the flexible substrate and is generated via the input terminal Td on the transparent insulating substrate SUB1. That is, each of the eight gradation voltages (between Vi and Vi + 1) is further divided into eight by the series resistance dividing circuit Rseg in the driver to generate gradation voltages for 64 gradations. Next, the gradation voltage corresponding to the display data is set to 6
Selection is made by a selection circuit composed of 4 × b MOS transistors, and output to drain signal lines 1 to b. Similarly, the power supply voltage 3.3 volts supplied to the driver and the ground potential
The driving IC is supplied from the connection terminal 10 with the flexible substrate, and is supplied through the input terminal Td on the transparent insulating substrate SUB1.
To the connection terminal 11 with the input bump BUMP.

An object of the present invention is to transmit the above-mentioned gradation reference voltage and power supply voltage from a voltage generation circuit to a series resistance dividing circuit Rseg in a driver accurately without voltage change. Specifically, the resistance variation and the absolute value of the total value Rt of the resistance value Radd of the input wiring Td, the connection resistance value RA with the bump, and the connection resistance value RA with the flexible substrate are designed to be as small as possible. To minimize the voltage drop and the voltage variation at the terminal. The target is 15 Ω or less in resistance Rt. Therefore,
It is possible to generate a gradation voltage for 64 gradations faithful to a design value determined by the bus line resistance Rbus and the series resistance dividing circuit Rseg inside the driving IC. In this example, a common wiring (reference power supply line) for supplying a power supply voltage and a clock to a plurality of drivers has a low resistance wiring such as a copper pattern on the peripheral substrate side in order to reduce the wiring resistance to a negligible level. Formed.

FIG. 15 shows an applied voltage-transmittance characteristic of a typical liquid crystal display device.

Among the gradation voltages for the 64 gradations, in the halftone display in which the slope of the applied voltage-transmittance characteristic is the steepest, it is observed as luminance unevenness in the gradation voltage fluctuation display. For example, assuming a working voltage range of about 3 volts,
When a gradation voltage for 256 gradations is required, each gradation difference is
The output error is about 10 millivolts, and a luminance difference occurs due to such an output error.

<< Method of Manufacturing Transparent Insulating Substrate SUB1 >> Next, the first transparent insulating substrate SUB of the liquid crystal display device described above.
The manufacturing method on one side will be described with reference to FIGS. In the figure, the characters in the center are the abbreviations of the process names, the left side shows the pixel portion, and the right side shows the flow of processing as viewed in the cross-sectional shape near the gate terminal. Except for the steps B and D, the steps A to G are classified according to each photo (photo) processing, and the processing after the photo processing is completed in all the sectional views of each step, and the photoresist is removed. Is shown. In this description, the photo (photo) processing refers to a series of operations from application of a photoresist, through selective exposure using a mask, to development thereof.
Avoid repeated explanations. A description will be given below according to the divided steps.

Step A, FIG. 18 After a silicon oxide film SIO is provided on both surfaces of a first transparent insulating substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. Note that this SIO film is formed in order to alleviate the surface irregularities of the transparent insulating substrate SUB1.
This is a step that can be omitted. Al-T with a thickness of 2800 °
a, a first conductive film g1 made of Al—Ti—Ta, Al—Pd, or the like is provided by sputtering. After the photo-treatment, the first conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step B, FIG. 18 After drawing the resist directly (after forming the anodic oxidation pattern described above),
3% tartaric acid with ammonia PH 6.25 ± 0.05
The substrate SUB1 is immersed in an anodizing solution composed of a solution obtained by diluting the solution adjusted to 1: 9 with an ethylene glycol solution,
The formation current density is adjusted to 0.5 mA / cm 2 (constant current formation). Next, anodic oxidation (anodization) is performed until the formation voltage 125 V necessary for obtaining a predetermined Al2O3 film thickness is reached. Thereafter, it is desirable to maintain this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al2O3 film. As a result, the conductive film g1 is anodized, and the film thickness is 1800 on the scanning signal lines (gate lines) GL and on the side surfaces in a self-aligned manner.
The anodic oxide film AOF of Å is formed and the thin film transistor T
It becomes a part of the gate insulating film of the FT.

Step C, FIG. 18 A transparent conductive film (Indium-Tin) having a thickness of 1400 °
-Oxide Nesa film) A conductive film d1 made of ITO is provided by sputtering. After the photo-processing, the conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the gate terminal GTM, the uppermost layer of the drain terminal DTM, and the transparent pixel electrode ITO1.

Step D, FIG. 19 An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to provide a 2000-nm thick Si nitride film, and a silane gas and a hydrogen gas are introduced into the plasma CVD apparatus to form a film. After providing a 2000 ° i-type amorphous Si film, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus to form a 300 ° -thick N + type amorphous Si film d0. This film formation is performed continuously by changing the reaction chamber in the same CVD apparatus.

Step E, FIG. 19 After photo processing, SF6, BC
The N + type amorphous Si film d0 and the i type amorphous S
The i-film AS is etched. Subsequently, the Si nitride film GI is etched using SF6. Of course, the N + type amorphous Si film d0, the i type amorphous Si film AS, and the Si nitride film GI may be successively etched with SF6 gas.

The feature of the manufacturing process of the present embodiment is that the three-layer CVD film is continuously etched with a gas containing SF6 as a main component. That is, the etching rate with respect to the SF6 gas increases in the order of the N + type amorphous Si film d0, the i type amorphous Si film AS, and the Si nitride nitride film GI. Therefore, when the etching of the N + type amorphous Si film d0 is completed and the etching of the i type amorphous Si film AS starts, the upper N + type
The type amorphous Si film d0 is side-etched, and as a result, the i-type amorphous Si film AS is processed into a taper of about 70 degrees. When the etching of the i-type amorphous Si film AS is completed and the etching of the Si nitride film GI starts, the upper N + type amorphous Si film d0 and the i-type amorphous Si film AS are side-etched in this order. As a result, the i-type amorphous Si film AS is about 50 degrees,
The silicon nitride film GI is tapered to 20 degrees. Due to the tapered shape, the probability of disconnection is significantly reduced even when the source electrode SD1 is formed on the upper portion. The taper angle of the N + type amorphous Si film d0 is close to 90 degrees, but since the thickness is as thin as 300 °, the probability of disconnection at this step is very small. Therefore, the plane patterns of the N + type amorphous Si film d0, the i type amorphous Si film AS, and the Si nitride film GI are not strictly the same pattern, and the cross section has a forward tapered shape. Si film d0, i-type amorphous Si film A
The pattern becomes larger in the order of S and the Si nitride film GI.

Step F, FIG. 20 A second conductive film d2 made of Cr having a thickness of 600 ° is provided by sputtering, and a second conductive film d2 having a thickness of 4000 ° is further formed.
A third conductive film d3 made of Pd, Al-Si, Al-Ta, Al-Ti-Ta, or the like is provided by sputtering.
After the photo-treatment, the third conductive film d3 is etched with the same liquid as in step A, and the second conductive film d2 is etched with a ceric ammonium nitrate solution to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. I do.

Here, in this embodiment, as shown in step E, the N + type amorphous Si film d0, the i type amorphous Si film AS,
Since the Si nitride film GI has a forward taper, in a liquid crystal display device having a large tolerance of the resistance of the video signal line DL, it is possible to form only the second conductive film d2.

Next, SF6,
By introducing BCl3 and etching the N + type amorphous Si film d0, the N + type semiconductor layer d0 between the source and the drain is selectively removed.

Step G, FIG. 20 An ammonia gas, a silane gas and a nitrogen gas are introduced into the plasma CVD apparatus to form a 0.6 μm-thick Si nitride film. After photo processing, SF6 is used as a dry etching gas.
The protective film PSV1 is etched by using
To form As the protective film, not only a SiN film formed by CVD but also a film using an organic material can be used.

<< Electrostatic Countermeasures Using Short-Circuit Wiring SHc Under Driving IC >> FIG. 7 is a plan view showing the vicinity of the portion where the driving IC is mounted on the transparent insulating substrate SUB1 and the vicinity of the cutting line CT1 of the substrate. is there.

As shown in FIG. 7, in this example, both the input and output of the IC for driving a drain come out from one side of the IC chip. The drain lines DL connected to the respective wiring patterns DTM are alternately provided in alternate directions. One of the drain lines DL extends beyond one cutting line CT1 (not shown) and extends in the y direction in the drawing. The short-circuit wiring SHd is connected to the short-circuit wiring SHd and the other is short-circuited.
And the input line Td (to the drain line driving IC) extends beyond the cutting line CT1 and is short-circuited by being connected to the drain short-circuiting line SHd. In other words, every other drain line DL is electrically connected to the short-circuit wiring SHc and short-circuited for each driving IC, and the short-circuit wiring SHc is connected to two input wirings Td to the drain-line driving IC. , The drain short-circuit wiring S via the two input wirings Td.
Hd. Thus, each drain line DL
And the static electricity generated in the input wiring Td is dispersed through the short-circuit wiring SHc and the drain short-circuit wiring SHd. After the completion of the liquid crystal display element, the operation is of course required unless the short circuit is released.
Are formed on the surface of the transparent insulating substrate SUB1 outside the cutting line CT1, which is cut and discarded in a later step. The short-circuit release of the input terminal IP at the tip end of the input wiring Td directly connected to the drain short-circuit wiring SHd is performed by cutting the substrate SUB1 along the cutting line CT1. On the other hand, the short-circuit wiring SH
c and the drain short-circuit wiring SHd via the input wiring Td
Release of the short circuit of the drain line DL connected to the
Due to the presence of Hc, the cutting of the substrate SUB1 at the cutting line CT1 is not performed. As shown in FIGS. 7 and 8, the short-circuit wiring SHc and every other drain terminal DTM and the input wiring Td are connected to each other before the drive IC is mounted on the substrate SUB1 as shown in FIGS. Cutting is performed by laser or photo etching at the cutting line C1. Therefore, as shown in FIGS. 7 and 8, the passivation film PAS1 (that is, the protection film PSV1) is not formed in the region (the IC mounting region) where the cutting line C1 exists due to this cutting. In this example, the short circuit can be easily released by one cut at the cutting line C1.

Since the wiring DTM at the position of the cutting line C1 is formed of the transparent conductive film ITO with little contamination even in laser cutting, the contamination can be suppressed. Also,
This cutting may be performed by photoetching.

In this example, unlike the drain line DL, the short-circuit wiring SH for each IC is provided on the gate line GL side.
c is not provided. The reason is that the gate line driving ICs are arranged only on one side, and the gate lines GL can be short-circuited to each other by the gate short-circuit wiring SHg on the opposite side (the side on which the gate line driving ICs are not arranged). Since the pixel pitch on the gate side is about three times larger than that on the drain side, the probability of short-circuit failure between adjacent gate lines is small.
This is because short circuit inspection is unnecessary. However, when the gate line driving IC is arranged on both sides, or when the gate short-circuit wiring SH
g, the gate line GL is connected to the short-circuit wiring SHc.
To the gate short-circuit wiring SHg. Further, it is needless to say that the structure having the short-circuit wiring SHc can be applied to the case where the output and the input are also output from one side of the IC chip on the gate scanning drive IC side.

FIG. 8 is an enlarged detailed view of a main part (a drain input side corner) of FIG. On the substrate SUB1, in addition to the input terminal IP and the short-circuit wiring SHc, the driving I
7 shows a state in which an alignment mark ALD with C and a displacement detection pattern BAR of the driving IC after mounting are provided.

<< Input Wiring Td to Driving IC >> FIG.
FIG. 3 is an enlarged plan view of an input wiring Td to a driving IC according to the present invention.

As shown in FIG. 1, the input wiring Td to the driving IC is formed on the transparent insulating substrate SUB1 from the lower layer in the same step as the gate electrode and the gate line.
A first conductive film g1 made of a low-resistance metal such as Al-Ti-Ta or Al-Pd; a conductive film d1 made of an ITO (indium tin oxide) film formed in the same process as the transparent pixel electrode of the display portion; A second conductive film d2 formed of the same process as the source / drain electrodes and made of a low-resistance metal such as Cr, Al-Pd, Al-Si, Al-
A third conductive film d3 made of a low-resistance metal such as Ta, Al-Ti-Ta, etc .;
A protective film (passivation film) PSV1 made of N or the like is provided.

In FIG. 1, the position where the driving IC is mounted is indicated by a broken line with the reference numeral IC. The code BUMP
Denotes a bump connection portion to which the bump BUMP of the driving IC is bonded. Also, a signal from the outside to the driving IC,
The position (one end) where the flexible substrate FPC for supplying the power supply voltage is connected and mounted is indicated by a broken line with the reference numeral FPC. The portion of the input wiring Td that is connected to the output terminal of the flexible substrate is a portion on the left side (opposite to the display unit) of the broken line FPC in FIG.

In the portion of the input wiring Td connected to the output terminal of the flexible substrate, the second conductive film d2 and the third conductive film d3 are formed on one side of the input wiring Td as shown in FIG. . In addition, the protection film PSV1 is also connected to the input wiring T
Along the second and third conductive films d2 and d3 formed on one side of d, the second and third conductive films are formed slightly larger on one side of the input wiring Td. That is, in the input wiring Td, the portion other than the protective film PSV1 exposed on the surface is the transparent conductive film d1.
Is exposed over a large area, and the exposed transparent conductive film d
1 is an inspection terminal (pad), and the exposed transparent conductive film d1 is directly connected to the output terminal of the flexible substrate.

The first conductive film g1 and the second conductive film d2 are connected via through holes TH1 and TH2.

In FIG. 1, reference symbol P denotes a terminal (input wiring Td) pitch (approximately 0.4 to 1.3 mm), and reference symbol G denotes a terminal gap (interval) (approximately 0.2 to 1.1 mm). .

Here, a flexible substrate and a driving IC
Is connected to an input wiring Td made of a low-resistance metal.
The transparent conductive film d is configured to include the conductive film g1, the second and third conductive films d2 and d3, and has a high contact resistance with the low-resistance metal.
1, the first conductive film g1 and the second conductive film d2 are connected via the through holes TH1 and TH2, so that the resistance of the input wiring Tg can be reduced, and the resistance between the flexible substrate and the driving IC can be reduced. Can be realized.

Further, the second and third conductive films d formed on one side of the input wiring Td for lowering resistance, in which electrolytic corrosion is likely to proceed.
The top of 2, d3 is covered with a protective film PSV1 to prevent electrolytic corrosion, and the portion connected to the terminal of the flexible substrate is made of a transparent conductive film d1 which has high stability, is less likely to be contaminated and oxidized, and is less likely to cause electrolytic corrosion. Since it is configured so as to be exposed, the corrosion resistance of the input wiring Td connecting the flexible substrate and the driving IC can be improved. As a result, the reliability of the product can be improved.

Further, the second and third conductive films d 2, in the portion of the input wiring Td connected to the output terminal of the flexible substrate,
Since d3 is formed on one side of the input wiring Td, and the other part has a large area and the transparent conductive film d1 is exposed, as described in the section <Production Flow>, after mounting the driving IC, Before mounting the flexible substrate, the inspection probe is applied to the exposed portion TEST of the transparent conductive film d1, and a lighting inspection is performed to determine the quality of the driving IC.

As described above, by adopting the above-described terminal structure, the resistance from the connection portion of the input terminal Td to the flexible substrate to the input terminal IP is, for example, 300 μm in wiring width.
m, the wiring distance is 2 mm, and the thickness of the wiring layer d3 is about 4
000 °, the resistivity of Al—Pd is 0.1 Ω /
□, if the thickness of the wiring layer g1 is about 2800 °, A
In 1-Ta-Ti, since the resistivity is about 0.5 Ω / □, the resistance becomes a parallel connection resistance of 0.67 Ω and 3.3 Ω, respectively, and further, the through-holes of TH1 and TH2 between the transparent conductive film d1. In consideration of the Hall resistance, the resistance is several Ω in total.

FIG. 16 is a perspective view showing a method for folding and mounting a bendable multilayer flexible substrate FPC on a liquid crystal display element.

The flexible substrate FPC has a multi-layer structure and can be bent. As shown in FIG. 16, on the edge of the lower transparent insulating substrate of the liquid crystal display element, an anisotropic conductive film (see ACF1 in FIG. 17) is interposed. Electrically and mechanically, and the flexible board FPC is mounted by being bent in the direction of the arrow.

An anisotropic conductive film (ACF1) is stuck on the connection portion of the lower transparent insulating substrate SUB1, and the hole FHL of the flexible substrate FPC is temporarily fixed to the positioning pin of the jig.
The opening hole and the hole of the flexible printed circuit board FPC are aligned to make a rough alignment. Substrate SUB1 to improve alignment accuracy
On the side, a square filling pattern (see ALC in FIGS. 6 and 7) is arranged. This pattern (ALC)
The flexible substrate is preliminarily thermocompression-bonded with a heat tool while adjusting the position so as to fit in the square-shaped alignment patterns ALMG and ALMD on the flexible substrate FPC side.
After confirming that there is no misalignment, final thermocompression bonding is performed to fix the flexible substrate FPC to the substrate SUB1.

The reason for using the anisotropic conductive film ACF1 is as follows.
It is necessary to wire about 45 input signals and power supply voltages to the driving IC, and the pitch P between the input wires Td is about 400 μm.
Therefore, soldering to the transparent insulating substrate SUB1 was difficult, and reliable electrical connection was difficult. Therefore, according to the present invention, even if the number of pixels and the number of display colors are increased and the pitch between wirings is narrowed, the electrical connection with the flexible substrate can be made with high reliability.

FIGS. 24 (a) and 24 (b) are each an example of a sectional view of a main part of a liquid crystal display module.

A liquid crystal display element with a driving circuit, which is a combination of a flip-chip type and a multilayer flexible substrate, has a shield case SHD, an insulating spacer SPC, a rubber cushion GC, a deflecting plate POL, a prism sheet PRS, a diffusion sheet SPS, and a light guide plate GLB. , Reflection sheet RFS, lower mold case MCA, fluorescent tube LP, lamp cable L
As shown in the figure, the PC and the like are stacked in a vertical arrangement relationship, and the liquid crystal display module is assembled.

<< Structure of Input Terminal IP >> FIGS. 1 to 4 show structural examples of the input terminal IP of the present invention.

As described above, the resistance from the connection portion of the input wiring Td to the flexible substrate to the input terminal IP is a resistance of several Ω. On the other hand, the input terminal IP section also needs to have a resistance value of several Ω.

FIGS. 2A, 2B and 2C are enlarged plan views showing the relative positions of the input terminals IP and the bumps of the driving IC according to the embodiment of the present invention. In the structure of this example, since the bump is not divided, the single bump SB is used for convenience.
It is called P structure.

Assuming that the input terminals IP have the same size, the protruding portions JUT of the wiring layers d2 and d3 formed around the bumps correspond to one side of the bump in FIG.
It can be seen that the connection area between the transparent conductive film and the bump decreases as (b) the two sides of the bump and FIG. 2 (c) the three sides of the bump. When the input terminal IP has a width of about 100 μm and a connection area of 70 μm square or more is required for highly reliable connection, the wiring width of the protruding portion JUT of the wiring layers d2 and d3 is about 10 to 20 μm. (A) The structure on one side of the bump is optimal. In addition, this structure is gentle with respect to the displacement of the bump in the length direction of the input terminal IP, and does not destroy the protruding portion JUT. However, if there is a margin in the width of the input terminal IP, the wiring resistance R
2 (b) where t can be reduced, two sides of the bump, FIG. 2 (c)
The configuration on the three sides of the bump is advantageous. In this example, the protruding portion JUT uses the wiring layers d2 and d3. However, even if the wiring layer g1 is used in a similar pattern, low-resistance wiring can be achieved. Note that the wiring layers d2, d3
In the case where is used, furthermore, in order to prevent the damage of the protruding pattern and to improve the reliability against electrolytic corrosion, the wiring mainly made of aluminum is not directly exposed to the outside air, so that the wiring is covered with a protective film PSV1.

FIGS. 3 (a), 3 (b), 3 (c) and 3 (d) show an input terminal IP and a drive I which show another embodiment of the present invention.
It is an enlarged plan view which shows the relative position with respect to the divided bump of C. The structure of this example is referred to as a double bump WBP structure for convenience because the bump is divided into a plurality of parts.

Assuming that the input terminals IP have the same size, the protruding portions JUT of the wiring layers d2 and d3 are
(A) The gap at the center of the divided bump, FIG. 3 (b) The gap at the center of the divided bump and one side of the periphery, FIG. 3 (c)
The gap at the center of the divided bump and the two sides around it, FIG.
(D) the center gap between the divided bumps and the three sides of the periphery,
It can be seen that the connection area between the transparent conductive film and the bumps decreases as becomes smaller. Input terminal IP is about 100μm
If the total connection area is required to be 70 μm square or more in width, the wiring width of the protruding portion JUT of the wiring layers d2 and d3 is about 10 to 2
Since it is 0 μm, the structure arranged in the center gap between the divided bumps in FIG. Also, this structure
The position of the bump in the length direction of the input terminal IP is loose and the projecting portion JUT is not broken. However,
When there is a margin in the width of the input terminal IP, the wiring resistance value Rt can be further reduced.
(C) The configuration on the three sides of the bump is advantageous. In this example, the protruding portion JUT uses the wiring layers d2 and d3.
Even if the wiring layer g1 is used in a similar pattern, low-resistance wiring can be achieved. Note that the wiring layer d is provided on the protruding portion JUT.
In the case of using d2 and d3, the wiring mainly composed of aluminum is not directly exposed to the outside air in order to further prevent the damage of the protruding pattern and to improve the reliability against electric erosion, so that the wiring is covered with a protective film PSV1. ing.

FIG. 10 schematically shows an example of a conventional typical input terminal structure and a resistance value up to a bump. Further, FIG.
1, FIG. 12 schematically shows the input terminal structures SBP and WBP of the present invention and the resistance values up to the bumps.

In the input terminal portion IP, a bump B indicated by a dotted line
Assuming that the bump BUMP width is 70 μm and the distance between the wiring layers d2 and d3 and the bump BUMP is 40 μm as the resistance value R1 up to the connection point with the UMP. Then, resistivity 2
If it is about 0Ω / □, it becomes about 11.4Ω. Further, the resistance values R2, R3, and R4 are the resistances of the remaining three sides around the bump, but all of them are larger than the resistance value R1. Therefore, the connection portion with the bump BUMP and the wiring layer d
2, the total parallel resistance with the end of d3 is substantially equal to the resistance R1
It was found to be as large as about 10Ω. Further, it was found that the resistance value R1 changed to 5 to 17Ω when the distance varied, for example, from 20 to 60 μm for each bump due to the positional deviation of the connection portion with the bump BUMP. Therefore, in the conventional input terminal structure, specifically, the variation of the total value Rt of the resistance value Radd of the input wiring Td, the connection resistance value RA with the bump, and the connection resistance value RA with the flexible substrate is minimized. It was difficult to reduce the absolute value to 15Ω or less as a target.

On the other hand, in the single bump SBP structure shown in FIG. 2, since the protruding portion JUT is formed around the bump BUMP, the resistor RD shown in FIG. 11 is formed in parallel with the resistor R1. , A lower resistance wiring can be realized. For example, assuming that the width of the resistor RD on the bump side is 70 μm and the distance between the wiring layers d2 and d3 and the bump BUMP is 40 μm and the resistivity of the wiring layer d1 is about 20Ω / □, the resistance value RD is about 11. 4Ω. That is, the parallel resistance is mainly composed of the resistances R1 and RD, and can be reduced by half compared to the prior art, and is about 6Ω or less. Further, it goes without saying that the input terminal resistance is reduced by surrounding the periphery of the bump more with the protruding portion JUT.

Further, the double bump W shown in FIG.
In the BP structure, since the protrusion JUT is formed at the center of the divided bump BUMP, the resistance R shown in FIG.
D are formed on both sides of the central protruding portion JUT, and these resistors RD are formed in parallel with the resistor R1,
As compared with FIG. 11, lower resistance wiring can be realized. For example, a width of the resistor RD on the bump side of 70 μm, a wiring layer d2,
Assuming that the distance between d3 and the bump BUMP is 40 μm and the resistivity of the wiring layer d1 is about 20Ω / □, the resistance value RD
Is about 11.4Ω. That is, the parallel resistance becomes a parallel resistance of the resistances R1 / 2 and RD / 2 for each of the divided bumps, which can be reduced to about 1/4 as compared with the conventional one, and about 3
Ω or less. Further, it goes without saying that the input terminal resistance is reduced by surrounding the periphery of the bump more with the protruding portion JUT.

FIG. 5 is a diagram showing the resistance between terminals and a measuring method when a wiring of a low resistance metal layer is formed below or above the transparent conductive film.

As shown in FIG. 5A, the measurement terminal pattern has a multilayer structure including a transparent conductive film ITO.
The connection area between the lower layer 11 and the upper layer 12 is approximately 200 μm in width.
m and length 600 μm. In addition, approximately 100μ in length
With a connection length of m, the flexible substrate FPC is electrically connected to the upper layer 12 via the anisotropic conductive film ACF, and the resistance Ro is further connected.
A voltage of about 1 volt was applied via n. The current value is
An inspection probe needle was applied to the end of the measurement terminal pattern to measure, and a resistance value was calculated.

FIG. 5B shows the measurement results.

In a single layer of the transparent conductive film ITO, the resistance value between the terminals is about 40 to 100Ω, and the resistance value is high and the variation is large. It is considered that this is because the specific resistance is as high as about 20 Ω / □ and the influence of the variation in the film thickness is large. Therefore, it can be seen that a single-layer structure of the transparent conductive film ITO is not appropriate for the input terminal.

On the other hand, in the structure in which the low-resistance metal layer is wired below the transparent conductive film ITO, the connection resistance differs depending on the material of the lower layer 11, and thus the resistance value between the terminals is different. That is, in the ITO / Al structure in which the upper layer 12 is formed of the transparent conductive film ITO and the lower layer 11 is formed of a film mainly composed of aluminum Al, the resistance value between the terminals is reduced only by about 10Ω, and the connection resistance between the two layers is reduced. However, it turns out that it is quite high. This is probably because a thin oxide film was formed on the surface of the film mainly composed of aluminum Al. In the structure ITO / Cr or ITO / Ta in which a film mainly composed of chromium Cr or tantalum Ta is formed in the lower layer 11, the resistance between the terminals is reduced by about half, and the connection resistance between the two layers is reduced.
It turns out that it is quite low.

In the Al / Cr / ITO structure in which the upper layer 12 is made of two layers of aluminum Al and chromium Cr and the lower layer 11 is formed with a transparent conductive film ITO, it can be seen that there is almost no connection resistance between the two layers.

As described above, the metal layer forming the gate wiring is used as the wiring of the low-resistance metal layer, and the input terminal IP formed by projecting the wiring of the low-resistance metal layer below the transparent conductive film. It can be seen that the structure of (1) can reduce the resistance of the input terminal portion as compared with the case of a single-layer transparent conductive film.

FIG. 4 shows another embodiment of the present invention, in which a metal layer forming a gate wiring is used as a wiring of a low resistance metal layer.

In FIG. 4A, at the input terminal portion IP, a protrusion J made of a metal layer g1 forming a gate wiring is provided.
UT completely covers the connection part BUMP with the bump, and
The area is smaller than that of the transparent conductive film d1. Therefore, even a relatively soft material or a material which is likely to cause electrolytic corrosion as a gate wiring material is covered with the upper layer of the relatively hard and reliable transparent conductive film d1, so that connection reliability is improved and low resistance is obtained. Can be realized.

4 (b) and 4 (c), FIG.
In the input terminal IP structure shown in FIG. 3A and FIG. 3A, a protruding portion JUT is further formed on a metal layer g1 forming a gate wiring.
Is formed. Therefore, FIG.
In addition, lower resistance can be realized as compared with FIG.

In this example, a material mainly composed of aluminum Al is used as the gate wiring material. However, even when a material mainly composed of chromium Cr or tantalum Ta is used, the effect of lowering the resistance can be further reduced. This is as shown in FIG.

FIG. 13 is a schematic cross-sectional view of the double-bump WBP structure shown in FIG. 1 and FIG. 3A along the line GG after mounting the driving IC.

In this example, the bump BUMP of the driving IC is used.
Was formed from a gold Au material. As the anisotropic conductive film ACF2, a commercially available material is used. As the particle material, approximately 5 μm diameter plastic plated with nickel Ni and gold Au and having a particle density of 10,000 particles / mm2 or more is used. At the time of pressure bonding, the driving IC side was heated to 150 ° C. or higher and pressurized to make electrical connection with the transparent conductive film d1 on the transparent insulating substrate. As a result, the resistance value RA between the bump BUMP and the transparent conductive film d1 was several Ω when the total connection area was 40 μm square or more.

Therefore, according to the present invention, the resistance value of this portion can be reduced to half or less of the conventional value, and the structure of the input terminal IP suitable for high-density bump mounting with high reliability can be obtained.

FIG. 9 shows an example in which the input terminal structure of the present invention is applied to each input signal of the drain driving IC of the actual liquid crystal display module. The enlarged plan view is shown in FIG.
Shown in

The numbers 1 and 45 of the input wiring Td are wirings for supplying a voltage to the common electrode COM formed on the transparent insulating substrate SUB2 side. Also, numbers 2 and 44 are
It is connected to the short wiring SHc and has no connection to the input bump. The numbers 4 to 10, 15, 16, 29 to 31, and 37 to 42 are the display data signals D00 to D05, D10
~ D15, D20 ~ D25, 6 bits for each color, total 1
Approximately 260,000 colors are displayed by 8 bits. Since these display data are high impedance inputs, the adverse effect of the resistance value of the input terminal is not so large. Therefore, the input terminal structure is a single bump SBP structure shown in FIG. Also, a scanning direction change signal (LD24
0-1) wiring number 11, clock capture control (R
ESERVED) wiring number 14, clock input wiring number 17 (DCLK), operation clamp wiring number 32
(CLAMP), data inversion signal (DATA-INV)
Input wiring number 35, carry signal input wiring number 43
(EiO1) also has a high impedance input, so the adverse effect of the resistance value of the input terminal is not so large. Therefore, the input terminal structure is a single bump SBP structure.

On the other hand, since the input impedance of the gray scale reference voltage and the power supply voltage is low, the adverse effect of the resistance value Radd of the input wiring becomes large as described in the section <Method of generating gray scale voltage>. For this reason, the input terminal structure is a double bump WBP structure.

That is, the 9-level gradation reference voltages V0 to V8
Are the input wiring numbers 12, 13, 20, 21 to 25, 2
6, 33 and 34, and the input terminal structure is a double bump WBP structure shown in FIG. Further, 3.3 volt supply input wiring number 1 for digital power supply (VDDD) and analog power supply (VDDA)
8 and 19 also have a double bump WBP structure. Further, the input wiring numbers 27 and 28 for the analog ground (AGND) and the digital ground (DGND) also have the double bump WBP structure.

As described above, by adopting an optimal input terminal configuration corresponding to each input signal, no luminance unevenness was observed in any halftone display in the liquid crystal display device.

<< Information Equipment Mounted with Liquid Crystal Display Module MDL >> FIG. 25 is a perspective view of a notebook personal computer or a word processor apparatus mounted with the liquid crystal display module MDL.

COG of drive IC on liquid crystal panel PNL
By employing bending and mounting on the multilayer flexible substrate as a mounting and peripheral circuit for the drain and gate driver on the outer peripheral portion, the outer size can be significantly reduced as compared with the conventional case. In this example, since the drain driver peripheral circuit mounted on one side can be arranged above the display section above the hinge of the information device, compact mounting is possible.

In the figure, a signal from an information device first goes to a display control integrated circuit element (TCON) from a connector located substantially at the center of the left interface board PCB. And flows to the drain driver peripheral circuit on the multilayer flexible substrate. As described above, by using the flip-chip method and the multilayer flexible substrate, the restrictions on the outer shape of the information device in the lateral width can be eliminated, and a small-sized information device with low power consumption can be provided.

Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the scope of the present invention. is there.

[0118]

As is apparent from the above description,
According to the flip-chip type liquid crystal display device of the present invention, it is possible to provide an input terminal portion which can be electrically connected to a high-density bump with low resistance and high reliability. A high quality screen without unevenness can be displayed.

[Brief description of the drawings]

FIG. 1 is an enlarged plan view of an input wiring Td to a driving IC according to the present invention.

FIG. 2 is an enlarged plan view illustrating a relative position between an input terminal IP and a bump of a driving IC according to the embodiment of the present invention.

FIG. 3 is an enlarged plan view showing a relative position between an input terminal IP and a divided bump of a driving IC according to another embodiment of the present invention.

FIG. 4 shows another embodiment of the present invention, in which a metal layer forming a gate wiring is used as a wiring of a low-resistance metal layer, and the wiring of the low-resistance metal layer is formed under a transparent conductive film. FIG. 4 is an enlarged plan view showing a relative position between a structure of an input terminal IP and a bump of a driving IC when formed so as to protrude.

FIG. 5 is a diagram showing a resistance between terminals and a measuring method when a wiring of a low-resistance metal layer is formed below or above a transparent conductive film.

FIG. 6 shows a transparent insulating substrate SUB of the liquid crystal display device of the present invention.
FIG. 2 is a plan view showing a state in which a driving IC is mounted on 1.

FIG. 7 shows a transparent insulating substrate SUB of the liquid crystal display device of the present invention.
FIG. 2 is a plan view of the vicinity of a portion on which a driving IC is mounted on a substrate 1 and a main portion near a cutting line CT1 of the substrate.

FIG. 8 is a main part of FIG. 7 (a corner portion of a driving IC input side);
FIG.

FIG. 9 is a diagram showing a correspondence between a substrate-side input terminal structure and a driving IC-side bump for each input signal.

FIG. 10 is a plan view schematically showing a conventional input terminal structure and a resistance value up to a bump.

FIG. 11 is a plan view schematically showing an input terminal structure of the present invention and a resistance value up to a bump.

FIG. 12 is a plan view schematically showing an input terminal structure of the present invention and resistance values up to divided bumps.

13 is a schematic cross-sectional view taken along the line GG of FIG. 1 after mounting the driving IC.

FIG. 14 is a schematic circuit diagram showing a resistance division portion in a typical multi-gradation display driving IC and a reference power supply line for supplying a gradation voltage to the driving IC.

FIG. 15 is a diagram showing an applied voltage-transmittance characteristic of a typical liquid crystal.

FIG. 16: A bendable multilayer flexible substrate FP
It is a perspective view which shows the method of bending and mounting C on a liquid crystal display element.

FIG. 17 is a sectional view taken along the line AA in FIG. 6;

FIG. 18 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 19 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of Steps D to E on the substrate SUB1 side.

FIG. 20 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes FG on the substrate SUB1 side.

FIG. 21 is a block diagram showing a liquid crystal display panel and circuits arranged around the liquid crystal display panel.

FIG. 22 is a diagram showing flows of display data and a clock signal from the display control device to the gate and drain drivers.

FIG. 23 is a diagram showing a common voltage applied to a common electrode, a drain voltage applied to a drain electrode, a level of a gate voltage applied to a gate electrode, and a waveform thereof in a TFT liquid crystal display module.

FIGS. 24A and 24B are main-portion cross-sectional views of a liquid crystal display module.

FIG. 25 is a perspective view of a notebook personal computer or a word processor on which a liquid crystal display module is mounted.

[Explanation of symbols]

 BUMP-Bump of driving IC FPC-Flexible board Td-Input wiring section IP-Input terminal section SBP-Single bump structure WBP-Double bump structure JUT-Protruding part

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shiro Ueda 3300 Hayano Mobara-shi, Chiba Electronic Device Division, Hitachi, Ltd. (56) References JP-A-3-222348 (JP, A) JP-A-5 JP-14911 (JP, A) JP-A-7-5484 (JP, A) JP-A-2-23843 (JP, A) JP-A-63-276232 (JP, A) JP-A-6-27477 (JP, A JP-A-2-223925 (JP, A) JP-A-2-245736 (JP, A) JP-A-3-56936 (JP, A) JP-A-3-242623 (JP, A) 33138 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/1345

Claims (7)

(57) [Claims] 1. Two transparent sheets superposed via a liquid crystal layer
An insulating substrate, mounted on a surface of one of the transparent insulating substrates on the liquid crystal layer side;
Liquid crystal drive circuit, inputting a signal to the liquid crystal drive circuit
A flexible substrate, and provided on the liquid crystal layer side surface of the one transparent insulating substrate.
And the output terminal of the flexible substrate is connected to the liquid crystal driving circuit.
Provide multiple input wires that are electrically connected to
In addition, each of the plurality of input wires is connected to the one transparent insulating substrate.
A first metal layer formed on the liquid crystal layer side surface of
(1) the output end of the flexible substrate, which covers the metal layer;
Formed in contact with the input terminal of the liquid crystal driving circuit
And a transparent conductive film formed on the transparent conductive film and
The output terminal side of the flexible substrate and the liquid crystal
Each of the transparent conductive films is formed on the input terminal side of the drive circuit.
A second metal contacting the first metal layer through the formed opening
And a protective film covering the second metal layer, wherein the first metal layer and the second metal layer are formed of the transparent conductive film.
The transparent conductive film extends to the outside of the protective film to extend the liquid crystal.
An exposure portion connected to an input terminal of the drive circuit, wherein the second metal layer extends along the extending direction of the transparent conductive film.
A protrusion protruding above a part of the exposed portion of the transparent conductive film
Liquid crystal display device having a minute. 2. The protection film according to claim 1, wherein the protection film is formed on the protrusion of the second metal layer.
And partially covering the exposed portion of the transparent conductive film.
The liquid crystal display device according to claim 1, wherein the liquid crystal display device is covered. 3. The input terminal of the liquid crystal drive circuit is provided with a
The input wiring included in each of the plurality of input wirings
The bumps are connected to the exposed portions of the transparent conductive film.
The liquid crystal display device according to claim 1 or claim 2. 4. The transparent substrate according to claim 1 , wherein the projecting portion of the second metal layer is transparent.
Mashimashi urchin extension by dividing the exposed portion of the conductive film, the transparent
The bump is provided on each of the divided exposed portions of the conductive film.
The liquid crystal display device according to claim 3, wherein the liquid crystal display devices are respectively connected. 5. The method according to claim 1, wherein the first metal layer is provided on the transparent conductive film.
An extension of the first metal layer extends to a lower side of the protrusion.
2. The method according to claim 1, wherein the light-transmitting film is covered with an exposed portion.
3. The liquid crystal display device according to 2. 6. The second metal layer is made of aluminum or copper.
3. A metal layer mainly composed of a metal layer.
Liquid crystal display device. 7. The first metal layer is made of aluminum, black,
Or a metal layer mainly composed of tantalum.
The liquid crystal display device according to claim 2.