JP3345265B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phase lock).
ed loop) circuit, in particular, it is possible to change the setting of the frequency pull-in speed while suppressing large-scale circuit and deterioration of circuit characteristics, and it is suitable for application to various devices such as synthesizers and phase shifters. Related to a simple PLL circuit.

[0002]

2. Description of the Related Art In recent years, PLL circuits have been applied to information processing apparatuses in various fields. As an application example, there are an electronic device built in an electronic musical instrument and a transceiver for oscillating a signal of a predetermined frequency, and a control signal generator for various actuators such as a brushless motor. In addition, it has been widely used for digital signal processing and the like with the development of multimedia technology in recent years.

[0003] Examples of applications in the digital technology field include C
D (compact disc), LD (laser disc),
It is frequently used in a circuit for generating a clock signal for reading digital information from a digital information storage medium such as a DVD (Digital Video Disk), and also in a reproducing circuit system for reproducing digital information using the clock. further,
Its application fields are diverse and various, such as analog-to-digital converters and reference clock generation circuits used in digital-to-analog converters.

FIG. 1 shows an example of a conventional configuration of a PLL circuit used in various devices. FIG. 1 shows a first configuration example of a conventional analog PLL circuit.
The analog PLL circuit includes a phase comparator 1 that outputs a signal indicating a phase difference between a reference signal and an output signal, a charge pump 2 that outputs a current according to the phase difference signal, and a filter 3 that performs a signal smoothing process. And a voltage controlled oscillator (VCO) 4 that outputs a signal having a frequency corresponding to the input voltage, and operates so as to output an output signal having the same phase as the reference signal via an output terminal.

[0005] Each component is a known circuit and will not be described in detail, but will be briefly described. The phase comparator 1 operates to output a signal indicating the phase difference between the reference signal and the output signal, and can be realized by a circuit configuration of a type called a sample hold circuit type, an EX-OR circuit type, or the like. Have been. Note that a phase comparator 1 called an edge type is adopted. In this case, it is known that the gain Kd of the phase comparator 1 is usually represented by “1 / π”. Although a detailed description of the configuration is omitted, as shown in FIG.
Will give an "up" signal if the phase of the reference signal is ahead of the phase of the output signal, and conversely, if the phase of the reference signal is behind the phase of the output signal,
It is configured to output a “down” signal.

FIG. 3 schematically shows the structure of the charge pump 2 (output current Icp). The charge pump 2 has “up
(Up) ”signal, the switch 8 is turned on, the current“ Icp ”flows from the current source 5, and
When the “down (down)” signal is input, the switch 7 is turned on and the current “−Icp” flows from the current source 6. The switches 7 and 8 schematically shown are specifically constituted by switching elements such as MOS FETs.

The filter 3 connects a resistor R1 and a capacitor C1 in series, and further connects a capacitor C2
Are connected in parallel, and operate as a low-pass filter.

The voltage controlled oscillator (VCO) 4 outputs a signal having an oscillation frequency proportional to the control voltage input to the point a to the point b. In the voltage controlled oscillator (VCO) 4, let Kcvo be a proportional coefficient when outputting a signal having an oscillation frequency proportional to the control voltage input to the point a.

In the PLL circuit thus configured, first, the phase comparator 1 outputs a signal indicating the phase difference between the reference signal and the output signal, and the charge pump 2 outputs a current corresponding to the signal indicating the phase difference. The output and the signal filtered by the filter 3 drive the voltage controlled oscillator (VCO) 4 to obtain an output signal having the same phase as the phase of the reference signal. For example, when digital information as described above is reproduced using a clock output from a clock generation circuit configured using a PLL circuit that performs such an operation, a change in the rotation speed of a storage medium such as a disk is affected. It is possible to configure a digital signal reproduction circuit system that is not used, and a device that reproduces a stable digital signal by applying it to a control system of a spindle motor that actually rotates a storage medium such as a disk is widely used. are doing.

Now, in the PLL circuit shown in FIG.
It is known that the transfer function of the open loop of LL is given by the following equation (1) when C2≪C1. In the following, the calculation process in the middle is omitted, and only the calculation result is described.

[0011]

(Equation 1) Further, the speed of pulling in the frequency of the PLL circuit depends on the band (band width) ω of the PLL circuit indicated by the transfer function, and the band ω is obtained by the following equation (2):
Also, a damping coefficient ξ (damping) indicating the stability of the PLL circuit.
factor: dumping factor) is known to be obtained by the following equation (3). Note that the attenuation coefficient。 may be simply referred to as “attenuation rate”.

[0012]

(Equation 2)

[0013]

(Equation 3) Now, when changing the band ω of the PLL circuit in order to change the frequency pull-in speed of the PLL circuit, the charge pump current Icp and the proportional coefficient Kvc of the voltage controlled oscillator are changed.
This is realized by changing the value of o.

FIG. 4 shows a second example of the configuration of a conventional analog PLL circuit. This circuit is based on the literature `` I Triple E 1993 Custom Integrated Circuit Conference 10.2.1 (IEEE 1993 CUSTOM INTEGRATE
D CIRCUITS CONFERENCE 10.2.1) ".

In FIG. 4, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. The feature of this circuit is that the output of the phase comparator 1 is supplied to two charge pumps 21 and 22, and the output of each of the charge pumps 21 and 22 is supplied to the input terminal of the filter 3, a resistor R and a capacitor constituting the filter 3. It is configured to supply the voltage to the connection point (intermediate terminal) of the element C1.

Now, the output current of the charge pump 21 is represented by Ic
p1 and the output current of the charge pump 22 is Icp2. Here, the charge pump currents Icp1 and Icp2 are referred to as “Ks · Icp1” and “Ks · (Ks─1) · I, respectively.
cp1 ”(where Ks is an arbitrary number).
It is known that when ≪C1, the transfer function of the open loop of the present PLL circuit is obtained as in the following equation (4).

[0017]

(Equation 4) Further, the band ω of the PLL circuit at this time is obtained by the following equation (5), and the attenuation coefficient 示 す indicating the stability of the PLL circuit is:
It is known that it can be obtained by the following equation (6).

[0018]

(Equation 5)

[0019]

(Equation 6) In this circuit, by changing Ks, equation (5)
, The band ω can be changed, and as can be seen with reference to equation (6), the attenuation coefficient ξ is constant even when Ks is changed.

FIG. 5 shows how the charge pump currents Icp1 and Icp2 and the band ω change when Ks is changed. The band at each Ks is “Ks = 1”.
Is shown as “ω”.

As described above, the band ω can be changed by changing Ks, but the charge pump current Icp
1, Icp2 are “Ks times” and “Ks ·” of Icp, respectively.
(Ks−1) times ”, which means that the charge pump 2 shown in FIG. 3 is changed to“ Ks pieces ”,“ Ks · (Ks−1)
It means that the circuit configuration is provided.

[0022]

However, in the above-described first configuration example of the conventional analog PLL circuit, when the frequency ω of the PLL circuit is changed in order to change the frequency pull-in speed of the PLL circuit. Are the charge pump current Icp and the proportional coefficient Kvco of the voltage controlled oscillator.
In this case, the attenuation coefficient ξ also changes as can be seen with reference to the equation (3), and it is difficult to optimize the attenuation coefficient に し while setting the value of the band ω to a desired value. It was difficult.

In the second example of the conventional analog PLL circuit, the band ω can be changed by changing Ks, and even if Ks is changed, the attenuation coefficient 一定 is constant. is there. However, since the charge pump current is made variable by changing Ks, the circuit system becomes complicated, and the steady-state phase error and the like increase, which tends to deteriorate the performance of the circuit. In addition, in order to increase the band ω by N times, the charge pump current must be increased by N ² times, so that there is a problem that the circuit scale is dramatically increased.

Accordingly, the present invention has been made to solve the above-mentioned problems, and has as its object to suppress deterioration of characteristics such as a steady phase error and an increase in jitter without changing the attenuation coefficient ξ. Another object of the present invention is to provide a PLL circuit capable of changing a band while changing the band.

Another object of the present invention is to provide a PLL circuit which can be manufactured while suppressing an increase in circuit scale, even when the band can be largely changed.

[0026]

According to the first aspect of the present invention, there is provided a PLL for generating an output signal having the same phase as a given reference signal. A circuit for outputting a signal corresponding to a phase difference between the reference signal and the output signal; a charge pump for outputting a current corresponding to the signal corresponding to the phase difference; and two or more circuits A filter for performing signal filtering, including a first-order response delay unit configured by connecting elements, and an adder for adding an output voltage of the filter and a voltage at any connection point of the two or more circuit elements When,
A PLL circuit is provided that includes a voltage-controlled oscillator that generates the output signal so as to have a frequency corresponding to the added voltage value.

According to a second aspect of the present invention, in the first aspect of the present invention, the primary response delay section is configured by connecting a resistance element and a capacitance element, and the addition of the adder is performed. A PLL circuit is provided, wherein one of the objects is a voltage at a connection point between the resistance element and the capacitance element.

According to a third aspect of the present invention, in the first aspect of the present invention, the adder includes means for multiplying the output voltage value of the filter by “Kg (Kg is an arbitrary number)”. Means for multiplying the value of the voltage at any one of the connection points of the two or more circuit elements by “Kg · (Kg−1)”;
And a means for adding the multiplication results of both means.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 6 shows a configuration diagram of a PLL circuit according to the first embodiment of the present invention.

Components having the same functions as those in FIG. 1 are denoted by the same reference numerals. The PLL circuit includes a phase comparator 1 that outputs a signal indicating a phase difference between a reference signal and an output signal, a charge pump 2 that outputs a current according to the signal indicating a phase difference, and a filter that performs a signal smoothing process. 3
And an adder 100 that adds the output voltage of the filter 3 and the output voltage of the intermediate terminal, and a voltage controlled oscillator (VCO) 4 that outputs a signal having a frequency corresponding to the input voltage.

The filter 3 includes a first-order response delay unit connecting the resistor R and the capacitor C1, and performs a signal filtering process. The connection point between the resistor R and the capacitor C1 is called an intermediate terminal, and the output voltage of the intermediate terminal is equal to the adder 1
00 is input. The first-order response delay unit is a circuit unit whose transfer function is expressed so as to output a first-order delay signal with respect to an input signal, and the filter 3 is configured to include the first-order response delay unit. Any lag-lead filter may be used.

As the filter 3, various lugs are used.
It is possible to employ a filter, a lag-lead filter, or the like, and as shown in FIG. 7A, a passive filter including a first-order response delay unit connecting a resistor R and a capacitor C1. Or an active filter including a first-order response delay unit in which a resistor R and a capacitor C1 are connected between an inverting terminal and an output terminal of an operational amplifier A, as shown in FIG. Further, as shown in FIG. 7C, a first-order response delay unit having a resistor R and a capacitor C1 connected between an inverting terminal and an output terminal of the operational amplifier B,
An active filter or the like including a capacitive element C2 connected in parallel to the next response delay unit is conceivable. In each filter shown in FIG. 7, the resistance R and the capacitance element C1
Is the intermediate terminal. Of course, the filter 3 applicable to this circuit is not limited to the one shown in FIG.

The adder 100 includes a voltage-current converter 101 for converting the output voltage of the filter 3 into a current with a conversion coefficient gm1, and a voltage-current converter 102 for converting the output voltage of the intermediate terminal into a current with a conversion coefficient gm2. And the voltage-current converter 1
01 and the sum of the output currents of the voltage-to-current converter 102 are input, converted to a voltage, and output.
3 is provided. Note that, as the conversion coefficient of the current-voltage conversion unit 103, an arbitrary real value is determined in advance,
The circuit may be configured to perform voltage conversion.

Now, assuming that Kg is an arbitrary number, the conversion coefficient gm
1, gm2 is “Kg”, “Kg · (Kg−1)”, respectively.
And FIG. 8 shows the voltage-current converter 101 (10
2) shows one configuration example.

The circuit shown in FIG. 8 has a power supply voltage of VDD, a ground voltage of VSS, a bias voltage of VBB, and a plurality of P-type MOSFETs 200 and a plurality of N-type MOSFETs 2.
01 and performs an operation of converting the input voltage V into the output current I. Since such a circuit configuration is known, a detailed description of the operation will not be given. Also, of course,
The voltage-current converter 101 (102) is not limited to the circuit configuration as shown in FIG. 8, but is a circuit that performs a voltage-current conversion operation, and can be realized by a known circuit that can change a conversion coefficient. Note that the circuit shown in FIG. 8 has a configuration in which two current generation units 100 that supply a current when a predetermined voltage is applied to a terminal are provided. When a predetermined voltage is applied only to the terminal a1, “Kg = 1” is obtained, and the terminal a
When a predetermined voltage is applied to terminal 1 and terminal a2, “Kg
= 2 ".

Specifically, first, when a voltage V is applied to a voltage terminal (existing on the left side in the figure), an N-type MOSFET is applied.
201c and 201d are turned on, and the P-type MOSF
The ETs 200c and 200d are turned on, and the P-type MOSFETs 200a and 200b constituting each current generating unit 150 are turned on. Note that the N-type MOSFETs 201e, f,
g is in an on state with the bias voltage VBB applied to its own gate terminal.

In this state, when a predetermined voltage is applied to the terminal a1, the N-type MOSFET 201a is turned on, and a current is output from the power supply VDD to the current terminal via the P-type MOSFET 200a and the N-type MOSFET 201a. You. Similarly, when a predetermined voltage is applied to the terminal a2, the N-type MOSFET 201b is turned on, and the P-type MOSFET 200b and the N-type MOSFET
A current is output to the current terminal via T201b.
With such a circuit operation, as described above, the terminal a
When a predetermined voltage is applied to only 1, “Kg = 1”, and when a predetermined voltage is applied to the terminals a1 and a2, “Kg = 2”. In general, a plurality of current generation units 100 are provided, and a conversion coefficient can be changed by adjusting a predetermined voltage applied to a terminal included in each current generation unit 100.

In the PLL circuit thus configured, first, the phase comparator 1 outputs a signal indicating the phase difference between the reference signal and the output signal, and the charge pump 2 outputs a current corresponding to the signal indicating the phase difference. Output and give to filter 3.

Then, the output voltage of the filter 3 and the voltage of the intermediate terminal are input to the voltage-current converter 101 and the voltage-current converter 102, respectively. The voltage-current converter 101 and the voltage-current converter 102 each set the input voltage to “Kg”.
The current multiplied by “Kg · (Kg−1)” is supplied to the current-to-voltage converter 103. Then, the current-voltage converter 103 converts the supplied current into a voltage and supplies the voltage to the voltage-controlled oscillator 4. The voltage controlled oscillator 4 is driven so as to oscillate a signal having a frequency according to the applied voltage, and the present PLL circuit can obtain an output signal having the same phase as the phase of the reference signal.

Now, if the transfer function of the open loop of the present PLL circuit is C2≪C1, the following equation (7) is obtained by calculation. Here, the description of the calculation process is omitted to avoid complicating the description, and only the calculation result is described.

[0041]

(Equation 7) In addition, a calculation based on this transfer function yields PL at this time.
The band ω of the L circuit is given by the following equation (8).
The attenuation coefficient 示 す indicating the stability of the L circuit is calculated by the following equation (9). Again,
The description of the calculation process is omitted, and only the calculation result is described.

[0042]

(Equation 8)

[0043]

(Equation 9) As can be seen by referring to these equations, even when Kg is changed to change the band ω of the PLL circuit, the attenuation coefficient ξ is a constant value. Therefore, the band ω and the attenuation coefficient ξ can be set independently, and the optimum setting of the band ω and the attenuation coefficient 容易 is facilitated. Also, since the current value output by the charge pump is constant, it is possible to minimize performance degradation such as steady phase error and jitter.

Therefore, such a PLL circuit is applied to a clock generation circuit for reproducing digital information, etc.
By reproducing digital information, it is possible to greatly reduce the error rate of reproduced data.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIG. This PLL circuit includes a phase comparator 1 that outputs a signal indicating a phase difference between a reference signal and an output signal, two charge pumps 21 and 22 that output a current according to the phase difference signal, and performs a signal smoothing process. And a voltage-controlled oscillator (VCO) 4 that outputs a signal having a frequency corresponding to the input voltage. Is done. Note that components having the same functions as those in FIG. 6 are denoted by the same reference numerals and will not be described in detail.

As in the first embodiment, the voltage-current conversion coefficients gm1 and gm1
2 are “Kg” and “Kg · (Kg−1)”, respectively.
Note that, with reference to FIG. 9, only the configuration of the charge pump 21 (22) will be described. Now, the charge pump current Icp output from the charge pumps 21 and 22
1 and Icp2 are “Ks · Icp1” and “Ks · (K
s-1) · Icp2 ”(Ks is an arbitrary number).

The present charge pump 21 includes a plurality of current units 210, and each current unit 210
Turns on the switch 8 when the "up signal" is given, outputs the current "Icp" from the current source 5, and turns on the switch 7 when the "down signal" is given. The current source 6 is configured to output a current “−Icp”, and a current is output by applying a predetermined voltage to a terminal of the switching element 220. FIG. 9 shows a charge pump 21 having a configuration including two current units 220. When a predetermined voltage is applied only to the terminal b1, “Ks = 1”, and the predetermined voltage is applied to the terminals b1 and b2. When applied, “Ks = 2”. As described above, generally, a configuration is provided in which a plurality of current units 200 are provided, and the value of the charge pump current can be changed by adjusting a predetermined voltage applied to the terminal provided in each current unit 220. Note that the charge pump 22 is also
It can be realized by a configuration similar to

Now, if the transfer function of the open loop of the present PLL circuit is C2 の C1, the following equation (10) can be obtained by calculation. Here, to avoid complicating the description, the description of the calculation process is omitted, and only the calculation result is described.

[0049]

(Equation 10) In addition, a calculation based on this transfer function yields PL at this time.
The band ω of the L circuit is given by the following equation (11).
The attenuation coefficient を indicating the stability of the LL circuit is obtained by calculation to be given by the following equation (12). Also in this case, the description of the calculation process is omitted, and only the calculation result is described.

[0050]

[Equation 11]

[0051]

(Equation 12) As can be seen from equation (11), since the band ω of the PLL circuit is proportional to “Ks · Kg”, the current generation unit 150 does not need to increase the values of Ks and Kg.
And Ks and Kg without providing many current units 210
The value of the band ω, which is a value proportional to the product of “Ks · Kg”, can be changed, so that a PLL circuit with a large band ω change width can be realized without increasing the circuit configuration. Becomes possible.

As an example, to configure a PLL circuit that can change the band ω from 1 to 9 times, “Ks = 3, Kg
= 3 ”,“ Ks · Kg = 9 ”, and the charge pump currents Icp1 and Icp2 are“ Icp1 = 3, Icp ”.
2 = 6 ”, and the voltage-current conversion coefficients gm1 and gm2 are“ gm1
= 3, gm2 = 6 ". In the second configuration example of the conventional analog PLL circuit shown in FIG. 4, in order to configure a PLL circuit capable of changing the band ω from 1 to 9 times, the charge pump currents Icp1 and Icp2 are set to “Icp
1 = 9, Icp2 = 72 ”and the voltage-current conversion coefficients gm1 and gm2 must be“ gm1 = 1, gm = 0 ”.

Therefore, the circuit scale necessary for realizing “1” for both Icp and gm, in other words, the circuit scale necessary for manufacturing one current generating unit 150 and one current unit 210 are manufactured. Considering that the circuit scale required for the above is about the same circuit scale, the circuit scale can be reduced to "18/82" in order to realize a PLL circuit having the same band change width.

As described above, according to the first embodiment, the attenuation coefficient 示 す indicating the stability and the band ω can be changed independently, so that the attenuation coefficient ξ and the band ω can be optimized. , And it is possible to realize a PLL circuit in which an increase in steady phase error, jitter and the like is suppressed.
Therefore, by applying the present PLL circuit to a clock generation circuit or the like for reproducing digital information and reproducing digital information, the error rate of reproduced data can be significantly reduced. Further, according to the second embodiment, it is possible to realize a PLL circuit having a large change width of the band ω without increasing the circuit scale.

[0055]

As described above, according to the first aspect of the present invention, a PLL circuit includes a first-order response delay unit configured by connecting two or more circuit elements, and performs signal filtering. A filter, further comprising an adder for adding the output voltage of the filter and the voltage at any one of the connection points of the two or more circuit elements, wherein an output signal having a frequency corresponding to the added voltage value is provided. Generates
The attenuation coefficient 示 す indicating the damping state at the time of signal pull-in and the band ω can be set independently, and it is also possible to suppress an increase in steady-state phase error, jitter, and the like.

According to a second aspect of the present invention, the first response delay section is constituted by connecting a resistance element and a capacitance element,
Since one of the objects to be added by the adder is a voltage at a connection point between the resistance element and the capacitance element, the PLL circuit of the present invention can be realized with a simple configuration in addition to the effect of the invention described in claim 1. This has the effect.

According to the third aspect of the present invention, in addition to the effect of the first aspect of the invention, the value of the output voltage of the filter is multiplied by "Kg (Kg is an arbitrary real number)".
Further, the value of the voltage at any one of the connection points of the two or more circuit elements is multiplied by “Kg · (Kg−1)”, and the two multiplication results are added. Since the output signal is generated, even if the change width of the band of the PLL circuit is large, the PLL circuit can be manufactured without increasing the circuit scale corresponding to the change width of the band.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration example of a conventional PLL circuit.

FIG. 2 is an explanatory diagram of an operation of a phase comparator.

FIG. 3 is an explanatory diagram illustrating a configuration of a charge pump.

FIG. 4 is a configuration diagram showing another configuration example of a conventional PLL circuit.

FIG. 5 is an explanatory diagram of an operation of a conventional PLL circuit.

FIG. 6 is a configuration diagram of a first embodiment of the present invention.

FIG. 7 is an explanatory diagram of a configuration example of a filter applicable to the present invention.

FIG. 8 is a configuration diagram illustrating a configuration example of a voltage-current converter.

FIG. 9 is an explanatory diagram illustrating a configuration of a charge pump.

FIG. 10 is a configuration diagram of a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Charge pump 3 Filter 4 Voltage controlled oscillator 5 Current source 6 Current source 7 Switch 8 Switch 21 Charge pump 22 Charge pump 100 Adder 101 Voltage-current converter 102 Voltage-current converter 103 Current-voltage converter 150 Current generation Unit 200 P-type MOSFET 201 N-type MOSFET 210 Current unit 220 Switching element

Claims (3)

(57) [Claims] 1. A PLL circuit for generating an output signal having the same phase as a given reference signal, comprising: a phase comparator for outputting a signal corresponding to a phase difference between the reference signal and the output signal; A charge pump that outputs a current corresponding to a signal corresponding to the phase difference, a filter that includes a primary response delay unit configured by connecting two or more circuit elements and performs signal filtering, an output voltage of the filter, and A PLL comprising: an adder for adding a voltage at any one of the connection points of the two or more circuit elements; and a voltage-controlled oscillator for generating the output signal so as to have a frequency corresponding to the added voltage value.
circuit. 2. The delay circuit according to claim 1, wherein the first-order response delay section is configured by connecting a resistance element and a capacitance element, and sets one of the addition targets of the adder to the resistance element and the capacitance element. A PLL circuit characterized in that the voltage at the connection point is: 3. The device according to claim 1, wherein the adder multiplies a value of an output voltage of the filter by “Kg (Kg is an arbitrary number)” and a connection point of any one of the two or more circuit elements. And a means for multiplying the value of the voltage by “Kg · (Kg−1)” and a means for adding the multiplication result of both means.