JP3345283B2 - Active wafer level contact system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] This application is assigned to the assignee of the present invention and is hereby incorporated by reference, under co-pending US Provisional Patent Application No. 6 / 13,1995, filed November 13, 1995.
No. 0 / 006,432, claiming priority over the title of the invention "planar contact of active wafer" under 35 U.S.C. 119 (e) (1).

The present invention relates generally to the field of integrated circuit electrical interconnect and test systems. More specifically, the present invention relates to an active wafer planar contact system for connecting an integrated circuit device arranged on a wafer and a tester for testing and analyzing the integrated circuit device.
Preferred embodiments of the present invention include an active wafer planar contact system having at least a portion of signal conditioning or an integrated circuit test system disposed on the active wafer planar contact system.

[0003]

BACKGROUND OF THE INVENTION In a typical semiconductor manufacturing facility, each integrated circuit is tested using tester equipment. The test equipment is connected to the integrated circuit via an interconnect system. Tester equipment tests the function and performance of the integrated circuit via the interconnect system.

As the performance of modern semiconductor devices, such as, for example, their speed, is improving, it is increasingly difficult for manufacturers to test the "speed" of these devices. Testing of high performance semiconductor devices requires accurate impedance matching and minimum parasitic capacitance to limit distortion of the performance characteristics of the device under test.

[0005] Integrated circuits are typically mass-produced on silicon wafers using integrated circuit wafer processing techniques. After integrated circuit fabrication is completed, each integrated circuit is removed from the silicon wafer for packaging. Testing individual integrated circuits while still on the wafer saves cost and saves time.

One of the prior art wafer planar contact devices is a probe card contact system. The probe card contact system has an opening larger than the integrated circuit device under test. A relatively rigid, fixed position metal pin with a sharp tip extends from the probe card through the opening. The number of pins is determined by the input / output (I /
O) It corresponds to the number of pads. When the probe card is positioned on the integrated circuit device, the sharp tips of the metal pins make direct contact with the corresponding I / O pads on the integrated circuit device under test, and the pins are shaped like long cantilevers. Electrical signals are conducted between the integrated circuit device under test and the probe card.

A tester is connected to the probe card for testing various performance characteristics of the integrated circuit device under test.
The probe card also includes termination circuits, such as resistors and capacitors, for adjusting the test signal output to the tester.

It is desirable to provide a wafer planar contact system for testing the "speed" of high performance integrated circuit devices. Wafer planar contact systems should provide signal conditioning including accurate impedance matching and minimal parasitic capacitance. In addition, for a more efficient and economical test system, it is desirable to have an "active" wafer contact system with active circuitry that is integral with the wafer planar contact system.

[0009]

It is an object of the present invention to overcome these disadvantages of the description and the prior art. That is, an object of the present invention is to provide an active wafer planar contact system which deals with the description of the prior art and solves those problems. That is, the present invention relates to an active wafer planar contact system for connecting an integrated circuit device placed on a wafer and a tester for performing test analysis of the integrated circuit device.

[0010]

SUMMARY OF THE INVENTION A preferred embodiment of the present invention includes an active wafer planar contact system having at least a portion of signal conditioning, or an integrated circuit test system disposed on the active wafer planar contact system.

In one embodiment, the present invention is an apparatus for testing semiconductor devices placed on a wafer. The apparatus includes a wafer body. The device contact area is provided on the wafer main body and comes into contact with the semiconductor device. The active component area is connected to the device contact area. Means are provided for connecting the active component area to the remote test equipment.

[0012] The wafer body may be formed from silicon.
The device contact area further includes a contact element disposed in the device contact area at a position corresponding to the I / O pad of the semiconductor device. In one of the preferred embodiments, the contact elements are formed from solder bumps.

[0013] The active component area may include circuit components that are disposed integrally with the wafer. Circuit components can be formed using silicon wafer processing techniques such as silicon doping. The active component area may include a signal conditioning circuit or a semiconductor device test circuit. The semiconductor device test circuit may include a memory chip, a microprocessor, a transistor, or a logic gate. Further, the active component area may include a test system for testing a semiconductor device.

[0014] The connection means may comprise a large pad contact area. Further, the connection means may comprise a cable termination device.
In one embodiment, the wafer body is flexible. The flexible wafer body is fixed to a rigid support member. The rigid support member includes an inclined region and a flat region, the contact region is connected to the flat region, and the active component region is connected to the inclined region. Alternatively, the wafer body may be substantially rigid.

In another embodiment, a wafer body can include a first silicon substrate and a second silicon substrate bonded to the first silicon substrate. The contact area may be located on a first silicon substrate and the active component area may be located on a second silicon substrate.

The present invention may further comprise a replaceable contact system having a replaceable device contact site disposed between the contact area and the semiconductor device. In another embodiment, the invention is an apparatus used for testing semiconductor devices located on a wafer. The apparatus includes a wafer body.
Means for contacting the semiconductor device is connected to the wafer body. Means for providing an active component area on the wafer body are integrated with the wafer body. The active component area may include means for adjusting the test signal. The active component area also includes means for testing the semiconductor device.

An active wafer planar contact system according to the present invention is capable of testing high performance (speed) integrated circuit devices. Active wafer planar contact systems provide test signal conditioning with accurate impedance matching and minimal parasitic capacitance. Further, the active wafer contact system includes an active circuit arrangement integral with the active wafer planar contact system for a more efficient and economical test system.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS Other objects and various advantages of the present invention will be more clearly understood from the following detailed description of the invention with reference to the drawings. Here, the same reference numerals in the drawings indicate the same parts throughout the drawings.

The present invention is an active wafer planar contact system for connecting an integrated circuit device arranged on a wafer and a tester for analyzing the integrated circuit device. A preferred embodiment of the present invention comprises an active wafer planar contact system having at least a portion of signal conditioning, or an integrated circuit test system disposed on the active wafer planar contact system.

The present invention provides an active planar wafer contact system for testing high performance integrated circuits and semiconductor devices. The wafer planar contact system includes a signal conditioning and active circuit device integrated with the wafer planar contact system.

The associated wafer here is preferably formed from silicon, but may be manufactured from any other suitable active circuit manufacturing substrate (such as a bandgap).

The present invention, in one embodiment, includes a silicon wafer body. The contact region is connected to the silicon wafer body and contacts an input / output (I / O) pad of the integrated circuit device. The contact area preferably comprises a row of solder bumps corresponding to the I / O pads on the integrated circuit device for electromechanically connecting the wafer to the integrated circuit device to be tested.

The active component area is located on the wafer body. The active component area comprises active circuit components for testing integrated circuit devices, such as test signal conditioning circuits, test circuits or complete test equipment. The active circuit components are integrated with the silicon wafer using silicon wafer processing techniques such as doping and the like. The silicon wafer body further comprises a next planar I / O area connected to the active component area and including means for connecting the silicon wafer to a remote device, such as an integrated circuit device tester.

Referring to FIG. 1, a wafer planar contact system
Indicated by The wafer planar contact system is used for the wafer 22 under test.
Placed on top, the wafer 22 has devices 24 on its surface, and the system tests one device at a time. The wafer plane contact system 20 is lowered for electromechanical connection with a particular device 24 as shown by arrow 25 during performance testing of the device. Wafer plane contact system 20
Are placed on the wafer 22 under test and connected to a tester 26 for performing a performance test of the apparatus 24.

The wafer 22 includes a plurality of devices 24 selectively connected to the wafer plane contact system 20 for performance testing. In order to describe the wafer plane contact system 20 here, a particular device 28 under test located below the wafer plane contact system 20 is shown. Equipment under test 2
8 is an input / output (I / O) pad 30 (shown by a bump)
Semiconductor or integrated circuit device having

The wafer planar contact system 20 includes a support body 32 having an active silicon wafer 34 mounted on the system. Active silicon wafer 34
Will be described later in this specification. The active silicon wafer 34 is electrically connected to the tester 26. The active silicon wafer 34 may be electrically connected to the tester 26 via the interface circuit 36 and the interface circuit 38.

In one embodiment, the support body 32 is rigid and formed of plastic. Support body 32
Is substantially rectangular and includes a top surface 39 and a bottom surface 40. The upper surface 39 shows arrows to move the wafer plane contact system 20 between a position where the wafer plane contact system 20 contacts the device under test and a position where the wafer plane contact system 20 does not contact the device under test. It is mechanically connected to a mechanism (not shown) as shown at 42.

The bottom surface 40 substantially corresponds to the first inclined region 4.
4, a flat region 46 and a second inclined region 48 are provided. The sloped region may be curved or rounded. The active silicon wafer 34 is a flexible silicon wafer that is formed and bent to be fixed to the support body bottom surface 40. Specifically, the active silicon wafer 34 is fixed along the first inclined region 44, the flat region 46, and the second inclined region 48. Structurally,
The active wafer 34 is formed using semiconductor processing. The active silicon wafer 34 supports the silicon wafer 34 in a curved manner about a small radius of curvature along the bottom surface 40 between the first inclined region 44 and the flat region 46 and between the flat region 46 and the second inclined region 48. It is lined by the thickness of the material. A large pad area is provided for the next plane I / O connection.

The active silicon wafer 34 has a contact region 50, an active component region 52, an active component region 54, a connection pad region 56, and a connection pad region 58. The contact area 50 is flat,
It also includes contact elements 60 (shown as bumps) that are maintained parallel to the device 28 under test and provide an electromechanical connection to the device I / O pad 30 under test. In a preferred embodiment, contact element 60 is a solder bump. Active component area 52 and large pad contact area 56
Are located along the first sloped area 44 and the active component 54 and the large pad contact area 58
Are arranged along the inclined region 48.

The active component area 52 and the active component area 54 include active components such as test circuits or signal conditioning circuits. Large pad contact area 56 includes contact pads 62 (shown in FIG. 2) electrically connected to termination device 64. The interface circuit 66 includes the shielded cable 6
6, the cable 66 is electrically connected to the large contact pad 62 by the terminating device 64. A similar shielded cable 68 connecting the large contact pad 62 and the interface circuit 38 via the terminating device 70 is terminated at the terminating device 70. The first inclined region 44 and the second inclined region 48 allow the termination device 6
4, 70 and shielded cables 66, 68 do not interfere with or contact the upper surface of wafer 22 under test.

The interface circuit 36 is electrically connected to the remote tester 26 as indicated by reference numeral 74. The interface circuit 38 is electrically connected to the remote tester 26 as indicated by reference numeral 76.

FIG. 2 shows a plan view of one embodiment of the active silicon wafer 34. As shown, the large pad contact area 56 extends between points A and B, the active component area 52 extends between points B and C, and the contact area 50 extends between points C and D. Extending, the active component area 54 extends between points D and E, and the large pad contact area 58
Extends between point and point F. The active silicon wafer 34 is formed substantially from silicon. The active silicon wafer 34 may also be formed using wafer processing techniques and include a passivation layer that opens at contact points on the active silicon wafer 34 to protect circuits / devices located on the wafer 34. Good. The passivation layer (not shown) may be formed from glass or silicon dioxide.

The contact area 50 is used to electromechanically connect the device 28 under test. As can be seen from FIG. 3, the contact area 50 includes a contact element 60 for electromechanical coupling with the I / O pad 30 of the device under test. In one embodiment, contact elements 60 are contact bumps formed from solder for contacting I / O pads 30 of the device under test. The contact element 60 is the device 2 under test.
8 which are provided on the outer periphery of the area to be arranged and which are in contact with the internal pads of the device 28 under test in order to carry out a selective internal circuit test similar to the contact element 60 and as already mentioned. A contact element 78 may optionally be included .

The active circuit components are preferably located inside the active component area 52 and the active component area 54. Active component area 52 and active component area 54 include electrical circuits that are part of the test system. The circuit is preferably integrated on a silicon wafer using silicon circuit processing techniques such as silicon "doping". Alternatively, circuits including circuit components may also be surface mounted on silicon.

Circuits located within active component area 52 and active component area 54 include electrical components for performing signal conditioning or testing functions. In one embodiment, active component region 52 and active component region 54 may have contact elements 60, 60 due to impedance matching and minimization of parasitic capacitance causing performance signal interference.
It includes a resistor and capacitance termination network that regulates the test signal between 78 and tester 26.

By arranging active components on a silicon wafer, the present invention allows for the "speed" testing of high performance integrated circuit devices. The proximity of the signal conditioning and test circuit to the contact element allows
Test signal interference caused by cantilevered contact elements connected to long circuit conductors is minimized,
Or be excluded. Further, by arranging circuit components within the active areas 52, 54, the wafer planar contact system 20 can effectively use silicon processing techniques such as silicon doping and the like, thereby integrating the silicon wafer. Circuit components can be formed efficiently and economically.

Active component areas 52, 54
May include simple signal conditioning circuitry or more complex logic gates, transistors, memory chips or microprocessor based controllers to place some or all of the test equipment on the active silicon wafer 34. . For example, active component areas 52, 54 may include signal conditioning / termination circuitry. In another embodiment, the active component regions 52, 54 further comprise localized test circuits for performing tests of the integrated circuit device on the active silicon wafer 34. The test signal is sent back to tester 36, which includes a controller or other logic operator responsive to the completion of the microprocessor-based test. In another embodiment, the completed test units may be located in the active component areas 52,54. The completed test unit can be provided with signal conditioning circuits, transistors, logic gates, counters and memory chips. When the completed test unit is placed on the active silicon wafer 34, a simple "go" or "no go" signal is sent back to the tester 26, which passes or fails the integrated circuit device under test. Operates as a "dummy tester" for passing.

FIG. 4 shows a simple tester circuit arranged in the active component area 52 or 54 for performing a local test of the device 28 under test. In this example, the device under test 28
Is a random access memory (RAM) 28. The test circuit 80 includes a first counter 82, a second counter 8
4 and a comparator 86. The first counter 82 and the second counter 84, as shown at 88,
Activated by a signal received from If the most significant bit of the first counter 82 is zero, the R
AM is in the write mode, and data is written to each address location. If the most significant bit of the first counter 82 is 1
(Or more), the RA of the device under test 28
M operates in read mode and data is output to comparator 86 as shown at 94. Second counter 84
Is also connected to a comparator 86 as shown at 96 and is activated simultaneously with the first counter 82. If the most significant bit of the second counter 84 is equal to one (or more), the comparator 86 is activated. At that time, the comparator 86 outputs the data output from the RAM of the device under test 28 and the second data.
Of the device 28 under test.
An output is provided to tester 26 indicating whether M has a read / write error.

Since the test circuits are arranged on the active silicon wafer 34 using silicon processing technology, most of the test circuits can be arranged on the active silicon wafer 34. In a preferred embodiment, the active circuit components include active component regions 52
It is better not to dispose them at the position where is in contact with the contact region 50 and the position where the active component region 54 is in contact with the contact region 50. This is because these positions are curved.

Referring again to FIG. 2, the large pad contact area 56 and the large pad contact area 68 are formed of active silicon, such as shielded cables 66, 68 for connection to external or remote devices, such as the tester 26. It has a large contact pad 62 for connecting the wafer 34. The large contact pad 62 is used to connect the active silicon wafer 34 to the next planar connection to an external or remote device.
Provides a connection point between the microcircuit components located above. For example, a circuit such as a signal conditioning circuit or a test circuit may be located in the large pad contact area 56 or the large pad contact area 58 between the large contact pads 62, the circuit including the signal conditioning circuit and the test circuit described above. It is similar to a circuit.

With the unique wafer planar contact system 20 according to the present invention, signal conditioning or device testing on the active silicon wafer 34 can be achieved. The unique contact elements, active component areas, and large pad contact areas that are integrated into silicon using semiconductor processing techniques allow high performance semiconductor or integrated circuit devices to be economically and effectively tested.

A wafer plane contact system 20 according to the present invention
Another embodiment of is shown in FIG. The wafer planar contact system 20 includes a first active silicon wafer 104, a second
The active silicon wafer 106 and the supporting body 32 are provided. The first active silicon wafer 104 includes a flat region 108, a slant region 110, and a slant region 112. First active silicon wafer 104 and second active silicon wafer 104
The active silicon wafer 106 is formed from silicon and / or gallium arsenide using semiconductor processing technology. The support body 32 is formed from a substantially rigid circuit board material such as plastic. In this embodiment,
The second active silicon wafer 106 is larger than the first active silicon wafer 104. Support body 32
Is larger than the second active silicon wafer 106.

In this embodiment, the contact area 50 is
The active component area 52 and the active component area 54 are placed on the flat
The large pad contact area 56 and the large pad contact area 58 are disposed on the support body 32.

As already mentioned, the I of the device 28 under test is
/ O pad 30 corresponds to contact element 60 (and contact element 78) in contact area 50. The contact area 50 is flat,
And parallel to the test surface of the device 28 under test. The test signal is transmitted from the contact element 60 in the contact area through the inclined areas 110, 112 via paths 114, 116 (in silicon) terminating in the wire bonding pads 115, 117. Bonding paths 114, 116 are connected to similar wire bonding pads 119, 121 located on active component areas 52, 58 via path wires 118,120. The active component regions 52, 54 include signal conditioning and / or test circuits fabricated integrally with silicon using semiconductor processing techniques as described above. Furthermore,
The wire bonding pads 122 and 124 are connected to the active component regions 52 and 58 through the route wires 130 and 132 and the wire bonding pads 126 and
128 for electrical coupling and transmission of test signals
It is arranged on the corresponding active component area 52, 58.

Wire bonding pads 126 and 128
The test signal is transmitted to the support body 32 using vias and / or through holes (not shown) in the support body 32.
It is transmitted to the large contact pad 62 arranged above. The large contact pad 62 is connected to shielded cables 66 and 68 via termination devices 64 and 70.

Another embodiment of a wafer planar contact system 20 according to the present invention, similar to the embodiment shown in FIG.
Shown in In this embodiment, the second active silicon wafer 106 is formed in a size close to the support main body 32. All of the active component regions 52, 54, the large pad contact regions 56, 58 (including the large contact region 62) and the termination devices 64, 70 are located on the second active silicon wafer 106, or It is integrated with.

Wafer planar contact system 20 according to the present invention
FIG. 7 shows another embodiment of the present invention. In FIG. 7, reference numerals of some members are omitted for clarity. The active silicon wafer 34 is substantially rigid, is disposed between the support main bodies 32, and is connected to the support main bodies 32.
The active silicon wafer 34 substantially includes a bottom surface 34 having a flat region 136, a first inclined region 138, and a second inclined region 140. The contact area 50 is located in the flat area 136 and the active component area 5
4 and the large pad contact area 56 have a first sloped area 138.
The active component area 54 and the large pad contact area 58 are disposed on the second inclined area 140. The terminating devices 64 and 70 are connected to the corresponding large contact pads 62 and the shielded cable 6 leading to the tester 26.
6, 68.

Another embodiment of the present invention is shown in FIG. In this embodiment, the contact area 50, the active component areas 52, 54, the large pad contact areas 66, 68 and the terminators 64, 70 are all located on a common active silicon wafer 34 substrate. The active component regions 52 and 54 are electrically connected via vias in the active silicon wafer 34 to the large contact pads 62 arranged in the large pad contact regions 56 and 58. The via is formed by laser drilling or anisotropically so as to penetrate the active silicon wafer 34, and the via is filled with a metalized material.

[0049] Wafer planar contact system 20 according to the present invention
Another embodiment is shown in FIG. This embodiment is similar to the embodiment of FIG. In this embodiment, the active component regions 52, 54 are located on top of the active silicon wafer 34. The active component regions 52 and 54 are formed in the vias 14 in the same manner as described above.
6 to be electrically connected to the corresponding contact areas 50.

Wafer planar contact system 20 according to the present invention
Another embodiment is shown in FIG. This embodiment is similar to the previously described embodiment shown in FIG. Wafer planar contact system 20 further includes a replaceable contact system 150. With repeated use and testing, the contact elements located in the contact area 50 wear and deform. The replaceable contact system 150 can replace the contact elements in order to extend the useful life of the wafer planar contact system 20.

[0051] The replaceable contact system 150 typically includes a film 152 that is connected to a film feed system 154 (partially shown). The film 152 is inserted between the contact area 50 of the wafer planar contact system and the device 28 under test. FIG. 1 is a plan view of a part of the film 152.
It is shown in FIG. The film 152 includes a film substrate 154, a device part 156, and an index hole 158. Film substrate 154 is formed from a dielectric film material. The index hole 158 serves as an indicator of the position of the film 154 relative to the wafer plane contact system 20.
And used to connect to a sprocket mechanism for feeding the film, such as a film feed system 154.

The device portion 156 includes a conductive metal pad 160 separated from a non-conductive region 162 that is part of the film 154. The contact element 164 is a metal pad 16
0. In a preferred embodiment, contact element 164 comprises a solder module or solder bump (similar to contact element 60). The location and number of contact elements 164 correspond and correspond to the contact elements 60, 78 in the contact area and the I / O pad 30 of the device under test. For clarity of illustration, only a portion of the contact element 164 is shown in FIG.
It is shown in FIG.

FIG. 12 is a cross-sectional view of the device portion 156 according to one embodiment. The film 154 has a top surface 166 and a bottom surface 1
68. Metal pads 160 and contact elements 164 are located on top surface 166 and bottom surface 168. Corresponding metal elements 164 and metal pads 160 are electrically connected to each other through film substrate 154 using vias 170. Via 170 comprises a hole through a film substrate 154 having a conductive material, such as a metal embedded therein. Film 154 is typically taut against active silicon wafer 34.

A block diagram of one embodiment of the replaceable contact system 150 is shown at 172 in FIG. The replaceable contact system 150 includes a controller 174 for controlling the logical operation of the system 150. Controller 174 may be located within tester 26.
Wafer position sensor 176 and film position tracking sensor 178 provide corresponding inputs 180, 182 to controller 174. Further, the test equipment counter 18
4 supplies an input signal 186 to the controller 174. Further, other control inputs 188 provide other control signals 190 to controller 174. Based on the sensor input characteristics 180, 182, 186 and 190, the controller 174 outputs an output signal 192 for the performance test 194 and an output signal 1 for the film feed mechanism 198.
It provides other output signals 200 to 96 and other output devices 202.

In operation, the device site 156 is located between the contact area 50 of the active silicon wafer 34 and the I / O pad 30 of the device under test. Device part 15
6 maintains tension on the contact area 50 during and after testing of the device 28 under test. When the wafer plane contact system 20 is moved to the next device 24 for testing, the device portion 156 remains stationary with respect to the contact area 50. After the desired number of semiconductor tests, indicated by test equipment counter 184, have been completed, controller 174 outputs signal 19 to film advance mechanism 198 to advance film 152 to the next equipment site 156.
Supply 6. The position of the film device portion 156 with respect to the contact area 50 is determined by the film position tracking sensor 17.
8 and the wafer position sensor 176. Still other control inputs 188 are used to position device portion 156 with respect to contact area 50.

It can be seen that the unique active wafer planar contact system 20 according to the present invention has many embodiments. In addition to integrated circuit testing, the active component area on the active silicon wafer can also include burn-in circuitry for burning in the integrated circuit device. In addition, the wafer plane contact system 20 may be designed to individually test each device located on the wafer 22 under test, or may be configured with multiple wafer plane contact systems 20 connected together. A scale contact system may be designed to simultaneously test all devices placed on a wafer. In one particular embodiment, a normal location self-test read-only memory (RO)
M) The circuits may be located on an active wafer planar contact system, thereby eliminating the need to place these circuits on a microprocessor.

Various features and advantages of the invention have been described above. Of course, it will be understood that this disclosure is, in many respects, only illustrative. Details, i.e., the shape, size and arrangement of the components, can be varied without departing from the scope of the invention. The scope of the present invention is defined by the claims set forth below.

【The invention's effect】 According to the present invention, the active component
The contact area is connected close to the device contact area.
Is caused by a conventional cantilever-shaped contact element.
This minimizes the interference of the test signal,
Circuit components in the active component area
Circuit is integrated with the wafer body
Components can be formed efficiently and economically
It has an excellent effect of cutting.

[Brief description of the drawings]

FIG. 1 is an enlarged sectional view of a first embodiment of an active wafer contact system according to the present invention.

FIG. 2 is an enlarged plan view of the silicon wafer shown in FIG.

FIG. 3 is a partially enlarged plan view of a portion described as FIG. 3 in FIG. 2;

FIG. 4 is an example of a test circuit arranged on an active wafer contact system according to the present invention.

FIG. 5 is an enlarged sectional view of a second embodiment of the present invention.

FIG. 6 is an enlarged sectional view of a third embodiment of the present invention.

FIG. 7 is an enlarged sectional view of a fourth embodiment of the present invention.

FIG. 8 is an enlarged sectional view of a fifth embodiment of the present invention.

FIG. 9 is an enlarged sectional view of a sixth embodiment of the present invention.

FIG. 10 is an enlarged sectional view of a seventh embodiment of the present invention.

FIG. 11 is a partial plan view showing the film of FIG. 10;

FIG. 12 is an enlarged partial cross-sectional view of the contact area of FIG. 10;

FIG. 13 is a process block diagram illustrating the film feeding system of FIG. 9;

[Explanation of symbols] 26: tester, 34: active silicon wafer, 50
... contact area, 52, 54 ... active component area
Area, 56, 58 ... connection pad area, 60 ... contact element, 1
08 ... flat area, 110, 112 ... inclined area, 150 ...
Contact system.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-78496 (JP, A) JP-A-7-115113 (JP, A) JP-A-1-12542 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/66

Claims (17)

(57) [Claims] An apparatus used for testing an individual semiconductor device manufactured on a wafer, comprising: a wafer body; and a device contact area provided on the wafer body and in contact with the semiconductor device, wherein the device contact area is provided. Wherein the device contact region including a contact element disposed at a position corresponding to an I / O pad on the semiconductor device; and an active component region connected in close proximity to the device contact region, wherein An active component area including circuit components arranged integrally; and means provided on the wafer body for connecting the active component area to a remote test apparatus, wherein the wafer body is fixed to a rigid support member. The rigid support member includes an inclined area and a flat area, the device contact area is located in the flat area, and the I Bed component regions are disposed on the inclined region, the inclined region is formed so as to prevent the said connecting means is in contact with the web Ha device. 2. The apparatus according to claim 1, wherein said wafer body is formed of silicon. 3. The apparatus of claim 1 wherein the contact element is formed from solder. 4. The active component area,
The apparatus of claim 1, comprising a signal conditioning circuit. 5. The active component area,
The device of claim 1 including a semiconductor device test circuit. 6. The device according to claim 5, wherein the semiconductor device test circuit includes a storage circuit. 7. The active component area,
The apparatus according to claim 1, further comprising a test system for testing a semiconductor device. 8. The apparatus of claim 1, wherein said connection means includes a large pad contact area. 9. The apparatus according to claim 1, wherein said connection means includes a cable termination device. 10. The apparatus of claim 1, wherein said wafer body is flexible. 11. The apparatus of claim 1, wherein said wafer body is substantially rigid. 12. The apparatus according to claim 1, wherein the wafer body comprises a first silicon substrate and a second silicon substrate bonded to the first silicon substrate. 13. The apparatus of claim 12, wherein said contact area is located on said first silicon substrate and said active component area is located on said second silicon substrate. 14. The device of claim 1, further comprising a replaceable contact system disposed between the contact area and the semiconductor device and having a device contact site. 15. An apparatus used for testing individual semiconductor devices arranged on a wafer, comprising: a wafer main body; and a means connected to the wafer main body and in contact with the semiconductor device, wherein: A contact element including a contact element disposed at a position corresponding to an I / O pad; and an active component area including a circuit component disposed on the wafer body integrally with the wafer body, the contact element being located close to the contact means. Means provided on the wafer body for connecting the active component area and the remote test apparatus, wherein the wafer body is fixed to a rigid support member, and the rigid support member has an inclined area and a flat surface. Area, wherein said contact means is provided in said flat area, and said active component area is arranged in said inclined area. Ri, the inclined region is formed so as to prevent the said connecting means is in contact with the web Ha device. 16. The apparatus of claim 15, wherein said active component area comprises means for adjusting a test signal. 17. The device of claim 15, wherein the active component area comprises means for testing a semiconductor device.