JP3345381B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the miniaturization of electronic equipment, and more particularly to the construction of a micro computer optimal for space use.

[0002]

2. Description of the Related Art In recent years, many computers have been used for various purposes, and there has been a demand for smaller and lighter computers. In particular, computers used in space need to be further reduced in size and weight in order to reduce launch costs and increase payload (payload weight).

However, a space computer is disclosed in Document 1 (Goya et al., "Radiation-resistant 16-bit microprocessor LSI").
Development of the 32nd Space Science and Technology Union Lecture Meeting, pp.
As shown in Photo 1 of 10-411) and the like, it was composed of discrete (individual) parts in which a single chip having high reliability and environmental resistance was put in a single package. In addition, radiation resistance, especially bit inversion by cosmic rays (SEU: Single Event
In order to prevent the occurrence of Upset, the cell size must be larger than that for the ground. Since the chip size was originally large, the increase in the package size due to the increase in the number of pins did not cause much problem.

On the other hand, on the ground, a so-called multi-chip mounting technique for mounting a plurality of bare chips on one wiring board has been studied. Conventionally, FIG. 3 of Document 2 (Nikkei Microdevices, December 1989, pp. 32-40)
The wiring conductor connected to the bonding pad is drawn out of the die bonding pad as shown in FIG.

As for the fault-tolerant system, errors and failures are detected as described in Document 3 (Tsuchimura et al., "Trial Production and Evaluation of Fault-Tolerant Crystal Oscillation ICs", 24th FTC Study Group). 2. Description of the Related Art It is widely practiced to reduce the size of an inspection part and a part to be inspected by placing them on the same chip. In particular, ASIC (Application Specifie
With the spread of (dIC), A
Attempts have been made to add an MPU inspection circuit by SIC technology.

[0006]

Among the above-mentioned prior arts, the system composed of individual parts disclosed in Document 1 and the like does not take into account reduction in the size and weight of a computer.

[0007] In this regard, Japanese Patent Application No. 2-7022, already filed by the inventors, discloses an LSI having a small cell size by using a fault-tolerant technique.
That is, an environment-resistant computer using a highly integrated LSI is provided. Accordingly, the chip size of the space computer can be significantly reduced, and the increase in the package size due to the increase in the number of pins, which has not been a problem in the past, has become a way to reduce the size and weight of the space computer. PGA (Pin Grid Array), which can pull out many pins from a small package, is not suitable for use in space because visual inspection is difficult and mechanical stress generated by thermal expansion and contraction of pins cannot be released. With the increase in mind, other types of packages (QFP, DIP, etc.) must be used. The above points are problematic to some extent even on the ground. An object of the present invention is to eliminate an increase in package size due to an increase in the number of pins.

The method of drawing out the wiring conductor connected to the bonding pad outside the die bonding pad as in Document 2 does not take into account the equalization of the wiring density, and does not consider the wiring density in the outermost layer, especially in the vicinity of the die bonding pad. Is extremely high. For this reason, efficient wiring could not be performed, and the wiring density of the outermost layer became a path, and the package size could not be sufficiently reduced. In particular, in a multilayer wiring board, a via hole (Via Ho) connecting the upper and lower wiring layers
Since le) occupies a large area, many via holes occupy a large area in the outermost layer, especially around the die bonding pad. Another object of the present invention is to
It is an object of the present invention to reduce the concentration of wiring density on the outermost layer, especially around the die bonding pad, and to reduce the package size. Also, as described above, the via hole occupies a large area, so if there are many connection points with via holes between the wiring layers, the size of the wiring board required for wiring increases, and the package size accordingly increases. Become. Another object of the present invention is to reduce the number of connection points between wiring layers and to reduce the package size.

In the method of placing the inspection unit and the inspection target on the same chip as in Reference 3, the failure and the failure over the entire chip are not considered, and the inspection unit and the inspection target fail at the same time. In some cases, there is fear that an abnormality cannot be detected. One of the aspects of the present invention is to reduce the size and weight of an electronic device with an inspection function, which has less omission in detection of abnormality. Another object of the present invention is to provide an ultra-small electronic device in which program development is easy.

[0010]

In order to achieve the above object, the present invention takes the following measures.

<Elimination of Pin Neck> In order to eliminate an increase in package size due to an increase in the number of pins, according to the present invention, all semiconductor chips connected by bus lines are mounted on a wiring board with bare chips, and a wire is connected between the bare chip and the wiring board. Connected by bonding.

However, since the size of the wiring board is limited due to thermal stress and the like, in a wiring board of a size that can be manufactured at present, according to the conventional method, all the semiconductor chips connected by bus lines are bare chips on the wiring board. Impossible to implement. In order to mount many bare chips on a wiring board having a limited size, the following measures are taken. <Equalization of wiring density> In order to avoid concentration of wiring density near the die bonding land of the outermost layer of the multilayer wiring board, in the present invention, an insulating layer and a part are formed on the upper surface of the outermost wiring conductor,
By forming a die bonding land on the upper surface, a lead line from a wire bonding pad and a via hole are also formed below the die bonding land.

<Reduction of the number of via holes> In order to reduce the number of connection points between wiring layers, in the present invention, data signal lines constituting a data bus are divided into two groups, and one group of the wiring board is provided on one surface. The storage element connected to the signal line is mounted, and the storage element connected to the other group of signal lines is mounted on the other surface.

<Reduction of Detection Leakage> In order to realize an ultra-small electronic device with an inspection function with less detection omission of abnormality, in the present invention, the inspection section and the inspection target section are configured in different chips, and The chip is mounted on a wiring board with a bare chip, and the bare chip and the wiring board are connected by wire bonding.

<Easy Program Development> In order to facilitate program development, the present invention uses the RO
The signal line connected to the storage element such as M is also drawn out of the package, and the device for development is operated with the ROM connected outside the package without mounting the ROM in the package and wire bonding. After the program development is completed, the R
Operate with OM.

<Elimination of Pin Neck> In electronic equipment such as a computer, a plurality of semiconductor chips are usually connected by a bus composed of many signal lines. Therefore, in a conventional configuration using individual components, an enormous number of pins are required because the signal line connected to the bus connects the inside and outside of the package. In the present invention, since all the semiconductor chips connected to the bus are combined into a single package, the number of signal lines connecting the inside and outside of the package is greatly reduced.

<Equalization of Wiring Density> In the present invention, the die bonding lands are provided on the layer above (outside) the wire bonding pads. In this case, the area of the wire bonding pad portion can be used for drawing out the wiring from the wire bonding pad and forming a via hole in an inner layer, thereby alleviating the concentration of the wiring density near the wire bonding pad. be able to. Therefore, the wiring density of each wiring layer can be equalized, and the area can be used effectively.

<Reduction of the number of via holes> MPU (Microproc
The data line connected to the ESS unit has a 4, 8, 16, 32, or 64 bit width depending on the type of MPU. on the other hand,
ROM (Read Only Memory) and RAM (Random Access Me
The data lines connected to the storage elements such as mory) have a 1, 4 or 8 bit width depending on the type. That is, in many cases, the data width of the storage element is smaller than the data width of the MPU.
Therefore, as shown in FIG.
00 contains a plurality of RAMs 102-1 to 102-N and a ROM 103-1.
Storage elements such as to 103 to N are bit-sliced and connected.

According to the present invention, the data lines are divided into groups based on the widths connected to the storage elements, and the storage elements connected to the same group of data lines are mounted on the same surface of the wiring board, so that the wiring The size of the wiring substrate can be reduced in order to reduce the number of connections (via holes) between the layers and reduce the area occupied by the via holes.

<Reduction of Omission of Detection> Most of the failures of semiconductor elements occur on a transistor (gate) basis, but there are also failures in which the range of the failure extends to the entire element (chip). Such a failure that affects the entire chip is caused by an electronic device in which the inspected part and the inspection part are housed in the same chip.
It cannot be detected, and the significance of adding the inspection unit is diminished.

However, if the inspected portion and the inspected portion are formed of individual chips formed of individual packages, signal lines for inspection must be provided between the packages, which increases the size of electronic equipment. Would.

Therefore, in the present invention, the inspected part and the inspected part are divided into separate chips, mounted on the same wiring board with a bare chip, and the wiring board and the bare chip are connected by wire bonding to form a single package. As a result, it is possible to provide a small and lightweight electronic device that eliminates failure to detect a failure that affects the entire chip.

<Easy Program Development> A storage element (ROM) storing a program is mounted on the same wiring board as a semiconductor chip in the form of a bare chip, and if it is incorporated in the same package, the electronic equipment can be greatly reduced. Compact and lightweight.
However, if the ROM is incorporated in the package, a device is required for programming and erasing the program. EE
If a PROM (Electrically Erasable Programmable ROM) is used, it can be easily programmed and erased, and UVEPROM (Ultra-Violet Erasable Programmable ROM)
Even when an e-ROM is used, programming and erasing can be performed by providing a window for transmitting ultraviolet light for erasing in the package.

However, when an EPROM is used in a space electronic device exposed to cosmic rays or the like, data may be erased by the written cosmic rays. Also, since data written by the thermal motion of electrons is erased with time, EPROM cannot be used for electronic equipment used for a long period of decades. Therefore, a mask ROM or a fuse ROM must be used for these applications.

In order to develop a program, it is necessary to modify and rewrite the program many times, so that efficient program development cannot be performed using a mask ROM or a fuse ROM.

Therefore, according to the present invention, a mask ROM or a fuse ROM is built in a package,
The connection line to M is drawn out of the package, and operation is possible even with a ROM outside the package. Therefore, wire bonding is not performed on the ROM in the package for development, and if an EPROM that can be easily programmed and erased is connected to the outside, the program can be programmed using the same wiring pattern as the production one. Can be developed.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the internal configuration of an electronic device provided by the present invention. In this embodiment, the MPU 101, the RAM 102, the ROM 1
03, FPU (Floating-point Proccessing Unit) 10
4, DMAC (Direct Memory Access Controller) 10
5, The interface circuit 106 is a wiring board (package)
10 are connected by a bus 100. In this embodiment, it should be noted that the bus 100 is not drawn out of the wiring board (package) 10 and only the interface line 150 with the outside is connected to the wiring board (package) 1.
It is a point that is drawn out of 0. Conventionally, a bus 1 is provided outside a wiring board (package) 10 as shown in FIG.
Since the number of pins was increased, the size of the package was increased with an increase in the number of pins. However, in this embodiment, all the semiconductor chips connected to the bus 100 are mounted on the wiring board (package) 10. According to the present embodiment, the bus 100 is provided outside the wiring board (package) 10.
Are not drawn out, so that the number of signal lines connecting inside and outside can be greatly reduced. Therefore, the number of pins connecting signal lines inside and outside the wiring board (package) 10 can be reduced, and the number of pins does not prevent the wiring board (package) 10 from being reduced in size and weight.

FIG. 2 is a sectional view of a die bonding portion of a wiring board according to the present invention. An insulating layer 16 is partially formed on the outside (upper) of the wire bonding pad 11 and the wiring conductor 14 drawn out from the wiring board 10, and the die bonding land 1 is formed on the outer (upper) of the insulating layer 16.
5 is formed, and the semiconductor chip 20 is die-bonded,
The bonding wires 30 are connected between the wire bonding pads 21 on the semiconductor chip 20 and the wire bonding pads 11 on the wiring board 10. According to the present embodiment, as shown in FIG. 3, not only the via hole 13 around the die bonding land 15 but also the via hole 13 'can be formed inside the die bonding land 15. Therefore, according to the present embodiment, the portion under the outermost layer die bonding land 15 which has not been conventionally used can also be used as a wiring region or a via hole region, and the wiring compared with the area occupied by the semiconductor chip in the wiring substrate is reduced. And the area occupied by the via hole region can be significantly reduced.

FIG. 4 shows a data bus 100 connected to the MPU 101.
Are divided into two groups of 100-1 and 100-2 for each bit and connected to the data bus 100-1.
RAM 102-1 to 102-k and ROM 103-1 to 103-k are B
The RAM 102- (k +) connected to the data bus 100-2
This is an embodiment in which 1) to 102-N and ROM 103- (k + 1) to 103-N are mounted on the A surface. According to the present embodiment, the connection of the data bus between the side A and the side B is unnecessary, and the number of bare holes occupying a large area can be reduced. Therefore, the area occupied by the wiring and the via hole area can be significantly reduced as compared with the area occupied by the semiconductor chip on the wiring board,
Electronic devices can be reduced in size and weight.

FIG. 5 shows the MPU 101 in the embodiment shown in FIG.
Is 32 bits wide, and the RO
This is an embodiment in the case where the data bus connected to M and RAM has an 8-bit width. Of the data lines D0 to D31 constituting the data bus 100, D0 to D15 are connected to the data bus 100.
-1 and D16 to D31 are grouped into the data bus 100-2. D0 of the data bus 100-1
To D7 are connected to the RAM 102-1 and the ROM 103-1 and D8 to D
15 is connected to the RAM 102-2 and the ROM 103-2. Also, D15 to D23 of the data bus 100-2 are connected to the RAM 102.
-3 and the ROM 103-3, and connect D24 to D31 to the RAM 102.
-4 and ROM 103-4. According to this embodiment, it is possible to reduce the size and weight of the electronic device as in the embodiment shown in FIG.

FIG. 6 shows an embodiment in which the MPU 101 and the inspection circuit 111 of the MPU 101 are mounted on a wiring board 10 with a bare chip. MP
U101 and inspection circuit 111 are separate bare chips, respectively.
It is connected to the wiring board 10 by wire bonding. For simplicity, the bonding wires are omitted in the figure. Various methods have been conventionally proposed for the inspection circuit 111.

For example, (1) when there is no access from the MPU 101 within a certain period
A watchdog timer that resets the MPU101 as if it were a runaway of the MPU101.

(2) MPU for reference inside inspection circuit 111
(Not shown in the figure), the output signal of the reference MPU is compared with the output signal of the MPU 101, and when a mismatch is found, the reference MPU or the MPU 101 is regarded as abnormal.

And the like.

In the conventional method in which the MPU 101 and the inspection circuit 111 are provided in separate packages, the number of packages and the number of wirings increase, and the size of the electronic device increases. In addition, in the method adopted recently, in which the MPU 101 and the test circuit 111 are on the same chip, if a failure occurs on the entire chip, the test circuit 111 also stops functioning. Can not.

According to this embodiment, it is possible to provide the MPU 101 with the inspection circuit 111 that can detect a failure over the entire chip without increasing the number of packages and the number of wirings. Therefore, a small, lightweight, and highly reliable electronic device can be provided.

FIG. 7 shows an embodiment in which the RAM 102 and the error correction code encoding / decoding circuit 112 are provided as separate chips, and are mounted on the wiring board 10 with bare chips. The RAM 102 and the error correction code encoding / decoding circuit 112 are separate bare chips, and are connected to the wiring board 10 by wire bonding. For simplicity, the bonding wires are omitted in the figure.

The error correction code enables detection and correction of errors by adding redundant bits for error detection and correction to data stored in the memory and making the Hamming distance between the codes four or more. When the Hamming distance between codes is 4, a 1-bit error can be corrected, and a 2-bit error can only be detected. Therefore, SECDED (Single-ErrorCrrectio
n, Double-Error Detection) code. For example, in order to realize SECDED for 16-bit data, 6-bit redundant bits for detection and correction may be added. Since the object of the present invention is not to provide an error correction code, a detailed description of the error correction code will be omitted.

In the conventional method in which the RAM 102 and the error correction code encoding / decoding circuit 112 are packaged separately, the number of packages and the number of wirings increase, and the size of the electronic device becomes large. Further, in a method adopted recently, in which the RAM 102 and the error correction code encoding / decoding circuit 112 are on the same chip, when a failure occurs over the entire chip, the error correction code encoding / decoding circuit 112 also functions. Therefore, the failure cannot be completely detected.

According to the present embodiment, the error correction coding / decoding circuit 112 can detect a failure over the entire chip without increasing the number of packages and the number of wirings.
Attached RAM 102 can be provided. Therefore, a small, lightweight, and highly reliable electronic device can be provided.

FIG. 8 shows an embodiment in which both the ROM inside the wiring board (package) 10 and the ROM connected outside can be operated. Inside the wiring board (package) 10, the RAM 102 and the ROM 103 are connected to the MPU 101 and the bus 100. In addition, the RAM 102, RO
An M103 selection signal CS # has been generated. In the figure, active-low signals are marked with a line above the signal line name,
In this specification, for convenience of description, a signal line name is described with a "#" symbol. Address decoder 107 is connected to bus 1
The high-order bits of the address signal output to 00 are decoded, and when the address signal indicates the address of the RAM 102 or the ROM 103, the respective selection signals CS # are output to the RAM 102 or the ROM 103. RAM102 or ROM1
In 03, when the selection signal CS # is active, data at a predetermined address is read or written according to the lower bits.

In this embodiment, the selection signal CS # 1 of the ROM 103
08 is also output to the outside of the wiring board (package) 10. Therefore, the ROM 103 in the wiring board (package) 10
Instead of the ROM 10 outside the wiring board (package) 10
It is possible to work with 3 '. Also, ROM10
Since the address line connected to 3 'is sufficient for the lower bits which are a part of the signal of the address bus, an increase in the number of lead lines to the outside of the wiring board (package) 10 can be suppressed. In order to develop the program, the wiring board (package) 10
Since the program may be written in the ROM 103 'outside the wiring board (package) 10 without mounting the ROM 103, the program can be easily written to and erased from the ROM, and efficient program development can be performed. In addition, after the program is developed, the ROM 103 in the wiring board (package) 10
If a mask ROM or fuse ROM is used as
An electronic device that can withstand long-term use without fear of erasing data in the M103 can be provided.

FIG. 9 shows an example of a circuit according to an embodiment of the present invention. MPU 101, RAM 102, ROM 103, FPU 10
4. The DMAC 105 and the gate array 110 are mounted on a bare chip. The RAM 102 and the ROM 103 are composed of a plurality of chips according to the memory capacity and the bit width, but are collectively represented as one in the figure for simplicity. Gate array 1
10, an inspection circuit 111 including a watchdog timer for detecting runaway of the MPU, an error correction code encoding / decoding circuit 112 for correcting data inversion of the RAM 102, an address decoder 107, and an external interface circuit 10
6 are built in. (These circuits inside the gate array 110 are not shown.) By forming the peripheral circuits of the MPU 101 into a gate array, the number of chips can be significantly reduced.

Further, since the inspection circuit 111 and the error correction code encoding / decoding circuit 112 are housed in the gate array 110 which is a separate chip from the MPU 101 and the RAM 102, respectively, it is possible to detect a failure over the entire chip. Can be prevented.

The MPU 101, FPU 104 and DMAC 105 can be of various types, but here, GMICRO / 2
The illustration is based on the use of the 00 (H32 / 200) series. Therefore, the names of various control signal lines are GMICRO /
It is shown according to the specifications of the 200 (H32 / 200) series. Since the present invention is not embodied only by a specific product series, a description of signal names not particularly related to the present invention will be omitted.
/ 200 Hardware Manual ", Hitachi, Ltd.)
And so on. Since the bit positions of the address and data lines are displayed in big endian,
The upper bits are represented by smaller numbers. For example, A0 of the address line represents the most significant bit, and A29 represents the least significant bit.

In this embodiment, the bus signal lines led out of the wiring board (package) 10 are the address lines A13 to A13.
A29, data lines D0 to D31, address strobe AS
1 #, AS2 #, byte control signals BC0 # -B
Only C2 #, read / write switching signal R / W #, and data transfer end signal DC #. Therefore, since only a part of the bus signal line is drawn out of the wiring board (package) 10, the number of pins attached to the outside of the package can be reduced, and the package size can be reduced. Furthermore, if a ROM or the like outside the wiring board (package) 10 is not used, it is not necessary to draw out these bus signal lines at all, and the number of pins can be greatly reduced.

An address decoder 107 (not shown) in the gate array 110 has a ROM selection signal ROCS # 108 and a RAM selection signal RACE0 based on the address lines A0 to A12.
# To RACE3 # and an external element selection signal XCS #.

Of these signal lines, the ROM selection signal RO
CS # 108 is ROM1 inside the wiring board (package) 10.
03 and wiring board (package) 10
Has been pulled out to the outside. According to the present embodiment, it is possible to operate by connecting a ROM 103 ′ (not shown) outside the wiring board (package) 10 instead of the ROM 103 in the wiring board (package) 10. Also, since the address lines connected to the ROM 103 'need only be lower bits A13 to A29, which are part of the address bus signal, an increase in the number of lead lines to the outside of the wiring board (package) 10 can be suppressed. Wiring board (package) for program development
Wiring board (package) without mounting ROM103 in 10
Since the program only needs to be written in the ROM 103 'outside the ROM 10, the program can be easily written to and erased from the ROM, and efficient program development is possible. In addition, if a mask ROM or a fuse ROM is used as the ROM 103 in the wiring board (package) 10 in the actual device after the program development, there is no fear of erasing the data in the ROM 103, and an electronic device that can be used for a long time is provided. can do. RA
RACE among M selection signals RACE0 # to RACE3 #
0 # to RACE1 # are the RAM inside the wiring board (package) 10.
RACE2 # to RACE3 # are connected to the outside of the wiring board (package) 10. According to the present embodiment, RACE2 # to RACE3 #, byte control signals BC0 # to BC2 #, and read / write switching signal R / W drawn out of the wiring board (package) 10.
#, Address lines A13 to A29, and data lines D0 to
D31 outside the wiring board (package) 10 not shown
If connected to the RAM 102 ', the storage capacity can be increased by adding the RAM 102' to the RAM 102.

The external element selection signal XCS # is led out of the wiring board (package) 10, and is supplied to external elements (not shown) such as the external element selection signal XCS #, byte control signals BC0 # to BC2 #, and read / write switching signal R / W #, address strobes AS1 #, AS2 #, data transfer end signal DC #, address lines A13 to A29,
If the data lines D0 to D31 are connected, external elements can be used, and the expandability of the system can be improved.

RAM outside wiring board (package) 10
102 ', RAM selection signals RACE2 # to RACE3 # when no external element is connected, external element selection signal XC
S #, byte control signals BC0 # to BC2 #, read / write switching signal R / W #, address strobes AS1 #, AS2 #, data transfer end signal DC #, address lines A13 to A29, and data lines D0 to D31 Since it is not necessary to pull out to the outside of the substrate (package) 10, the number of pins can be significantly reduced. In addition, the gate interface 110 can also incorporate an external interface circuit 106. Signal line MIL
-1553B is a signal line for communication of a communication standard called MIL-1553B. Also, the signal line CELLCOMC
NTR is a communication path connecting a plurality of computer units each including a wiring board (package) 10. Prepare the required number of wiring boards (packages) 10 and connect the communication lines CELLCOMCNTR.
If they are connected to each other, a multiprocessor system or a multiplexed computer system for fault tolerance can be easily constructed.

FIGS. 10 and 11 show a method of mounting on the wiring board 10 of the embodiment of FIG. 9 according to the present invention. On the surface shown in FIG. 10, the MPU 101, FPU 104, ROM 103-1, 103-2, RAM 102-
1, 102-2 are mounted. On this surface, as shown in FIG. 5, storage elements connected to data lines belonging to the bus 100-1, ROMs 103-1 and 103-2, and RAMs 102-1 and 102-
2 is mounted.

FIG. 11 shows the DMAC 105 and the gate array 11.
0, ROM 103-3, 103-4, RAM 102-3, 102-4
Is installed. On this surface, as shown in FIG.
A storage element connected to the data line belonging to 00-2;
3, 103-4 and RAMs 102-3 and 102-4. According to the present embodiment, the number of via holes between the wiring layers can be reduced, so that the size of the wiring board 10 can be reduced. LSI, MPU101, FPU104, DMAC105 with large chip size and large number of input / output signal lines
By dividing the gate array 110 on both sides, heat generation and concentration of wiring on one side can be avoided. For applications requiring reliability, such as space applications, a ceramic substrate is suitable for the wiring substrate 10 in terms of thermal resistance, chemical stability, and the like.

FIG. 12 shows an embodiment of the package according to the present invention. A ceramic cap 50 is attached to both sides of a ceramic wiring board 10 having bare chips such as the MPU 101 mounted on both sides, and hermetically sealed. Hermetically sealed cap 50
Is filled with a vacuum or an inert gas such as nitrogen or helium. In particular, when helium is sealed, it can also be used as a leak checker when checking the airtightness of the sealed portion. When a plurality of chips are packed in a single package as in the present invention, the size of the package becomes large, and
The volume of gas inside 0 also increases. Therefore, the ceramic caps 50 are provided on both sides of the ceramic wiring board 10.
In the case where airtight sealing is performed by adding solder, the molten solder is drawn into the cap 50 or jumps out due to the pressure difference between the inside and outside during cooling after soldering. For this purpose, a vent hole 51 is opened in the cap 50, air-tightly sealed, an inert gas is sealed, and then the vent hole 51 is closed with a lid 52 or the like. Even in a large package, the molten solder is drawn into the cap 50. Or jumping out.

[0055]

According to the present invention, a plurality of semiconductor elements can be mounted in a single package, and the number of signal lines extending from the package to the outside can be reduced, so that the size of the package can be reduced. Thus, a small and lightweight electronic device can be realized.

[Brief description of the drawings]

FIG. 1 is a system configuration.

FIG. 2 is a sectional view of the present invention.

FIG. 3 shows the arrangement of via holes.

FIG. 4 shows division of bits of a data bus.

FIG. 5 shows division of bits of a data bus.

FIG. 6 is an MPU with an inspection function.

FIG. 7 is a RAM with an error correction code.

FIG. 8 is an external ROM.

FIG. 9 is a circuit diagram of the present invention.

FIG. 10 shows mounting of a semiconductor chip on a wiring board.

FIG. 11 shows mounting of a semiconductor chip on a wiring board.

FIG. 12 is a cross section of a package.

FIG. 13 shows a conventional method.

FIG. 14 shows a conventional method.

DESCRIPTION OF SYMBOLS 10: wiring board, 11: wire bonding pad on wiring board, 13: via hole, 15: die bonding land, 20: semiconductor chip, 21: wire bonding pad on semiconductor chip, 30: bonding wire, 100 bus, 101 MPU, 102 RAM,
103 ROM.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisayoshi Yamanaka 1500 Ogawa Ogawa, Shimodate City, Ibaraki Prefecture Inside the Shimodate Plant, Hitachi Chemical Co., Ltd. Hitachi Chemical Co., Ltd. Ishigami Plant (72) Inventor Koichi Ihara 4-6-6 Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd. (72) Masanori Akiyama 4-6-6 Kanda Surugadai, Chiyoda-ku, Tokyo Stock (56) References JP-A-2-289014 (JP, A) JP-A-1-220498 (JP, A) JP-A-1-258466 (JP, A) Jpn. , U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/18 G06F 12/06 H01L 25/18-25/07

Claims (10)

(57) [Claims] An arithmetic unit, a plurality of memory modules, and data between the arithmetic unit and the plurality of memory modules.
Data is sent to the plurality of first data lines and the plurality of second data lines.
A data line having over data lines, on the basis of the signal sent from the arithmetic unit have a selection circuit for outputting a selection signal for selecting a plurality of said memory modules, the memory modules of the plurality first Data line
Includes a plurality of first memory located on one side of the connected substrate and the plurality of second plurality of second disposed on the other surface of the connected board to the data lines of the memory, From the first memory via the plurality of first data lines
Data of the upper bits Te is the double of the second memory
An information processing device to which lower-order bit data is output via a number of second data lines . 2. The information processing apparatus according to claim 1, wherein said first and second memories are RAMs. 3. The information processing device according to claim 1, wherein the selection circuit inputs an address signal output from the arithmetic device and outputs a selection signal based on the input address signal. 4. An arithmetic unit for outputting n-bit (n is an integer) data, and n-bit data can be sent from the arithmetic unit, and a plurality of first
Data line having one data line and a plurality of second data lines
And one of the surfaces of the substrate connected to the plurality of first data lines.
A plurality of first memories arranged and the plurality of second memories ;
And a plurality of second memory located on the other surface of the substrate is connected to the over data lines, wherein the plurality of first memory stores m-bit data (m is an integer), said plurality of the second memory is an information processing apparatus having a memory module for storing the (n-m) bit data. 5. The information processing apparatus according to claim 4, wherein said first and second memories are RAMs. 6. An arithmetic unit for outputting data of n bits (n is an integer) , connected to the arithmetic unit and having a data width of n bits,
It has a plurality of first data lines and a plurality of second data lines
And the data lines, the one surface of the substrate being connected to said plurality of first data lines
A plurality of first memories arranged and the plurality of second memories ;
A plurality of second memories connected to the data lines and arranged on the other surface of the substrate , wherein the plurality of first memories have m bits.
And the second memories store (n-
and a memory module for storing data of m) bits, a plurality of the first on the basis of a signal output from the arithmetic unit, an information processing apparatus having a selection circuit for selecting a memory for writing data from the second memory. 7. The information processing apparatus according to claim 6, before Symbol first, second data writing and reading an information processing apparatus, respectively in bytes of memory. [8 claims] and arithmetic unit, connected to the computing device, data of n bits (n is an integer)
Has a data width, the second data where the first data <br/> line data of m bits are sent, the (n-m) bit data are sent
A data line and a data line, a pre-Symbol first plurality of first arranged on one side of the connected substrate and data lines of the memory and the second memory, the second
The information processing apparatus having a memory module, the having a data line and connected to the other third of the plurality disposed on a surface of the memory and the fourth memory of the substrate. 9. An arithmetic unit for outputting n-bit (n is an integer) data and address; a first data line to which m-bit data is sent; and a second data line to which (n-m) -bit data is sent . and the data lines, before Symbol first plurality of first arranged on one side of the connected substrate and data lines of the memory and the second memory, the second
A memory module having a plurality of third memories and a fourth memory connected to the data lines of the first and second substrates and arranged on the other surface of the substrate; and a plurality of the first modules based on an address output from the arithmetic unit. A selection circuit that selects one of a memory and a plurality of the third memories or a plurality of the second memories and a plurality of the fourth memories; and n-bit data between the arithmetic unit and the memory module. the information processing apparatus having a third data lines sent. 10. The information processing device according to claim 9, wherein the selection circuit is configured to select one of the plurality of first, second, third, and fourth memories based on an address signal output from the arithmetic device. An information processing device for selecting one memory.