JP3348496B2 - Method of forming wiring structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring structure and a method for forming the same. The present invention can be used, for example, for wiring of various electronic materials.

[0002]

2. Description of the Related Art In the field of using a wiring structure, miniaturization and integration are progressing. For example, in the field of semiconductor devices, with the miniaturization of elements, the wiring has also been miniaturized, and the reliability of the wiring has increased. As the device operates at higher speeds and becomes more highly integrated, the current density flowing through the fine wiring increases, and it is particularly necessary to ensure resistance to electromigration. Most of the current wiring materials are Al-Si-C
Although an Al-based alloy such as u is used, sufficient electromigration resistance is not obtained in fine wiring.

The causes are as follows. For example, in a 0.3 μm-level fine wiring, an upper insulating film is put on the wiring in a device manufacturing process after the wiring is formed, and various temperatures are applied to the wiring, so that the Al wiring is affected by thermal stress of the upper insulating film and the like. Voids can occur. In this state, since a high current is applied to an actual device, current concentrates in the wiring void portion, and as a result, there is a problem in that reliability is reduced in a combined mode of stress migration and electromigration that leads to disconnection. Therefore, in the case of the conventional technology, the limit is beginning to be seen in the case of the Al-based alloy as a wiring material in fine device wiring.

In particular, with the increase in the degree of integration of elements, the width of wiring and the thickness of wiring to be formed have also been reduced.

As a conventional technique using an Al-based alloy as a wiring material, a MOS LSI process will be described below as an example. Conventionally, the following steps (a) and (b) are performed. (A) A MOS transistor is formed by forming element isolation, a gate wiring, and a source / drain region. (C) Blk-W (blanket tungsten) or the like is buried in the connection hole, and an Al-based alloy such as Al-Si-Cu is formed thereon and patterned to form a wiring region.

In the prior art, an element is formed by, for example, the above process example. To simply enhance the electromigration resistance, if the formed Al is made to have a large crystal grain size, the electromigration resistance is thereby improved. . However, with the increase in the degree of integration of elements, the thickness of the wiring to be formed has been reduced as the wiring width has been reduced. Crystal growth greatly depends on the film thickness. For example, when the device rule is a 0.8 μm rule, A
The film thickness is about 0.8 μm and the crystal grain size is 1-2 μm
The device rule is 0.25μ
In the m-th generation, the thickness of the Al film to be formed is also reduced to about 0.3 μm, and therefore, there is a problem that the crystal grain size of Al becomes a small grain size of 0.5 μm or less. This indicates that the crystal grain size does not grow extremely larger than the thickness of the formed film. For this reason, the current density increases with the miniaturization of the element, but the Al crystal grain size in the wiring portion decreases, and as a result,
More severe electromigration.

In order to improve the reliability of wiring in the above devices, a new wiring material has been proposed to replace the Al-based alloy.
For example, Cu wiring has attracted attention. This is because the resistivity of Cu is 1.72 μm from the resistivity of Al (2.47 μΩcm).
Although it is as low as Ωcm and has strong electromigration resistance, it has problems such as Cu workability by dry etching and cannot be applied practically.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a wiring having high electromigration resistance, for example, even when using a wiring material such as Al. , And a method for forming such a wiring structure.

[0009]

[Means for achieving the purpose]

According to the first aspect of the present invention, (a) a MOS transistor is provided on a substrate.
Forming a transistor, and (b) forming an interlayer film to form the interlayer film.
And (c) a blanket W is formed in the connection hole.
Is formed as an embedded wiring material, and (d) a wiring material
Each step of forming the material layer by Al or Al alloy
The wiring material layer is formed of Al
Or in the step of forming the Al alloy, the Al or Al alloy wiring layer to be formed under pressure of 200 atmospheres pressure below than 100 atm under a temperature below the melting point in an inert gas atmosphere to form a wiring material layer By completely burying in the trench deeper than the width of the wiring, and removing the wiring material in a region other than the trench by polishing or dry etching , the crystal grain size of the wiring layer is reduced.
A method for forming a wiring structure, characterized in that the wiring structure is formed to have a thickness equal to or greater than the thickness, and the above object is achieved by this configuration.

In the present invention, Al or Al is mainly used.
Alloy at a low temperature of 400 ° C or lower.
Then, reflow at a temperature of 400 ° C. or more to
It can be implemented to form structures.

According to a second aspect of the present invention, (a) a MOS transistor is provided on the substrate.
Forming a transistor, and (b) forming an interlayer film to form the interlayer film.
And (c) a blanket W is formed in the connection hole.
Is formed as an embedded wiring material, and (d) a wiring material
Each step of forming the material layer by Al or Al alloy
The wiring material layer is formed of Al
Alternatively, in the step of forming an Al alloy, an Al or Al alloy film to be formed as the wiring material layer is completely embedded in a groove deeper than the wiring width of the wiring layer to be formed, and the wiring material is subjected to a pressure of 200 atm. At 150 ° C to 30
After the heat treatment at 0 ° C., the wiring material in the region other than the groove is removed by polishing or dry etching, so that the crystal grain size of the wiring layer is formed to be equal to or larger than the film thickness of the wiring layer. This is a method for forming a wiring structure, which achieves the above object by this configuration.

According to a third aspect of the present invention, there is provided (a) a MOS transistor on a substrate.
Forming a transistor, and (b) forming an interlayer film to form the interlayer film.
And (c) a blanket W is formed in the connection hole.
Is formed as an embedded wiring material, and (d) a wiring material
Each step of forming the material layer by Al or Al alloy
The wiring material layer is formed of Al
Or in the step of forming the Al alloy, the Al or Al alloy wiring layer to be formed under pressure of 200 atmospheres pressure below than 100 atm under a temperature below the melting point in an inert gas atmosphere to form a wiring material layer Completely embedded in the trench deeper than the wiring width of
After heat treatment at 150 ° C. to 300 ° C. under atmospheric pressure, the wiring material in the area other than the groove is polished or dry.
Etching to remove the wiring layer
A method for forming a wiring structure, characterized in that the crystal grain size is formed to be equal to or larger than the film thickness of the wiring layer, and the above object is achieved by this configuration.

[0014]

The above etch back is preferably performed by heat treatment.
After, more preferably, after heat treatment at 400 ° C. or higher.
good.

According to the present invention, the thickness direction and the width direction of the wiring are
Crystal growth takes place in any direction
Progresses effectively.

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

According to the present invention, a wiring material layer is formed so as to be thicker than a wiring layer to be formed or wider than a wiring layer to be formed. Since a deep groove is formed and buried, a crystal grain size larger than a predetermined film thickness or width of a wiring layer to be formed can be obtained by growing the crystal here.
For example, FIG. 9 shows an example of an Al-Si alloy,
As shown here, in the case of the conventional wiring structure II, the crystal grain size becomes smaller as the wiring film thickness becomes smaller, and the MTT
Although F becomes small and electromigration resistance becomes small, in the wiring structure I using the method of the present invention,
When a wiring layer having a thickness of 1.0 μm is formed, it is almost 2 to 3 μm
Crystals with a (maximum) particle size grow and the MTTF hardly changes. Therefore, a wiring having high electromigration resistance can be obtained.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. However, needless to say, the invention of the present application is not limited to the embodiments described below.

Embodiment 1 In this embodiment, a wiring is formed in a fine wiring device so that Al has a large crystal grain size. In other words, in order to solve the problem that the crystal grain size grows only about the film thickness, a film thickness larger than the wiring width is formed in advance, and the crystal size is set to a grain size about the film thickness. In other words, by obtaining a crystal grain size equal to or larger than the wiring width, by forming the wiring into a bamboo structure,
The electromigration resistance is enhanced.

In the first embodiment, as a means for increasing the grain size, when the wiring width is 0.5 μm, an Al film having a thickness larger than the width, for example, about 5 μm, is formed and sintering is performed. Thereafter, the entire surface is polished to a thickness of about 0.5 μm to form a large-grain Al wiring.

In the present embodiment, the present invention is particularly applied to a MOS device process.

The wiring structure obtained by this embodiment is shown in FIG.
As shown in FIG. 1, in a wiring structure made of Al, which is a wiring material showing a crystal structure, a wiring layer 11 to be formed is formed.
Thicker than T ₂ of the, after the formation of the wiring material layer 11a, (see arrow 12) by processing the wiring layer of a predetermined thickness T _1, the wiring layer 11 crystal grain size of the film thickness or more It is formed in size.

In this embodiment, the following (a) to (d)
By the above process, the wiring structure of the MOS device was formed.

(A) On a substrate 1 (Si substrate) 1, an element isolation region 2, an insulating film 6 (SiO ₂ ) and a gate material 4 (poly S
A gate region composed of i) is formed, and after forming the side wall 5, ion implantation for forming the source / drain 3 is performed to form a MOS transistor. Thus, the structure shown in FIG. 2 is obtained.

(B) After forming the MOSFET structure, an interlayer film 7 (SiO ₂ ) is formed. The film was formed under the following conditions. Conditions Gas TEOS = 50 sccm Temperature 720 ° C. Pressure 40 Pa Film thickness 600 nm

Next, resist patterning was performed, and connection holes 7a were formed by dry etching to obtain the structure shown in FIG. The etching conditions were as follows. Dry etching conditions Gas C ₄ F ₈ = 50 sccm RF power 1200 W Pressure 2 Pa

(C) A buried wiring material in the connection hole 7a is formed. Here, the burying in the connection hole 7a was performed using the blanket W as the burying wiring material 9.
First, TiN / Ti was formed as the W adhesion layer 8 under the following conditions. Conditions Ti formation conditions Power 4 kW Film formation temperature 150 ° C. Gas Ar = 1000 sccm Film thickness 30 nm pressure 0.47 Pa TiN formation conditions Power 5 kW Gas Ar / N ₂ = 40/70 sccm Film thickness 70 nm Pressure 0.47 Pa

Next, a blanket W was formed under the following conditions. W formation conditions Gas Ar / N ₂ / H ₂ / WF ₆ = 2200
/ 300/500 / 75sccm temperature 450 ° C pressure 10640Pa

[0044] Ri by a W, which is the embedded wiring material 9 to be etched back, and the structure of FIG. 4. The etch-back conditions are as follows. Conditions Gas SF ₆ = 50 sccm RF power 150 W Pressure 1.33 Pa Film formation temperature 350 ° C.

(D) The wiring image 11 is formed. Here, an Al / Ti wiring was formed as follows. The Ti film as the barrier layer 10 can be formed under the following conditions. Ti film forming conditions Power 4 kW Film forming temperature 150 ° C. Gas Ar = 100 sccm Film thickness 30 nm Pressure 0.47 Pa

Further, an Al film is formed as the wiring material layer 11a. This can be formed under the following conditions. Continued
Cu is polished by a polishing method so as to remain only in the groove 10. Thus, the structure shown in FIG. 7 was obtained. The polishing conditions were as follows. Al film forming conditions Power 22.5 kW Film forming temperature 150 ° C. Gas Ar = 40 sccm Film thickness 5 μm Pressure 0.47 Pa

Next, in this embodiment, as schematically shown by an arrow 12, the entire surface is polished, and the wiring material layer 1 is polished.
Only the Al film 1a is thinned by mechanical chemical polishing under the following conditions. Conditions The polishing apparatus shown in FIG. 5 was used. Number of rotations of the polishing plate 60 37 rpm Number of rotations of the wafer holding sample 64 17 rpm Polishing pressure 5.5E8 Pa Working solution: hydrogen peroxide (1 wt%) + amine (1 wt%) + H ₂
O solution at a flow rate of 225 ml / min. Temperature of pad 67: 40 ° C

Thereafter, an Al / Ti wiring layer is formed by resist patterning and dry etching under the following conditions. Condition Gas BCl ₃ / Cl ₂ = 60 / 90s
ccm Microwave power 1000W RF power 50W Pressure 0.016Pa

In FIG. 5, reference numeral 61 denotes a supply port of the mechanical polishing liquid, 62 denotes a schematic view of the mechanical polishing liquid, 63 denotes a rotating shaft of the polishing plate 60, and 65 denotes a mechanical polishing liquid.
Denotes a rotation axis of the wafer holding sample stage 64 that supports the substrate wafer 68 to be polished, and 66 denotes pressure.

In this embodiment, the wiring forming material layer 11a
Since (Al) was formed to be thicker, especially thicker than the wiring width, even if the wiring to be formed became thinner, the crystal grain size was always larger than the wiring width, and the wiring maintained a bamboo structure. Therefore, the electromigration resistance increases.

Example 2 In this example, the same steps as in Example 1 were performed for FIGS. 2 to 4, and the entire surface was etched instead of the mechanical polishing in step (d). By this overall etching, the wiring material layer 11a is thinned to obtain a structure similar to that of FIG.

Embodiment 3 In this embodiment, when the wiring width to be formed is 0.5 μm, a groove deeper than that, particularly a groove of 1 μm or more is formed in advance. Al is buried therein by high-temperature sputtering or Al reflow to form a wiring material layer. The wiring material (Al film) other than the grooves was removed by metal polish.

Reference is now made to FIG. 6 and FIG. In this embodiment, the condition is changed only in the step (d) of the first embodiment. Step (d) of this example is as follows.
(D) The interlayer film 71 is formed under the following conditions. Condition Gas TEOS = 50 sccm Temperature 720 ° C. Pressure 0.016 Pa Film thickness 2 μm

Thereafter, a groove 14 is formed by resist patterning and dry etching (groove 1 having a depth of 2 μm).
4).

Further, the groove 14 is filled with T as an underlayer 10b.
After i film formation, Al as a wiring material is embedded by high-temperature sputtering. The embedded Al wiring layer is indicated by reference numeral 13b. Thereby, an Al / Ti wiring is formed.

Ti film forming conditions Power 4 kW Film forming temperature 150 ° C. Gas Ar = 100 sccm Film thickness 30 nm Pressure 0.47 Pa

Further, an Al film is formed. Al film formation conditions Power 22.5 kW Film formation temperature 500 ° C. Gas Ar = 40 sccm Film thickness 5 μm Pressure 0.47 Pa In the case of Al reflow, Al is subjected to heat treatment at about 150 ° C. to perform reflow.

Next, the entire surface is polished, and only the Al film which is the wiring material layer is subjected to mechanical chemical polishing. Conditions The polishing apparatus shown in FIG. 5 was used. Number of rotations of the polishing plate 60 37 rpm Number of rotations of the wafer holding sample 64 17 rpm Polishing pressure 5.5E8 Pa Working solution: hydrogen peroxide (1 wt%) + amine (1 wt%) + H ₂
O solution at a flow rate of 225 ml / min. Temperature of pad 67: 40 ° C

Thereafter, an Al / Ti wiring layer is formed by resist patterning and dry etching. Condition Gas BCl ₃ / Cl ₂ = 60 / 90s
ccm Microwave power 1000W RF power 50W Pressure 0.016Pa

In this embodiment, the wiring layers 13a and 13b are formed so that the wiring thickness d is larger than the wiring width W, as shown in FIG.
For this reason, the crystal growth is increased, the bamboo structure of the wiring material is realized, and a wiring with good electromigration resistance can be obtained.

That is, in the prior art, as schematically shown in FIG. 8, since the thickness d of the wiring 15 is smaller than the wiring width W, the wiring has a fine crystal grain size and the electromigration resistance has not been improved. In this embodiment, the particle size can be increased as described above, and the resistance can be improved.

In this embodiment, in particular, since the embedded wiring technique is used, even if the thickness of the Al wiring is increased, complete flattening is possible.

Embodiment 4 In this embodiment, the conditions are changed only in the step (d) of the embodiment 1.

In this embodiment, the thin film Al to be formed is 100
Film formation is performed under a pressure higher than the atmospheric pressure. Alternatively, after forming the Al film, high pressure is applied while applying a temperature of about 400 ° C. Under high pressure, the Al deposition temperature is 150 ° C to 300 ° C
At the level, the Al atoms are easy to move and try to approach a shape closer to a more stable single crystal, and as a result, even the thin film Al has a large grain size.

Step (d) of the present embodiment is as follows. (D) Al / Ti wiring is formed. Ti film forming conditions Power 4 kW Film forming temperature 150 ° C. Gas Ar = 100 sccm Film thickness 30 nm Pressure 0.47 Pa

Further, Al is formed as a wiring material layer. Al film forming conditions Power 22.5 kW Film forming temperature 150 ° C. Gas Ar = 40 sccm Film thickness 5 μm Pressure 0.47 Pa

In another pressurized chamber, a pressure of 200 atm in Ar is applied for 1 minute at 150 to 300 ° C. for 5 μm Al.

Thereafter, an Al / Ti wiring layer is formed by resist patterning and dry etching. Condition Gas BCl ₃ / Cl ₂ = 60 / 90s
ccm Microwave power 1000W RF power 50W Pressure 0.016Pa

According to this example, a favorable wiring structure having high electromigration resistance was obtained.

Embodiment 5 In this embodiment, the groove 14 is buried under the same conditions as in Embodiment 4, except that the process is performed at 200 atm.
1 film formation was continued.

According to this embodiment, the same effects as those of the fourth embodiment can be obtained.

Embodiment 6 In this embodiment, only the step (d) of the embodiment 1 is changed.

In this embodiment, a target thin film Al is formed on the entire surface, and thereafter, a heat treatment at about 400 ° C. is continuously performed to increase the grain size. Thereafter, a target pattern is formed by resist patterning and dry etching. It is better to apply the heat treatment when the Al film is present on the entire solid surface, compared to the case where the heat treatment is applied after the conventional pattern formation.
This embodiment is advantageous because Al moves in all directions, which makes it possible to increase the particle size.

The step (d) of this embodiment is as follows. (D) Al / Ti wiring is formed. Ti film forming conditions Power 4 kW Film forming temperature 150 ° C. Gas Ar = 100 sccm Film thickness 30 nm Pressure 0.47 Pa

Further, Al is formed as a wiring material layer. Al film forming conditions Power 22.5 kW Film forming temperature 150 ° C. Gas Ar = 40 sccm Film thickness 5 μm Pressure 0.47 Pa

Thereafter, a heat treatment at 400 ° C. is continuously performed for 60 hours.
Add for a minute.

Thereafter, an Al / Ti wiring layer is formed by resist patterning and dry etching under the following conditions. Condition Gas BCl ₃ / Cl ₂ = 60 / 90s
ccm Microwave power 1000W RF power 50W Pressure 0.016Pa

This embodiment has the same effect as the above embodiment.

Each of the above embodiments can take various other variations. For example, the film forming method can be applied even when CVD other than sputtering is used. Further, the process example can also be applied to devices other than MOS devices (bipolar transistors, CCDs, etc.). Also, Cu,
It can be applied to wiring materials other than Al, such as Ag.

[0080]

According to the present invention, it is possible to provide a wiring having high electromigration resistance, for example, an Al-based wiring structure having high electromigration resistance, and a method for forming such a wiring structure.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a wiring structure according to a first embodiment.

FIG. 2 is a cross-sectional view showing a step of Example 1 (1).

FIG. 3 is a sectional view showing a step of the first embodiment (2).

FIG. 4 is a sectional view showing a step of the first embodiment (3).

FIG. 5 is a configuration diagram showing a polishing apparatus used in the embodiment.

FIG. 6 is a cross-sectional view illustrating a wiring structure according to a second embodiment.

FIG. 7 is an enlarged view of a main part of a wiring structure according to a second embodiment.

FIG. 8 is a diagram showing a conventional technique.

FIG. 9 is an operation explanatory view of the present invention.

[Explanation of symbols]

 Reference Signs List 1 substrate (Si substrate) 11a wiring material layer 11 wiring layer 13a wiring layer 13b wiring layer 14 groove

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-354337 (JP, A) JP-A-6-275611 (JP, A) JP-A-5-251444 (JP, A) JP-A-60-1985 161636 (JP, A) JP-A-4-340713 (JP, A) JP-A-63-244858 (JP, A) JP-A-7-193063 (JP, A) JP-A-3-222332 (JP, A) JP-A-5-182966 (JP, A) JP-A-3-166761 (JP, A) JP-A-5-23533 (JP, U) European Patent Application Publication 516344 (EP, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (3)

(57) [Claims] 1. A MOS transistor is formed on a substrate.
And, (b) forming an interlayer film to form a contact hole in the interlayer film, the wiring material embedded blanket W in (c) said connection hole
Formed as, (d) further form a wiring material layer of Al or Al alloy
Forming a wiring material layer by using Al or an Al alloy.
In extent, Al or A is formed as the wiring material layer
alloy in an inert gas atmosphere at a temperature below the melting point.
Completely embedded in the trench deeper than the wiring width of the wiring layer to be formed while applying a pressure of 0 to 200 atm.
Look, wiring material in the region other than the groove is polished or Dora
Etching to remove the wiring layer
A method for forming a wiring structure, wherein the crystal grain size is formed to be equal to or larger than the thickness of the wiring layer . 2. A MOS transistor is formed on a substrate.
And, (b) forming an interlayer film to form a contact hole in the interlayer film, the wiring material embedded blanket W in (c) said connection hole
Formed as, (d) further form a wiring material layer of Al or Al alloy
Forming the wiring material layer by using Al or an Al alloy in the method of forming a wiring structure having each of the following steps:
After completely embedding the alloy film in a groove deeper than the wiring width of the wiring layer to be formed, heat-treating the wiring material at a pressure of 200 atm at 150 ° C. to 300 ° C., and then forming a wiring material in a region other than the groove. Forming a wiring layer having a crystal grain size larger than the thickness of the wiring layer by removing the wiring layer by polishing or dry etching. 3. A MOS transistor is formed on a substrate.
And, (b) forming an interlayer film to form a contact hole in the interlayer film, the wiring material embedded blanket W in (c) said connection hole
Formed as, (d) further form a wiring material layer of Al or Al alloy
Forming a wiring material layer by using Al or an Al alloy.
In extent, Al or A is formed as the wiring material layer
alloy in an inert gas atmosphere at a temperature below the melting point.
Completely embedded in the trench deeper than the wiring width of the wiring layer to be formed while applying a pressure of 0 to 200 atm.
At a pressure of 200 atm.
After heat treatment at ~ 300 ° C, the wiring material in the area other than the groove is
This is removed by polishing or dry etching
The crystal grain size of the wiring layer is equal to or greater than the thickness of the wiring layer.
A method for forming a wiring structure, wherein the wiring structure is formed to have a size .