JP3348716B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which outputs an output strobe signal for notifying output data fetch timing together with output data.

[0002]

2. Description of the Related Art FIG. 7 is a circuit diagram showing a main part of an example of a conventional semiconductor memory device. This semiconductor memory device operates in synchronization with a rising edge and a falling edge of a clock signal. This is an example of a data rate synchronous dynamic random access memory (hereinafter referred to as DDR-SDRAM).

In FIG. 7, 1 is a command buffer for inputting a command signal, 2 is a command decoder for decoding a command signal output from the command buffer 1,
Reference numeral 3 denotes a controller which receives a command decode signal output from the command decoder 2 and controls an internal circuit according to the content of the command.

Reference numeral 4 denotes an address buffer for inputting a row address signal and a column address signal;
1, 5-m are address latches for latching a row address signal and a column address signal output from the address buffer 4.

Also, 6-1 and 6-m are banks, and in the bank 6-1, 7-1 is a memory cell array in which memory cells are arranged, and 8-1 is a row latched by an address latch 5-1. This is a row decoder that decodes an address signal and selects a word line.

Reference numeral 9-1 denotes a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged.
Reference numeral 1 denotes a column decoder which decodes a column address signal latched by the address latch 5-1 to select a column.

In bank 6-m, 7-m is a memory cell array in which memory cells are arranged, and 8-m decodes a row address signal latched by address latch 5-m to select a word line. It is a row decoder.

Reference numeral 9-m denotes a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged.
A column decoder m decodes a column address signal latched by the address latch 5-m to select a column.

Reference numeral 11-1 denotes a data bus buffer for amplifying read data output from the bank 6-1 to the core data bus CDB1, and 12-1 denotes a core data bus CDB.
1 is a write buffer for outputting write data.

Reference numeral 11-m denotes a data bus buffer for amplifying read data output from the bank 6-m to the core data bus CDBm, and reference numeral 12-m denotes a core data bus CDB.
m is a write buffer for outputting write data to m.

Further, DB is a peripheral data bus, 13 is a data output buffer for outputting output data DQ _OUT to the outside, and 14 is input data D of a parallel N-bit configuration from outside.
A data input buffer 15 for inputting Q _IN and a strobe output buffer 15 for outputting an output strobe signal QS _OUT .

FIG. 8 shows a conventional DDR-SDRA shown in FIG.
FIG. 9 is a circuit diagram illustrating a part of an example of an electronic device including M. 8, reference numeral 17 denotes the conventional DDR-SDRA shown in FIG.
M, and the electronic device includes a plurality of DDR-SDRAMs.
17 and a control chip (not shown) for controlling the plurality of DDR-SDRAMs 17.

Reference numeral 18 denotes a normal phase clock signal line for transmitting the normal phase clock signal CLK, and 19 denotes a normal phase clock signal C.
A reverse phase clock signal line for transmitting a reverse phase clock signal / CLK having a reverse phase relationship with LK; 20, a command bus for transmitting a command signal; 21, an address bus for transmitting a row address signal and a column address signal; Is a data bus.

Reference numeral 23 denotes a DDR-SDRAM 17
Output data DQ_OUTOutput data DQ output with_OUT
Strobe signal Q indicating the timing of capturing
S_{O UT}Strobe signal for transmitting to the control chip
Line.

FIG. 9 shows complementary clock signals CLK and / CLK when data is output from DDR-SDRAM 17.
, Output strobe signal QS _OUT and output data DQ _OUT
FIG. 6 is a waveform diagram showing the relationship between

In FIG. 9, tCKQS is a QS access time from the intersection of the clock signal CLK and the negative-phase clock signal / CLK, tQSPRE is a QS preamble time (QS Preamble Time), and tQSPST. Is a QS postamble time.

TQSQ is an output data skew (Data Output Skew from QS) from the strobe signal QS, tAC
Is the data access time (Data Access Time f) from the intersection of the clock signal CLK and the negative-phase clock signal / CLK.
rom CLK // CLK), tDV is the output data decision time (Data Outp
ut Valid Time).

The electronic device shown in FIG.
A strobe signal line 23 having the same environment is provided, and DDR
Output data DQ from SDRAM 17_OUTOutput
Trobe signal QS_OUTAnd the output strobe signal Q
S_OUTOutput data DQ as seen from _OUTThe fixed time of
And the output data DQ by the control chip_OUTReceiving
The aim is to facilitate the removal.

[0019]

However, if the rise time and the fall time of the output strobe signal QS _OUT are different, the output strobe cycle will not be constant, and therefore, the fixed time of the output data DQ _OUT will be constant. However, when it is difficult to take the timing of taking in the output data DQ _OUT and the output strobe cycle becomes short, for example, when the output strobe cycle becomes 4 ns or less, the reception of the output data DQ _OUT by the control chip may become uncertain. There was a problem.

In view of the foregoing, the present invention is a semiconductor memory device that outputs an output strobe signal for notifying the timing of capturing output data, and ensures that the control chip receives output data even when the output strobe cycle is shortened. It is an object of the present invention to provide a semiconductor memory device which can be carried out at any time.

[0021]

A semiconductor memory device according to the present invention is a semiconductor memory device having means for outputting an output strobe signal for notifying the timing of fetching output data together with output data, the means for outputting an output strobe signal. Is to output a complementary output strobe signal as an output strobe signal.

According to the semiconductor memory device of the present invention, since the complementary output strobe signal is output as the output strobe signal, the rising time and the falling time of each of the positive-phase output strobe signal and the negative-phase output strobe signal are different. Even if they differ, the cycle as the output strobe signal (the time between cross points of the complementary output strobe signal) is constant. Therefore, the fixed time (fixed width) of the output data can be fixed.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor memory device according to the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing a main part of one embodiment of the semiconductor memory device of the present invention. One embodiment of the semiconductor memory device of the present invention is a first cycle random access memory which is a kind of DDR-SDRAM. Access memory
FCRAM).

In FIG. 1, 25 is a command buffer for inputting a command signal, and 26 is a command decoder for decoding a command signal output from the command buffer 25.

Reference numeral 27 denotes an address buffer for inputting a row address signal and a column address signal;
Address latches -1, 28-m latch the row address signal and the column address signal output from the address buffer 27.

Reference numerals 29-1 and 29-m denote banks. In the bank 29-1, 30-1 is a memory cell array in which memory cells are arranged, and 31-1 is a row latched by an address latch 28-1. This is a row decoder that decodes an address signal and selects a word line.

Reference numeral 32-1 denotes a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged.
A column decoder -1 decodes a column address signal latched by the address latch 28-1 to select a column.

An active pre-controller 34-1 receives a command decode signal output from the command decoder 26 and controls the column decoder 33-1 and the sense amplifier array 32-1 according to the contents of the command.

In the bank 29-m, 30-m
Is a memory cell array in which memory cells are arranged, 31-m
Is a row decoder for decoding a row address signal latched by the address latch 28-m and selecting a word line.

Reference numeral 32-m denotes a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged.
A column decoder -m decodes a column address signal latched by the address latch 28-m to select a column.

An active pre-controller 34-m inputs a command decode signal output from the command decoder 26 and controls the column decoder 33-m, the sense amplifier array 32-m, etc. according to the contents of the command.

A data bus buffer 35-1 amplifies read data output from the bank 29-1 to the core data bus CDB1, and a core data bus CD-1 36-1.
A write buffer for outputting write data to B1.

A data bus buffer 35-m amplifies read data output from the bank 29-m to the core data bus CDBm, and a core data bus CD-36-m.
This is a write buffer for outputting write data to Bm.

Reference numeral 37 denotes a parallel / serial conversion circuit for serializing parallel data transmitted from the data bus buffer corresponding to the selected bank, and reference numeral 38 denotes a serialized output from the parallel / serial conversion circuit 37. output data DQ _OUT. 1 to a parallel N-bit configuration
This is a data output buffer for outputting DQ _OUT N to the outside.

Further, the data input buffer for 39 to input the input data DQ _IN 1~DQ _IN N parallel N-bit structure from the outside, 40 denotes an input data DQ parallel N-bit configuration which is output from the data input buffer 39 _{IN 1 to} DQ _IN
This is a serial / parallel conversion circuit for parallelizing each of N.

Reference numeral 41 denotes output data DQ _OUT 1 to DQ _OUT
A strobe output buffer that outputs complementary output strobe signals QS _OUT and / QS _OUT to the outside as output strobe signals together with _OUT N.

In one embodiment of the semiconductor memory device of the present invention, the burst length can be set to a plurality, and in such a case, a plurality of data are read from the selected bank at the time of reading. Operate to be read in parallel,
At the time of writing, a plurality of parallel data can be written to a selected bank.

FIG. 2 is a circuit diagram showing the configuration of the data output buffer 38 and the strobe output buffer 41. FIG.
In the equation, mCLK is an internal clock, DE is a data enable signal, mDQ _OUT 1, mDQ _OUT 2, and mDQ _OUT N are internal output data, and mQS _OUT is an internal output strobe signal.

In the data output buffer 38,
44 and 45 are nMOS transistors whose on and off are controlled by the internal clock signal mCLK, 46 are inverters for inverting the internal clock signal mCLK, and 47 and 48 are pMOs whose on and off are controlled by the output of the inverter 46.
It is an S transistor.

A latch circuit 49 includes inverters 50 and 51 for latching the data enable signal DE.
52 is an inverter 5 for latching the output of the latch circuit 49
3 and 54 are latch circuits.

55-1 is the internal output data mDQ
N for performing NAND processing on _OUT 1 and the output of the latch circuit 52
AND circuit, 55-2 is a NAND circuit for performing NAND processing on the internal output data mDQ _OUT 2 and the output of the latch circuit 52, and 55-N is a NAND circuit for performing NAND processing on the internal output data mDQ _OUT N and the output of the latch circuit 52 It is.

Also, 56-1, 56-2, 56-N are:
NAND circuits 55-1, 55-2, 55-N, respectively
Output data DQ _OUT 1 and DQ
_OUT3 , a three-state inverter that outputs DQ _OUT N.

In the strobe output buffer 41, reference numeral 57 denotes a NAND circuit for performing NAND processing on the internal output strobe signal mQS _OUT and the data enable signal DE; 58, an inverter for inverting the internal output strobe signal mQS _OUT ; This is a NAND circuit that performs NAND processing on the output and the data enable signal DE.

A three-state inverter 60 inverts and amplifies the output of the NAND circuit 57 and outputs a positive-phase output strobe signal QS _OUT , and 61 inverts and amplifies the output of the NAND circuit 59 to generate a negative-phase output strobe signal / QS. _OUT
Is a three-state inverter.

In the data output buffer 38 and the strobe output buffer 41 configured as described above, when the data enable signal DE goes high and the internal clock mCLK goes high, the data output buffer 38
, The output of the latch circuit 49 becomes L level, the output of the latch circuit 52 becomes H level, and the NAND circuit 55−
1-55-N are activated and the internal output data mDQ _OUT
Output data DQ _OUT 1 to DQ corresponding to 1 to mDQ _OUT N
_OUT N will be output.

Further, in the strobe output buffer 41, NAND circuits 57 and 59 is activated, the internal output strobe signal MQS _OUT complementary output strobe signal corresponding to QS _OUT, / QS _OUT is output.

FIG. 3 is a circuit diagram showing a part of an example of an electronic device having one embodiment of the semiconductor memory device of the present invention. In FIG. 3, reference numeral 63 denotes an FCRAM which is an embodiment of the semiconductor memory device of the present invention.
It has a CRAM 63 and a control chip (not shown) for controlling the plurality of FCRAMs 63.

Further, 64 is a normal phase clock signal line for transmitting the normal phase clock signal CLK, and 65 is a normal phase clock signal C.
A reverse phase clock signal line transmitting a reverse phase clock signal / CLK having a reverse phase relationship with LK; 66, a command bus for transmitting a command signal; 67, an address bus for transmitting a row address signal and a column address signal; Is a data bus.

Reference numeral 69 denotes a normal-phase output strobe signal QS for notifying the fetch timing of the output data DQ _OUT output together with the output data DQ _OUT from the FCRAM 63.
_This is a positive-phase output strobe signal line that transmits _OUT to the control chip.

Reference numeral 70 denotes a negative-phase output strobe signal line for transmitting a negative-phase output strobe signal / QS _OUT having a negative-phase relationship with the normal-phase output strobe signal QS _OUT output from the FCRAM 63 to the control chip.

FIG. 4 shows the relationship between the complementary clock signals CLK and / CLK, the complementary output strobe signals QS _OUT and / QS _OUT, and the continuous 2-bit output data DQ _OUT = RD 1 and RD 2 when outputting data from the FCRAM 63. It is a waveform diagram shown.

That is, in the electronic device shown in FIG. 3, the complementary output strobe signals QS _OUT and / QS _OUT indicate the start of the cycle of the complementary output strobe signals QS _OUT and / QS _OUT for a predetermined time before the first cross point. The preamble time
tQSPRE. During the preamble time tQSPRE, the positive-phase output strobe signal QS _OUT = L level,
The negative-phase output strobe signal / QS _OUT is set to H level.

As described above, during the preamble time tQSPRE, the positive-phase output strobe signal QS _OUT = L level,
By setting the negative-phase output strobe signal / QS _OUT = H level, when the circuit receiving the positive-phase output strobe signal QS _OUT and the negative-phase output strobe signal / QS _OUT is a differential amplifier, the internal level is determined and the output data is determined. DQ _OUT can be placed in a receivable state.

Further, the complementary output strobe signal QS _OUT ,
/ QS _OUT complementary output strobe signal QS _OUT indicating the end of the period of, / QS _OUT predetermined time after the cross point of the the post-amble time TQSPST, this time, the positive phase output strobe signal QS _OUT and the negative phase output strobe signal/
QS _OUT is set to a state having different levels.

The complementary output strobe signal QS _OUT ,
/ QS _OUT is the same as the level in the postamble time tQSPST during the standby time when the output data DQ _OUT is continuous even data, that is, the positive-phase output strobe signal QS
_OUT = L level, reverse phase output strobe signal / QS _OUT = H
Maintain levels.

The complementary output strobe signal QS_OUT,
/ QS_OUTIs the output data DQ as shown in FIG._OUTBut
In the case of 1 or consecutive odd data, post
Same as the level at the toamble time tQSPST, that is,
Normal phase output strobe signal QS _OUT= H level, reverse phase output
Strobe signal / QS_OUT= L level is maintained and the next
At the start of the preamble time tQSPRE
Control to return to the original level
Any questions about making the roll tip ready for reception
No title arises.

Further, in the FCRAM 63 which is one embodiment of the semiconductor memory device of the present invention, the cross point of the complementary output strobe signals QS _OUT and / QS _OUT is set so as to provide an edge trigger point of the output data DQout. However, the complementary output strobe signal QS _OUT ,
The cross point of / QS _OUT may be set so as to provide the center point of the output data DQ _OUT as shown in FIG.

As described above, in the FCRAM 63 which is one embodiment of the semiconductor memory device of the present invention, the complementary output strobe signal QS _OUT ,
/ QS _OUT is output, so that the positive-phase output strobe signal QS _OUT and the negative-phase output strobe signal / QS
Also in each of the _OUT even if the rise and fall times different, complementary output strobe signal QS _OUT, / QS _OUT period (complementary output strobe signal QS _OUT as an output strobe signal, / QS _OUT crosspoints ) Can be constant, so that the fixed time (fixed width) of the output data DQ _OUT can be fixed.

Therefore, according to the FCRAM 63 which is one embodiment of the semiconductor memory device of the present invention, even if the output strobe cycle becomes short, for example, even if the output strobe cycle becomes 4 ns or less, the output data DQ by the control chip is not changed. _OUT can be reliably received.

The FCRAM 63, which is one embodiment of the semiconductor memory device of the present invention, reads data of a bit length corresponding to the burst length from the selected bank in parallel, and transmits this to the parallel / serial conversion circuit 37. The data is transferred to the data output buffer 38 after being serialized to speed up the read operation. However, as described above, the complementary output strobe signal QS _OUT ,
Since the cycle of / QS _OUT is constant, the output data DQ _OUT
Can be fixed, and the operation of the parallel / serial conversion circuit 37 can be given a margin.

[0062]

As described above, according to the semiconductor memory device of the present invention, since the complementary output strobe signal is output as the output strobe signal, each of the positive phase output strobe signal and the negative phase output strobe signal is output. Even when the rise time and the fall time are different, the period of the output strobe signal can be fixed and the fixed time (fixed width) of the output data can be fixed. Thus, the output data of the semiconductor memory device of the present invention can be reliably received by the control chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a data output buffer and a strobe output buffer included in an embodiment of the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing a part of an example of an electronic device including one embodiment of the semiconductor memory device of the present invention.

FIG. 4 shows a complementary clock signal, a complementary output strobe signal, and two consecutive bits of output data at the time of data output from one embodiment of the semiconductor memory device of the present invention provided in the electronic device shown in FIG. FIG. 6 is a waveform diagram showing a relationship.

5 is a waveform chart for explaining another example of a method of setting a level of a complementary output strobe signal during a standby time in one embodiment of the semiconductor memory device of the present invention provided in the electronic device shown in FIG. 3; .

FIG. 6 is a waveform diagram showing a case where a cross point of a complementary output strobe signal gives a center point of output data.

FIG. 7 is a circuit diagram showing a main part of an example of a conventional semiconductor memory device.

8 is a circuit diagram showing a part of an example of an electronic device including the conventional DDR-SDRAM shown in FIG.

9 is a waveform diagram showing a relationship among a complementary clock signal, an output strobe signal, and output data when data is output from the conventional DDR-SDRAM shown in FIG.

[Explanation of symbols]

CLK, / CLK clock signal QS _OUT , / QS _OUT complementary output strobe signal

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Mitsunori Sato 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-11-328963 (JP, A) B. Cosoroaba, Dou ble data rate SYNC HRONOUS DRAM in Hi gh Performance App lications, WESCON / 97 Conference Procee dings, the United States, 387-391 (58) investigated the field (Int.Cl. ^7, DB name) G11C 11/407

Claims (1)

(57) [Claims] 1. A semiconductor memory device comprising: means for outputting an output strobe signal for notifying output data fetch timing together with output data, wherein said means for outputting said output strobe signal comprises a complementary output strobe as said output strobe signal. In a standby period in which a signal is output to a receiving circuit having a differential circuit configuration and the output data is not output, one of the complementary output strobe signals is maintained at an H level and the other is maintained at an L level. Semiconductor storage device.