JP3348937B2 - Semiconductor integrated circuit device and method of assembling the same - Google Patents
Semiconductor integrated circuit device and method of assembling the sameInfo
- Publication number
- JP3348937B2 JP3348937B2 JP28854993A JP28854993A JP3348937B2 JP 3348937 B2 JP3348937 B2 JP 3348937B2 JP 28854993 A JP28854993 A JP 28854993A JP 28854993 A JP28854993 A JP 28854993A JP 3348937 B2 JP3348937 B2 JP 3348937B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring board
- integrated circuit
- circuit device
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特にバンプを介して半導体チップを配線基板に装
着するフリップチップ方式の半導体集積回路装置に適用
して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique effective when applied to a flip-chip type semiconductor integrated circuit device in which a semiconductor chip is mounted on a wiring board via bumps.
【0002】[0002]
【従来の技術】今日、ゲートアレイやマイクロコンピュ
ータなどの論理LSIにおいては、集積回路の多機能
化、高速化に伴い、外部回路との接続を行うチップ電極
の数が急速に増大しており、半導体チップの周辺に設け
られたボンディングパッドにワイヤを接続して外部回路
との接続を行うワイヤボンディング方式が限界に達して
いる。2. Description of the Related Art Today, in logic LSIs such as gate arrays and microcomputers, the number of chip electrodes for connecting to external circuits has been rapidly increasing with the increase in the functions and speed of integrated circuits. A wire bonding method of connecting a wire to a bonding pad provided around a semiconductor chip to connect to an external circuit has reached a limit.
【0003】またワイヤボンディング方式は、内部領域
の配線を周辺部のボンディングパッドまで延ばすので配
線長が長くなり、信号伝達速度が遅延する欠点があるた
め、高速動作が要求される論理LSIの実装方式として
は不向きでもある。Further, the wire bonding method has a drawback that the wiring in the internal region extends to the bonding pads in the peripheral portion, so that the wiring length becomes long and the signal transmission speed is delayed. Also unsuitable for.
【0004】これらの理由から、半導体チップの最上層
配線にバンプを形成し、これを介して半導体チップを基
板に実装する、いわゆるフリップチップ方式のボンディ
ング技術が注目されている。For these reasons, attention has been paid to a so-called flip-chip bonding technique in which a bump is formed on the uppermost layer wiring of a semiconductor chip, and the semiconductor chip is mounted on the substrate via the bump.
【0005】このフリップチップ方式は、半導体チップ
の周辺領域のみならず、内部領域にもチップ電極を設け
ることができるので、半導体チップの多ピン化を図るこ
とができる利点がある。さらに、前述のワイヤボンディ
ング方式に比べて、内部領域の配線を周辺部まで延ばす
必要がなくなるだけ半導体チップ上の配線長を短くする
ことができ、論理LSIの高速化を図ることができる利
点もある。The flip chip method has an advantage that the number of pins of the semiconductor chip can be increased because chip electrodes can be provided not only in the peripheral area of the semiconductor chip but also in the internal area. Further, as compared with the above-described wire bonding method, there is an advantage that the wiring length on the semiconductor chip can be reduced as much as it is not necessary to extend the wiring in the internal region to the peripheral portion, and the speed of the logic LSI can be increased. .
【0006】このバンプはチップ電極の電極下地を介し
て形成されるもので、配線基板に設けられた電極パッド
と相対応させて位置合わせを行い、熱処理炉を通すこと
によりバンプをリフローしてボンディングを行ってい
る。The bumps are formed through the electrode bases of the chip electrodes. The bumps are aligned in correspondence with the electrode pads provided on the wiring board, and are passed through a heat treatment furnace to reflow the bumps for bonding. It is carried out.
【0007】[0007]
【発明が解決しようとする課題】このようなフリップチ
ップ方式では、前記のような利点があるものの、半導体
チップと配線基板との熱膨張係数の不一致からバンプに
熱ひずみを生じ、温度サイクルの結果、接続部が熱疲労
破壊するという問題点がある。特に、半導体チップの中
心から最も遠い位置にあるバンプには最大のひずみが生
じることになり、この傾向は一層顕著である。したがっ
て、接続部の熱疲労破壊を防止するためには、配線基板
の熱膨張係数を半導体チップの熱膨張係数(3×10-6
〔K-1〕)に整合させることが必要となる。Although such a flip-chip method has the above-mentioned advantages, thermal distortion occurs in the bumps due to the mismatch in the coefficient of thermal expansion between the semiconductor chip and the wiring board, resulting in a temperature cycle. In addition, there is a problem that the connection portion is broken by thermal fatigue. In particular, the bumps located farthest from the center of the semiconductor chip will experience the largest distortion, and this tendency is even more remarkable. Therefore, in order to prevent thermal fatigue destruction of the connection portion, the thermal expansion coefficient of the wiring board is reduced by the thermal expansion coefficient of the semiconductor chip (3 × 10 −6).
[K -1 ]).
【0008】このような配線基板としては、ムライトま
たは窒化アルミニウムが最適であるが(熱膨張係数:3
〜4×10-6〔K-1〕)需要が少なく高価であり、近年
の半導体集積回路装置の高集積化による多ピン化が進
み、安価なシステムにおいてもフリップチップ方式によ
る実装が要求されている中では、採用が困難である。一
方、アルミナセラミックは比較的安価ではあるが、熱膨
張係数が大きい(7×10-6〔K-1〕)ために半導体チ
ップのサイズに制約が生じる。さらに、一般的な配線基
板であるガラスエポキシ樹脂では、熱膨張係数が15×
10-6〔K-1〕と極めて大きいために、フリップチップ
方式による実装自体が困難である。As such a wiring board, mullite or aluminum nitride is optimal (coefficient of thermal expansion: 3).
44 × 10 −6 [K −1 ])) The demand is low and the price is high. In recent years, the number of pins has been increased due to the high integration of semiconductor integrated circuit devices. Are difficult to adopt. On the other hand, alumina ceramic is relatively inexpensive, but has a large coefficient of thermal expansion (7 × 10 −6 [K −1 ]), which limits the size of the semiconductor chip. Furthermore, in the case of glass epoxy resin which is a general wiring board, the thermal expansion coefficient is 15 ×.
Since it is extremely large at 10 -6 [K -1 ], mounting itself by the flip chip method is difficult.
【0009】安価な配線基板にもフリップチップ方式に
よる実装を可能にするため、半導体チップと基板との間
を樹脂接着剤で埋めて接続寿命を延長する技術が提案さ
れているが(1992 42nd Electronic Conponents&Techno
logy Conference pp.22)、一旦樹脂埋めした後では、半
導体チップの交換が困難である。In order to enable mounting on an inexpensive wiring board by a flip-chip method, a technique of extending the connection life by filling the space between the semiconductor chip and the board with a resin adhesive has been proposed (1992 42nd Electronic Technology). Conponents & Techno
logy Conference pp.22), it is difficult to replace semiconductor chips once they are filled with resin.
【0010】そこで、本発明の目的は、半導体チップと
配線基板との熱膨張係数の整合性を問わず、フリップチ
ップ方式による実装が可能な半導体集積回路装置に関す
る技術を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a technique relating to a semiconductor integrated circuit device which can be mounted by a flip chip method regardless of the matching of thermal expansion coefficients between a semiconductor chip and a wiring board.
【0011】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【0012】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を説明すれば、次の通
りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be outlined as follows.
【0013】すなわち、本発明の半導体集積回路装置
は、搭載する半導体チップの電極配置に合わせて電極パ
ッドを配設した配線基板と、バンプを介してフリップチ
ップ方式に前記配線基板に搭載された、1つまたは高さ
が揃えられた複数の半導体チップと、前記半導体チップ
の裏面全面にわたって接触して、前記配線基板との間に
前記半導体チップを挟み込み、所定の圧力にて前記半導
体チップを押圧する板状の押圧部材とを備え、前記配線
基板上の前記電極パッドの表面形状を凹状曲面に形成
し、前記半導体チップが前記押圧部材により前記配線基
板に押圧されることで、前記半導体チップの電極と前記
配線基板上に形成された前記電極パッドとが横方向位置
ずれを可能としながら前記バンプを介して電気的に接続
されるものである。In other words, the semiconductor integrated circuit device of the present invention has a wiring board on which electrode pads are arranged in accordance with the electrode arrangement of a semiconductor chip to be mounted, and is mounted on the wiring board in a flip-chip manner via bumps. One or more semiconductor chips having the same height are brought into contact with the entire back surface of the semiconductor chip, the semiconductor chip is sandwiched between the wiring substrate and the semiconductor chip, and the semiconductor chip is pressed with a predetermined pressure. and a plate-like pressing member, wherein the wire
Form the surface shape of the electrode pad on the substrate into a concave curved surface
And, wherein that semiconductor chip is pressed against the wiring board by the pressing member, the bump while said electrode pad formed on the wiring board and the electrode of the semiconductor chip to allow the lateral position deviation It is electrically connected via the
【0014】また、本発明の半導体集積回路装置の組立
方法は、1つまたは高さが揃えられた複数の半導体チッ
プを、バンプを介してフリップチップ方式に配線基板上
の表面形状を凹状曲面に形成した電極パッドに搭載し、
板状の押圧部材を前記半導体チップの裏面全面にわたっ
て接触させて、前記配線基板との間に前記半導体チップ
を挟み込み、前記押圧部材により前記半導体チップを前
記配線基板に所定の圧力で押圧することにより、前記半
導体チップを前記配線基板上の前記電極パッドに対して
横方向位置ずれを可能としながら前記バンプを介して電
気的に接続するものである。Further, according to the method of assembling a semiconductor integrated circuit device of the present invention, one or a plurality of semiconductor chips having the same height are formed into a concave curved surface on a wiring board in a flip chip manner via bumps. Mount on the formed electrode pad,
By bringing a plate-shaped pressing member into contact with the entire back surface of the semiconductor chip, sandwiching the semiconductor chip with the wiring substrate, and pressing the semiconductor chip against the wiring substrate with a predetermined pressure by the pressing member. The semiconductor chip is electrically connected to the electrode pads on the wiring board via the bumps while allowing the semiconductor chips to be displaced in the lateral direction.
【0015】[0015]
【作用】上記のような構成の半導体集積回路装置によれ
ば、半導体チップが押圧部材に押圧されることによって
チップ電極が配線基板の電極パッドと電気的に接続され
たフリップチップ方式による実装構造とされているの
で、半導体チップと配線基板との熱膨張係数が不一致で
あっても、バンプと電極パッドとの位置関係が僅かにず
れつつも、両者の電気的な接続状態は確実に維持され
る。According to the semiconductor integrated circuit device having the above-described structure, a flip chip type mounting structure in which the chip electrodes are electrically connected to the electrode pads of the wiring board by the pressing of the semiconductor chip by the pressing member. Therefore, even if the thermal expansion coefficients of the semiconductor chip and the wiring board do not match, the electrical connection state between the bumps and the electrode pads is reliably maintained even though the positional relationship between the bumps and the electrode pads is slightly shifted. .
【0016】したがって、熱処理でリフローさせてバン
プを電極パッドにボンディングする場合と異なり、バン
プに熱ひずみが生じることがなく、接続部が熱疲労破壊
するおそれもない。すなわち、本発明の半導体集積回路
装置によれば、半導体チップとこれが装着される配線基
板との熱膨張係数の整合性を問わず、フリップチップ方
式により半導体チップを配線基板に装着することが可能
になる。Therefore, unlike the case where the bumps are bonded to the electrode pads by reflow by heat treatment, no thermal strain is generated in the bumps, and there is no possibility that the connection portions may be damaged by thermal fatigue. That is, according to the semiconductor integrated circuit device of the present invention, the semiconductor chip can be mounted on the wiring board by the flip chip method regardless of the matching of the thermal expansion coefficient between the semiconductor chip and the wiring board on which the semiconductor chip is mounted. Become.
【0017】また、上記のような構成の半導体集積回路
装置の組立方法によれば、位置合わせにおいて設定され
た半導体チップのバンプと配線基板の電極パッドとの位
置関係がずれることがないので、押圧部材により半導体
チップを配線基板に押圧して固定した場合、バンプと電
極パッドとの電気的接続を確実に図ることが可能にな
る。Further, according to the method of assembling the semiconductor integrated circuit device having the above-described configuration, the positional relationship between the bumps of the semiconductor chip and the electrode pads of the wiring board set in the alignment does not shift, so that the pressing is performed. When the semiconductor chip is pressed and fixed to the wiring board by the member, the electrical connection between the bump and the electrode pad can be reliably achieved.
【0018】[0018]
【実施例】以下、本発明の実施例を、図面に基づいてさ
らに詳細に説明する。Embodiments of the present invention will be described below in more detail with reference to the drawings.
【0019】(実施例1)図1は本発明の一実施例であ
る半導体集積回路装置を示す正面図、図2はその半導体
集積回路装置の要部断面図、そして図3はその半導体集
積回路装置の半導体チップと配線基板との接続状態を示
す断面図である。(Embodiment 1) FIG. 1 is a front view showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a sectional view of a principal part of the semiconductor integrated circuit device, and FIG. It is sectional drawing which shows the connection state of the semiconductor chip of an apparatus and a wiring board.
【0020】本実施例の半導体集積回路装置1はチップ
電極2に形成されたAuバンプ(バンプ)3を介して、
半導体チップ4がMCM(Multi-Chip Module )配線基
板(配線基板)5に装着されるフリップチップ方式の半
導体集積回路装置である。The semiconductor integrated circuit device 1 according to the present embodiment, via an Au bump (bump) 3 formed on the chip electrode 2,
This is a flip-chip type semiconductor integrated circuit device in which a semiconductor chip 4 is mounted on an MCM (Multi-Chip Module) wiring board (wiring board) 5.
【0021】図3に示すように、半導体チップ4の表面
には絶縁膜6が形成されて、作り込まれた回路素子(図
示せず)を保護しており、チップ電極2には、たとえば
Cr−Cu−Auからなる多層の金属薄膜で電極下地7
が形成されている。そして、この電極下地7を介して、
Auバンプ3がたとえばボールボンディング法により形
成されている。As shown in FIG. 3, an insulating film 6 is formed on the surface of the semiconductor chip 4 to protect a built-in circuit element (not shown). -An electrode substrate 7 with a multilayer metal thin film made of Cu-Au;
Is formed. Then, through the electrode base 7,
The Au bump 3 is formed by, for example, a ball bonding method.
【0022】一方、このAuバンプ3と接続されるMC
M配線基板5は、たとえば熱膨張係数が7×10-6〔K
-1〕であるアルミナセラミックからなっており、ここに
形成された電極パッド8は、たとえばAuからなる平坦
な表面形状であり、図2に示すように、接続孔9を介し
て配線層10と電気的に接続されている。On the other hand, the MC connected to the Au bump 3
The M wiring board 5 has, for example, a coefficient of thermal expansion of 7 × 10 −6 [K
The electrode pad 8 formed here has a flat surface shape made of, for example, Au, and is connected to the wiring layer 10 through the connection hole 9 as shown in FIG. It is electrically connected.
【0023】そして、図1に示すように、この半導体チ
ップ4は押圧部材11によりMCM配線基板5側に押圧
され、これによってチップ電極2と電極パッド8とが電
気的に接続されている。すなわち、MCM配線基板5と
押圧部材11とをボルト12とナット13とによってね
じ結合し、この両者でサンドイッチするように半導体チ
ップ4を設けることによって、チップ電極2と電極パッ
ド8との電気的な接触状態が確保されている。なお、ボ
ルト12の頭部と押圧部材11の外面側との間にはコイ
ルばね14が装着されており、このコイルばね14の弾
発力によって押圧部材11の過度の押圧力が調整され半
導体チップ4の破壊が防止されている。As shown in FIG. 1, the semiconductor chip 4 is pressed against the MCM wiring board 5 by a pressing member 11, whereby the chip electrodes 2 and the electrode pads 8 are electrically connected. That is, the MCM wiring board 5 and the pressing member 11 are screwed together with the bolts 12 and the nuts 13, and the semiconductor chip 4 is provided so as to be sandwiched between them. The contact state is ensured. A coil spring 14 is mounted between the head of the bolt 12 and the outer surface of the pressing member 11, and an excessive pressing force of the pressing member 11 is adjusted by the elastic force of the coil spring 14 so that the semiconductor chip 4 is prevented from being destroyed.
【0024】このように、本実施例の半導体集積回路装
置では、半導体チップ4が押圧部材11に押圧されるこ
とによって、半導体チップ4に形成されたチップ電極2
がMCM配線基板5の電極パッド8と電気的に接続され
たフリップチップ方式による実装構造とされている。As described above, in the semiconductor integrated circuit device of this embodiment, the semiconductor chip 4 is pressed by the pressing member 11 so that the chip electrode 2 formed on the semiconductor chip 4 is formed.
Have a flip-chip mounting structure electrically connected to the electrode pads 8 of the MCM wiring board 5.
【0025】したがって、Auバンプ3を熱処理でリフ
ローしてボンディングをした場合と異なり、半導体チッ
プ4の熱膨張係数が3×10-6〔K-1〕で、MCM配線
基板5の熱膨張係数が7×10-6〔K-1〕と両者の整合
性がとれていなくても、作動時において半導体チップ4
が発熱したときには、Auバンプ3と電極パッド8との
位置関係が僅かにずれるにとどまり、両者の電気的な接
続状態は確実に保持されることになる。Therefore, unlike the case where the Au bumps 3 are reflowed and bonded by heat treatment, the semiconductor chip 4 has a thermal expansion coefficient of 3 × 10 -6 [K -1 ] and the MCM wiring board 5 has a thermal expansion coefficient of Even when the consistency between 7 × 10 -6 [K -1 ] and both is not ensured, the semiconductor chip 4 during operation is not required.
When the heat is generated, the positional relationship between the Au bump 3 and the electrode pad 8 is slightly shifted, and the electrical connection between the two is reliably maintained.
【0026】したがって、Auバンプ3に熱ひずみが生
じることがなく、接続部が熱疲労破壊するおそれもな
く、半導体チップ4とMCM配線基板5との熱膨張係数
の整合性を問題にすることなく、フリップチップ方式に
より半導体チップ4を装着することが可能になる。Therefore, no thermal strain is generated in the Au bump 3, there is no possibility that the connection portion is damaged by thermal fatigue, and there is no problem in matching the thermal expansion coefficient between the semiconductor chip 4 and the MCM wiring board 5. The semiconductor chip 4 can be mounted by the flip chip method.
【0027】さらに半導体チップ4のAuバンプ3とM
CM配線基板5の電極パッド8とがいずれもAuからな
っているので、電気抵抗の小さい良好な接触状態を得る
ことができる。Further, the Au bumps 3 and M of the semiconductor chip 4
Since both of the electrode pads 8 of the CM wiring board 5 are made of Au, a good contact state with low electric resistance can be obtained.
【0028】(実施例2)図4は本発明の他の実施例で
ある半導体集積回路装置を示す正面図、図5はその半導
体集積回路装置の要部断面図、そして図6はその半導体
集積回路装置の半導体チップと配線基板との接続状態を
示す断面図である。(Embodiment 2) FIG. 4 is a front view showing a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 5 is a sectional view of a principal part of the semiconductor integrated circuit device, and FIG. FIG. 3 is a cross-sectional view illustrating a connection state between a semiconductor chip of a circuit device and a wiring board.
【0029】本実施例の半導体集積回路装置21におい
ては、図4に示すように、半導体チップ4をMCM配線
基板(配線基板)25側に押圧する押圧部材31の外面
に放熱フィン35が設けられ、この放熱フィン35によ
って半導体チップ4の熱が放散されるようになってい
る。In the semiconductor integrated circuit device 21 of the present embodiment, as shown in FIG. 4, a radiation fin 35 is provided on the outer surface of a pressing member 31 for pressing the semiconductor chip 4 toward the MCM wiring board (wiring board) 25 side. The heat radiation fins 35 dissipate the heat of the semiconductor chip 4.
【0030】また、図5に示すように、この押圧部材3
1の内面には樹脂フィルム36が貼着され、図6に示す
ように、形成された電極パッド28は凹状曲面の表面形
状とされている。さらに、MCM配線基板25は、たと
えば熱膨張係数が15×10-6〔K-1〕であるガラスエ
ポキシ樹脂からなっている。Further, as shown in FIG.
A resin film 36 is adhered to the inner surface of the electrode pad 1, and as shown in FIG. 6, the formed electrode pad 28 has a concave curved surface. Further, the MCM wiring board 25 is made of, for example, a glass epoxy resin having a thermal expansion coefficient of 15 × 10 −6 [K −1 ].
【0031】なお、本実施例以下において、前記実施例
と同一のものについては同一の符号を付している。In this embodiment and the following, the same reference numerals are given to the same components as those in the above embodiment.
【0032】本実施例の半導体集積回路装置では、前記
した実施例1の半導体集積回路装置の特徴が維持されつ
つ、さらに、押圧部材31の外面に放熱フィン35が設
けられているので、半導体チップ4からの熱は、Auバ
ンプ3からMCM配線基板25に至る経路のみならず、
この放熱フィン35からも放散されることになる。した
がって、熱放散効率が向上し、作動時におけるAuバン
プ3と電極パッド28との位置ずれを最小限にとどめる
ことが可能になる。In the semiconductor integrated circuit device of the present embodiment, since the radiation fins 35 are provided on the outer surface of the pressing member 31 while maintaining the features of the semiconductor integrated circuit device of the first embodiment, the semiconductor chip The heat from 4 is not limited to the path from the Au bump 3 to the MCM wiring board 25,
The heat is also radiated from the heat radiation fins 35. Therefore, the heat dissipation efficiency is improved, and the displacement between the Au bump 3 and the electrode pad 28 during operation can be minimized.
【0033】また、押圧部材31の内面に樹脂フィルム
36が貼着されているので、MCM配線基板25の電極
パッド28に対する半導体チップ4のAuバンプ(バン
プ)3のずれを樹脂フィルム36の弾性変形により防止
することができる。Further, since the resin film 36 is adhered to the inner surface of the pressing member 31, the displacement of the Au bump (bump) 3 of the semiconductor chip 4 with respect to the electrode pad 28 of the MCM wiring board 25 is controlled by the elastic deformation of the resin film 36. Can be prevented.
【0034】さらに、電極パッド28が凹状曲面の表面
形状とされているので、熱膨張係数が大きいガラスエポ
キシ樹脂をMCM配線基板25に用いても、Auバンプ
3と電極パッド28との位置ずれによる導通不良のおそ
れを確実に排除することができ、信頼性の向上を図るこ
とが可能になる。Further, since the electrode pad 28 has a concavely curved surface shape, even if a glass epoxy resin having a large thermal expansion coefficient is used for the MCM wiring board 25, the position difference between the Au bump 3 and the electrode pad 28 is caused. It is possible to reliably eliminate the possibility of conduction failure and improve reliability.
【0035】(実施例3)図7は本発明のさらに他の実
施例である半導体集積回路装置を示す要部断面図、図8
はその半導体集積回路装置の半導体チップと配線基板と
の接続状態を示す断面図である。(Embodiment 3) FIG. 7 is a sectional view of a principal part showing a semiconductor integrated circuit device according to still another embodiment of the present invention.
FIG. 2 is a sectional view showing a connection state between a semiconductor chip and a wiring board of the semiconductor integrated circuit device.
【0036】本実施例の半導体集積回路装置41は、そ
の組立時において、半導体チップ4のAuパンプ(バン
プ)3を共晶はんだ(ろう材)57でMCM配線基板
(配線基板)25の電極パッド28に仮接合し、その
後、押圧部材51により半導体チップ4をMCM配線基
板25に押圧して固定したものである。In the semiconductor integrated circuit device 41 of this embodiment, the Au pumps (bumps) 3 of the semiconductor chip 4 are eutectic solder (brazing material) 57 and the electrode pads of the MCM wiring board (wiring board) 25 at the time of assembly. 28, and then the semiconductor chip 4 is pressed against the MCM wiring board 25 by a pressing member 51 and fixed.
【0037】また、本実施例の半導体集積回路装置41
においては、押圧部材51の内面に凹状の固定溝58が
形成されており、半導体チップ4はこの固定溝58に嵌
合した状態でMCM配線基板25に装着されている。The semiconductor integrated circuit device 41 of the present embodiment
5, a concave fixing groove 58 is formed on the inner surface of the pressing member 51, and the semiconductor chip 4 is mounted on the MCM wiring board 25 in a state fitted in the fixing groove 58.
【0038】本実施例の半導体集積回路装置では、実施
例1の半導体集積回路装置の有する特徴に加えて、共晶
はんだ57によってAuバンプ3を電極パッド28に仮
接合した後に固定しているので、位置合わせにおけるA
uバンプ3と電極パッド28との位置関係が確実に保持
される。In the semiconductor integrated circuit device of the present embodiment, in addition to the features of the semiconductor integrated circuit device of the first embodiment, the Au bump 3 is temporarily bonded to the electrode pad 28 by the eutectic solder 57 and then fixed. , A in alignment
The positional relationship between the u bump 3 and the electrode pad 28 is reliably maintained.
【0039】さらに、押圧部材51の内面に凹状の固定
溝58が形成されているので、前記した実施例2の場合
と同様に、電極パッド28に対するAuバンプ3のずれ
を確実に防止することができる。Further, since the concave fixing groove 58 is formed on the inner surface of the pressing member 51, the displacement of the Au bump 3 with respect to the electrode pad 28 can be reliably prevented as in the case of the second embodiment. it can.
【0040】(実施例4)図9は本発明のさらに他の実
施例である半導体集積回路装置を示す要部断面図であ
る。(Embodiment 4) FIG. 9 is a sectional view showing a main part of a semiconductor integrated circuit device according to still another embodiment of the present invention.
【0041】本実施例の半導体集積回路装置61では、
ポリイミドフィルム62に形成された貫通電極63がA
uバンプとされ、このポリイミドフィルム62を半導体
チップ4とMCM配線基板(配線基板)5との間に設け
て押圧部材11で押圧することによって、チップ電極と
電極パッドとが貫通電極63を介し電気的に接続された
ものである。In the semiconductor integrated circuit device 61 of this embodiment,
The through electrode 63 formed on the polyimide film 62 has A
The polyimide film 62 is provided between the semiconductor chip 4 and the MCM wiring board (wiring board) 5 and is pressed by the pressing member 11 so that the chip electrode and the electrode pad are electrically connected via the through electrode 63. Are connected together.
【0042】このように、半導体チップ4を押圧部材1
1によりMCM配線基板5に装着する半導体集積回路装
置61によれば、バンプをリフローしてボンディングす
る必要がないので、貫通電極63の形成されたポリイミ
ドフィルム62を用いることも可能になる。As described above, the semiconductor chip 4 is connected to the pressing member 1.
According to 1, according to the semiconductor integrated circuit device 61 to be mounted on the MCM wiring substrate 5, it is not necessary to reflow and bond the bumps, so that it is possible to use the polyimide film 62 on which the through electrodes 63 are formed.
【0043】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は前記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更が可能であることは言うまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist of the invention. Needless to say.
【0044】たとえば、前記実施例において半導体チッ
プ4をMCM配線基板5,25に装着している押圧部材
11,31,51はボルト12とナット13、およびコ
イルばね14によって押圧力が付与されているが、その
他にも、押圧部材11,31,51とMCM配線基板
5,25との外周部を挟持する構造などとすることもで
きる。すなわち、本発明においては、いかなる押圧手段
かを問わず、半導体チップ4が押圧部材11,31,5
1によってMCM配線基板5,25に押圧されていれば
よい。For example, the pressing members 11, 31, and 51 for mounting the semiconductor chip 4 on the MCM wiring boards 5 and 25 in the above embodiment are given a pressing force by the bolts 12 and the nuts 13 and the coil springs 14. However, besides, a structure in which the outer peripheral portions of the pressing members 11, 31, 51 and the MCM wiring boards 5, 25 are sandwiched may be adopted. That is, in the present invention, the semiconductor chip 4 is connected to the pressing members 11, 31, 5 regardless of the pressing means.
1 only needs to be pressed against the MCM wiring boards 5 and 25.
【0045】また、前記実施例においては、バンプ3と
電極パッド8,28がともにAuからなっているが、通
常のようにPb−Sn等で形成することも勿論可能であ
り、また、いずれか一方をAuで形成することも可能で
ある。In the above embodiment, both the bumps 3 and the electrode pads 8 and 28 are made of Au. However, the bumps 3 and the electrode pads 8 and 28 may be made of Pb-Sn or the like as usual. One of them can be made of Au.
【0046】さらに、前記実施例のMCM配線基板5,
25はアルミナセラミックおよびガラスエポキシ樹脂で
あるが、これに限定されることなく他の種々のものを用
いることが可能であり、熱膨張係数が半導体チップ4と
整合性を有するものを用いてもよい。Further, the MCM wiring board 5,
Reference numeral 25 denotes an alumina ceramic and a glass epoxy resin. However, the present invention is not limited to this, and various other types can be used. Those having a coefficient of thermal expansion that is compatible with the semiconductor chip 4 may be used. .
【0047】[0047]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下の通りである。Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.
【0048】(1).すなわち、本発明の半導体集積回路装
置によれば、半導体チップが押圧部材に押圧されること
によって、半導体チップに形成されたチップ電極が配線
基板の電極パッドと電気的に接続されたフリップチップ
方式による実装構造である。したがって、バンプを熱処
理でリフローしてボンディングをした場合と異なり、半
導体チップと配線基板の熱膨張係数の整合性がとれてい
なくても、作動時において半導体チップが発熱したとき
には、バンプと電極パッドとの位置関係が僅かにずれる
にとどまり、両者の電気的な接続状態は確実に保持され
る。よって、バンプに熱ひずみが生じることがなく、接
続部が熱疲労破壊するおそれもないので、半導体チップ
と配線基板との熱膨張係数の整合性を問題にすることな
く、フリップチップ方式により半導体チップを装着する
ことが可能になる。(1) According to the semiconductor integrated circuit device of the present invention, when the semiconductor chip is pressed by the pressing member, the chip electrodes formed on the semiconductor chip are electrically connected to the electrode pads of the wiring board. This is a mounting structure by a connected flip chip method. Therefore, unlike the case where the bumps are reflowed by heat treatment and bonded, even when the thermal expansion coefficients of the semiconductor chip and the wiring board are not consistent, when the semiconductor chip generates heat during operation, the bumps and the electrode pads are not connected. Only slightly deviates from each other, and the electrical connection between the two is reliably maintained. Therefore, no thermal distortion occurs in the bumps, and there is no possibility of thermal fatigue destruction of the connection portion. Therefore, the semiconductor chip is manufactured by the flip chip method without making the thermal expansion coefficient match between the semiconductor chip and the wiring board. Can be mounted.
【0049】(2).また、押圧部材を取り外すことにより
容易に半導体チップを交換することができるので、不良
品の半導体チップの取り替えが簡単にできる。(2) Since the semiconductor chip can be easily replaced by removing the pressing member, replacement of a defective semiconductor chip can be easily performed.
【0050】(3).バンプと電極パッドがAuからなる半
導体集積回路装置によれば、電気抵抗の小さい良好な接
触状態を得ることができ、動作の高速化、安定化を図る
ことができる。(3) According to the semiconductor integrated circuit device in which the bumps and the electrode pads are made of Au, a good contact state with small electric resistance can be obtained, and the operation can be speeded up and stabilized.
【0051】(4).配線基板の電極パッドが凹状曲面の表
面形状である半導体集積回路装置によれば、熱膨張係数
が大きいガラスエポキシ樹脂などを配線基板に用いて
も、バンプと電極パッドとの位置ずれによる導通不良の
おそれを確実に排除することができ、信頼性の向上を図
ることが可能になる。(4) According to the semiconductor integrated circuit device in which the electrode pads of the wiring board have a concave curved surface, even if glass epoxy resin or the like having a large coefficient of thermal expansion is used for the wiring board, the bumps and the electrode pads are not formed. In this case, it is possible to reliably eliminate the possibility of conduction failure due to misalignment, and to improve reliability.
【0052】(5).押圧部材の外面に放熱フィンが設けら
れた半導体集積回路装置によれば、半導体チップからの
熱は放熱フィンからも放散されることになるので、熱放
散効率が向上し、作動時におけるバンプと電極パッドと
の位置ずれを最小限にとどめることができる。(5) According to the semiconductor integrated circuit device in which the radiation fins are provided on the outer surface of the pressing member, the heat from the semiconductor chip is also radiated from the radiation fins, so that the heat radiation efficiency is improved. In addition, the displacement between the bumps and the electrode pads during operation can be minimized.
【0053】(6).押圧部材の内面に樹脂フィルムが貼着
された半導体集積回路装置によれば、配線基板の電極パ
ッドに対する半導体チップのバンプのずれを樹脂フィル
ムの弾性変形により防止することができ、半導体チップ
装着時の安定化を図ることができる。(6) According to the semiconductor integrated circuit device in which the resin film is adhered to the inner surface of the pressing member, the displacement of the bump of the semiconductor chip with respect to the electrode pad of the wiring board can be prevented by the elastic deformation of the resin film. It is possible to stabilize the mounting of the semiconductor chip.
【0054】(7).押圧部材の内面に凹状の固定溝が形成
された半導体集積回路装置によれば、半導体チップが固
定溝に嵌合して配線基板に装着されているので、同様に
電極パッドに対するバンプのずれを防止することができ
る。(7) According to the semiconductor integrated circuit device in which the concave fixing groove is formed on the inner surface of the pressing member, the semiconductor chip is fitted into the fixing groove and mounted on the wiring board. The displacement of the bump with respect to the pad can be prevented.
【0055】(8).半導体チップのパンプをろう材で配線
基板の電極パッドに仮接合した後に、押圧部材により半
導体チップを配線基板に押圧して固定する半導体集積回
路装置の組立方法によれば、位置合わせにおけるバンプ
と電極パッドとの位置関係が確実に保持され、装置の信
頼性の向上を図ることができる。(8) According to the method of assembling a semiconductor integrated circuit device, in which the semiconductor chip pump is temporarily joined to the electrode pads of the wiring board with a brazing material, and then the semiconductor chip is pressed against the wiring board with a pressing member and fixed. In addition, the positional relationship between the bumps and the electrode pads in the alignment is reliably maintained, and the reliability of the device can be improved.
【図1】本発明の実施例1による半導体集積回路装置を
示す正面図である。FIG. 1 is a front view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.
【図2】その半導体集積回路装置の要部断面図である。FIG. 2 is a sectional view of a main part of the semiconductor integrated circuit device.
【図3】その半導体集積回路装置の半導体チップと配線
基板との接続状態を示す断面図である。FIG. 3 is a sectional view showing a connection state between a semiconductor chip and a wiring board of the semiconductor integrated circuit device.
【図4】本発明の実施例2による半導体集積回路装置を
示す正面図である。FIG. 4 is a front view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.
【図5】その半導体集積回路装置の要部断面図である。FIG. 5 is a sectional view of a principal part of the semiconductor integrated circuit device.
【図6】その半導体集積回路装置の半導体チップと配線
基板との接続状態を示す断面図である。FIG. 6 is a sectional view showing a connection state between a semiconductor chip and a wiring board of the semiconductor integrated circuit device.
【図7】本発明の実施例3による半導体集積回路装置を
示す要部断面図である。FIG. 7 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to Embodiment 3 of the present invention.
【図8】その半導体集積回路装置の半導体チップと配線
基板との接続状態を示す断面図である。FIG. 8 is a sectional view showing a connection state between a semiconductor chip and a wiring board of the semiconductor integrated circuit device.
【図9】本発明の実施例4による半導体集積回路装置を
示す要部断面図である。FIG. 9 is a fragmentary cross-sectional view showing a semiconductor integrated circuit device according to Embodiment 4 of the present invention.
1 半導体集積回路装置 2 チップ電極 3 Auバンプ(バンプ) 4 半導体チップ 5 MCM配線基板(配線基板) 6 絶縁膜 7 電極下地 8 電極パッド 9 接続孔 10 配線層 11 押圧部材 12 ボルト 13 ナット 14 コイルばね 21 半導体集積回路装置 25 MCM配線基板(配線基板) 28 電極パッド 31 押圧部材 35 放熱フィン 36 樹脂フィルム 41 半導体集積回路装置 51 押圧部材 57 共晶はんだ(ろう材) 58 固定溝 61 半導体集積回路装置 62 ポリイミドフィルム 63 貫通電極 Reference Signs List 1 semiconductor integrated circuit device 2 chip electrode 3 Au bump (bump) 4 semiconductor chip 5 MCM wiring board (wiring board) 6 insulating film 7 electrode base 8 electrode pad 9 connection hole 10 wiring layer 11 pressing member 12 bolt 13 nut 14 coil spring Reference Signs List 21 semiconductor integrated circuit device 25 MCM wiring substrate (wiring substrate) 28 electrode pad 31 pressing member 35 radiation fin 36 resin film 41 semiconductor integrated circuit device 51 pressing member 57 eutectic solder (brazing material) 58 fixing groove 61 semiconductor integrated circuit device 62 Polyimide film 63 Through electrode
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平1−255176(JP,A) 特開 昭59−184553(JP,A) 特開 平3−27552(JP,A) 実開 昭62−163945(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 25/40 H01L 21/60 H01L 23/32 H01R 33/76 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-255176 (JP, A) JP-A-59-184553 (JP, A) JP-A-3-27552 (JP, A) Jpn. 163945 (JP, U) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 25/40 H01L 21/60 H01L 23/32 H01R 33/76
Claims (3)
せて電極パッドを配設した配線基板と、 バンプを介してフリップチップ方式に前記配線基板に搭
載された、1つまたは高さが揃えられた複数の半導体チ
ップと、 前記半導体チップの裏面全面にわたって接触して、前記
配線基板との間に前記半導体チップを挟み込み、所定の
圧力にて前記半導体チップを押圧する板状の押圧部材と
を備え、前記配線基板上の前記電極パッドの表面形状を凹状曲面
に形成し、 前記半導体チップが前記押圧部材により前記配線基板に
押圧されることで、前記半導体チップの電極と前記配線
基板上に形成された前記電極パッドとが横方向位置ずれ
を可能としながら前記バンプを介して電気的に接続され
ることを特徴とする半導体集積回路装置。1. A wiring board on which electrode pads are arranged in accordance with the electrode arrangement of a semiconductor chip to be mounted, and one or the heights mounted on the wiring board in a flip-chip manner via bumps. A plurality of semiconductor chips, a plate-shaped pressing member that contacts the entire back surface of the semiconductor chip, sandwiches the semiconductor chip between the wiring substrate, and presses the semiconductor chip at a predetermined pressure; The surface shape of the electrode pad on the wiring substrate is a concave curved surface
The semiconductor chip is pressed against the wiring board by the pressing member, so that the electrodes of the semiconductor chip and the electrode pads formed on the wiring board can be displaced in the lateral direction while the semiconductor chip is pressed. A semiconductor integrated circuit device electrically connected through bumps.
ともいずれか一方がAuからなることを特徴とする請求
項1記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein at least one of said bump and said electrode pad is made of Au.
体チップを、バンプを介してフリップチップ方式に配線
基板上の表面形状を凹状曲面に形成した電極パッドに搭
載し、 板状の押圧部材を前記半導体チップの裏面全面にわたっ
て接触させて、前記配線基板との間に前記半導体チップ
を挟み込み、 前記押圧部材により前記半導体チップを前記配線基板に
所定の圧力で押圧することにより、前記半導体チップを
前記配線基板上の前記電極パッドに対して横方向位置ず
れを可能としながら前記バンプを介して電気的に接続す
ることを特徴とする半導体集積回路装置の組立方法。3. One or a plurality of semiconductor chips having the same height are mounted on an electrode pad having a concave curved surface on a wiring board in a flip-chip manner via bumps, and a plate-shaped pressing is performed. The member is brought into contact with the entire back surface of the semiconductor chip, the semiconductor chip is sandwiched between the semiconductor chip and the wiring substrate, and the semiconductor chip is pressed against the wiring substrate with a predetermined pressure by the pressing member. Electrically connecting the electrode pads to the electrode pads on the wiring board via the bumps while allowing the electrodes to be displaced in the lateral direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28854993A JP3348937B2 (en) | 1993-11-17 | 1993-11-17 | Semiconductor integrated circuit device and method of assembling the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28854993A JP3348937B2 (en) | 1993-11-17 | 1993-11-17 | Semiconductor integrated circuit device and method of assembling the same |
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| Publication Number | Publication Date |
|---|---|
| JPH07142534A JPH07142534A (en) | 1995-06-02 |
| JP3348937B2 true JP3348937B2 (en) | 2002-11-20 |
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|---|---|---|---|
| JP28854993A Expired - Fee Related JP3348937B2 (en) | 1993-11-17 | 1993-11-17 | Semiconductor integrated circuit device and method of assembling the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011033641A1 (en) | 2009-09-17 | 2011-03-24 | 株式会社 東芝 | Electronic device |
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| Publication number | Publication date |
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| JPH07142534A (en) | 1995-06-02 |
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