JP3349300B2 - Power saving control device, portable device using the same, and power saving control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving control device for stopping a clock supply to a CPU during a period in which processing by the CPU is unnecessary, switching the CPU to a power down mode for saving power consumption of the CPU, and causing the CPU to stand by. The present invention relates to a method, and a mobile device such as a mobile phone and a mobile information terminal using the same.

[0002]

2. Description of the Related Art A power-saving device used to reduce the power consumption of a portable device is, for example, a portable telephone which, when there is no outgoing call or incoming call for a predetermined time, enters a power down mode from a CPU. After receiving the switching request and executing the power down command by the CPU, the CPU is switched to the power down mode to be on standby, and a call or an incoming call is generated and the
By restarting the supply of the clock to the CPU when the processing of U becomes necessary, the power consumption of the CPU is reduced.

FIG. 4 is a flowchart showing a procedure for switching to a power down mode by a conventional power saving control device. When an occurrence of a request to switch to the power-down mode from the CPU is detected (S201), a process for inhibiting an external interrupt to the CPU is executed so that an interrupt signal is not input until the CPU switches to the power-down mode. (S202). The CPU executes a power-down command for switching to the power-down mode (S203).
When U switches to the power down mode, the power down status signal which becomes active / inactive depending on whether the CPU is in the power down mode becomes active among the status signals indicating the state of the execution environment of the CPU.

It is detected whether or not the switching of the CPU to the power-down mode has been completed, that is, whether or not the power-down status signal has been activated (S204). The supply is stopped, and the CPU is brought into a state where the system operation is stopped. In this state, the inhibition of the interrupt is released, and the CPU waits until the next interrupt occurs (S20).
5). If an interrupt occurs while the CPU is waiting, the CPU
, The clock supply is resumed, the CPU is returned from the power down mode, and the CPU executes processing for the interrupt.

[0005]

As described above, the conventional power-saving control device executes in advance the process of disabling the interrupt from the generation of the request for switching to the power-down mode until switching to the power-down mode. There must be. The reason is that an interrupt generated during execution of a power-down instruction in response to a request to switch to the power-down mode is a low-priority interrupt that can be extended earlier, for example, an interrupt such as a key input of a telephone number accompanying a call. In this case, if the mode is switched to the power down mode while the acceptance of the interrupt is first extended, the information of the interrupt may be lost.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to provide a method for switching to a power-down mode after a request for switching to a power-down mode is issued. Hold the interrupt signal, prohibit output to the CPU until the clock supply is restarted, and if the CPU switches to the power down mode and detects that the interrupt signal is Supply is restarted and the interrupt signal is sent to the CPU.
Output to the power-down mode, the interrupt processing between the power-down mode and the power-down mode is not performed.
Power saving control apparatus and method in which interrupt information is not lost,
In addition, the purpose of the present invention is to provide portable devices using these.

[0007]

According to a first aspect of the present invention, there is provided a power saving control apparatus, which executes a predetermined process in response to a request to switch to a power down mode in which a clock supply to the CPU is stopped, and then powers down the CPU. The power-saving control device switches the mode to the standby mode, resumes the supply of the clock to the CPU when the processing of the CPU becomes necessary, and saves the power consumption of the CPU. And also detects whether the CPU has been switched to the power-down mode and the supply of the clock has been stopped or whether the clock supply to the CPU has been restarted. While the CPU is executing or waiting in the power-down mode, the interrupt signal to the CPU is held while the CPU is stopped. After click supply is resumed, and the interrupt control means for outputting an interrupt signal held to CPU, after the CPU has been switched to the power-down mode,
And clock supply means for restarting the supply of the clock to the CPU when the interruption control means detects that the interruption signal is held.

[0008] A portable device according to a second aspect of the invention uses the power saving control device according to the first aspect of the invention.

A power saving control method according to a third aspect of the present invention provides a power saving control method, wherein the CPU executes predetermined processing in response to a request to switch to a power down mode in which clock supply to the CPU is stopped.
In the power saving control method for switching the power supply mode to the power down mode and making the CPU stand by, and restarting the supply of the clock to the CPU when the processing of the CPU becomes necessary, to save the power consumption of the CPU, Is detected, the CPU is switched to the power-down mode to detect whether or not the supply of the clock is stopped, and a request to switch to the power-down mode is issued and the predetermined processing is being executed, or in the power-down mode. C while waiting
After the interrupt signal to the PU is held and the CPU detects that the interrupt signal is held after the switching of the CPU to the power down mode is completed, the supply of the clock to the CPU is restarted and the clock to the CPU is restarted. After the supply is restarted, the held interrupt signal is output to the CPU.

A power saving control device, a portable device using the same, and a power saving control method according to the present invention detect the occurrence of a request to switch to a power down mode and switch the CPU to the power down mode to supply a clock. Is stopped, and a request to switch to the power-down mode is issued and the CPU is executing a predetermined process or interrupts the CPU while the CPU is in the power-down mode. After the CPU is switched to the power-down mode, if it is detected that the interrupt signal is being held, the supply of the clock to the CPU is resumed, and the supply of the clock to the CPU is stopped. After the restart, the interrupt signal held is output to the CPU. As a result, the information of the interrupt disappears even if the process of prohibiting the interrupt from the outside is not performed in advance from the generation of the switch request to the power down mode to the completion of the switch to stop the clock supply to the CPU. do not do.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a configuration of a main part of a portable device using a power saving control device of the present invention and a flow of signals. In the figure, reference numeral 1 denotes a CPU, and 2 denotes a register. When a request for switching to the power down mode is generated, the CPU 1 outputs a power down request signal a to the register 2.
And the occurrence of the switching request is written into the register 2. After outputting the power-down request signal a to the register 2, the CPU 1 executes a power-down instruction composed of a predetermined process for switching to the power-down mode, and when the execution of the power-down instruction is completed, activates the power-down status signal d. Further, the CPU 1 outputs a power-down return request signal e from a power-down control unit 4 described later, and makes the power-down status signal d inactive when the supply of the clock is resumed.

When the interrupt signal c to the CPU 1 is input, the interrupt control unit 3 temporarily latches the interrupt signal c, refers to the power down status signal b indicating the generation state of the request to switch the register 2 to the power down mode, and When the status signal b does not indicate the occurrence of the switching request, the latched interrupt signal c is output to the CPU 1.

On the other hand, when the power-down request status signal b indicates that a switching request has occurred, the interrupt control unit 3 determines whether or not the power-down request status signal b is active / inactive.
The interrupt signal c is latched until the power down status signal d indicating whether the PU 1 is in the power down mode becomes inactive, and is output to the CPU 1 when the power down status signal d becomes inactive.

The power-down control unit 4 supplies a clock to the CPU 1 in a normal mode other than the power-down mode. However, the CPU 1 terminates execution of the power-down instruction and the power-down status signal d becomes active, and the power-down mode is turned off. Then, the supply of the clock to the CPU 1 is stopped. The power down control unit 4
Monitors the interrupt control unit 3 while the power-down status signal d is active to detect whether the interrupt signal c is latched. If the interrupt control unit 3 has already latched the interrupt signal c, Alternatively, when the interrupt signal c is latched while the CPU 1 is on standby, a power-down return request signal e for returning the CPU 1 from the power-down mode to the normal mode is output to the CPU 1 and the
U1 is returned to normal mode and C
The supply of the clock to PU1 is restarted. The above-described register 2, interrupt control unit 3, and power-down control unit 4 constitute a power saving control device.

Next, the procedure of the power saving control method of the present invention will be described with reference to the flowchart shown in FIG. 2 and the timing chart shown in FIG. The CPU 1 outputs a power-down request signal a and writes the generation of the switching request to the register 2 in response to the generation of the switching request to the power-down mode. Notify the power down controller 4 (S1
01), a process for executing the power down instruction is started . When the interrupt signal c is input to the interrupt control unit 3 which detects that the request to switch to the power down mode has been generated with reference to the power down status signal b written in the register 2 (S102), the interrupt is generated. The control unit 3 latches the interrupt signal c (S103).

An internal counter (not shown) of the CPU 1 counts up time, and after a predetermined time elapses, the CPU 1
1 determines whether or not the cancellation of the request to switch to the power down mode has occurred, and writes information on whether or not to cancel the cancellation into the register 2 (S104). Power down controller 4
When it is confirmed by the data written in the register 2 that the request to switch to the power down mode has been released, the switch to the power down mode is stopped. At this time, if the interrupt signal is latched by the interrupt control unit 3 (S105), the interrupt control unit 3 outputs the latched interrupt signal c to the CPU 1, and the CPU 1 performs processing corresponding to the interrupt signal c. Is executed (S107). If the interrupt signal c is not latched, the CPU 1 waits in the normal mode (S106).

If the request to switch to the power down mode has not been released in step S104, the CP
U1 executes a power down command (S108). CP
When U1 finishes executing the power-down command and actually switches to the power-down mode, U1 activates the power-down status signal d (S111), and outputs information indicating that the power-down mode has been switched to the interrupt control unit 3 and the power controller. Notify the down control unit 4. When the interrupt signal c is input to the interrupt control unit 3 after the power down command is executed and before the power down status signal d becomes active (S109), the interrupt control unit 3 latches the interrupt signal c. (S110).

When the power down status signal d becomes active, the power down control unit 3 starts monitoring whether the interrupt control unit 3 latches the interrupt signal c (S112). As a result of the monitoring, when it is confirmed that the interrupt signal c is not latched, the CPU 1 is made to stand by in the power down mode until a return from the power down mode is requested from outside (S115).

On the other hand, the interrupt signal
Is already latched, or when the interrupt signal c is latched during standby in the power-down mode, the power-down control unit 4 outputs a power-down return request signal e to the CPU 1 to switch the CPU 1 to the normal mode. The CPU 1 is returned to a state where it can be returned, and the supply of the clock to the CPU 1 is restarted to release the CPU 1 from the power down mode (S11).
3). The CPU 1 released from the power down mode makes the power down status signal d inactive.
The interrupt control unit 3 monitors the power down status signal d of the CPU 1 and outputs an interrupt signal c to the CPU 1 when it determines that the CPU 1 has become inactive (S1).
14).

[0020]

As described above, the power saving control device, the portable device using the same, and the power saving method according to the present invention can be used until the power down mode is switched to the power down mode. CPU generated during
Is held until the supply of the clock is restarted, and after the CPU switches to the power down mode, when the CPU detects that the interrupt signal is being held, the supply of the clock is restarted. Interrupt signal to CPU
Output to the power-down mode, the interrupt processing between the power-down mode and the power-down mode is not performed.
This has an excellent effect that the information of the interruption does not disappear.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a portable device using a power saving control device of the present invention and a signal flow.

FIG. 2 is a flowchart illustrating an operation of the power saving control device of the present invention.

FIG. 3 is a timing chart of the operation of the power saving control device of the present invention.

FIG. 4 is a flowchart showing a procedure for switching to a power down mode by a conventional power saving control device.

[Explanation of symbols]

 1 CPU 2 register 3 interrupt control unit 4 power down control unit

Continuation of the front page (72) Inventor Hideyuki Yamamoto 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Toshiaki Mizushima 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo (56) References JP-A-4-245518 (JP, A) JP-A-58-114242 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1 / 26-1/32 H04B 7/26 H04M 1/73

Claims (3)

(57) [Claims] After the CPU executes a predetermined process in response to a request to switch to a power down mode in which the supply of a clock to the CPU is stopped, the CPU switches to the power down mode and waits for CPU processing. C
In the power saving control device that restarts the supply of the clock to the PU and saves the power consumption of the CPU, the occurrence of the request to switch to the power down mode is detected, and the CPU is switched to the power down mode to supply the clock. Detecting whether the clock is stopped or the clock supply to the CPU is resumed, an interrupt to the CPU is performed while the predetermined process is being executed and a request for switching to the power down mode is being generated or while the standby is being performed in the power down mode. While holding the signal, after the clock supply to the CPU is resumed,
An interrupt control means for outputting the held interrupt signal to the CPU; and a clock supply to the CPU when the interrupt control means detects that the interrupt signal is held after the CPU is switched to the power down mode. And a clock supply unit for restarting the operation. 2. A portable device using the power saving control device according to claim 1. 3. After the CPU executes a predetermined process in response to a request to switch to a power-down mode in which supply of a clock to the CPU is stopped, the CPU switches to the power-down mode to stand by, and the CPU needs to perform processing. C
In the power saving control method for restarting the supply of the clock to the PU and saving the power consumption of the CPU, the occurrence of a request to switch to the power down mode is detected, the CPU is switched to the power down mode, and the supply of the clock is stopped. During the execution of the predetermined processing or the standby in the power down mode, an interrupt signal to the CPU is held, and the CPU power down is detected. After the switching to the mode is completed, if it is detected that the interrupt signal is held, the supply of the clock to the CPU is resumed, and
A power saving control method comprising: outputting a held interrupt signal to a CPU after clock supply to a PU is resumed.