JP3350485B2 - Active matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device comprising a display pixel electrode array using thin film transistors as switching elements.

[0002]

2. Description of the Related Art In recent years, large-capacity, high-density active matrix type liquid crystal display devices for television display, graphic display, and the like have been developed and put into practical use as display devices using liquid crystal. In such a display device, a semiconductor switch is used as drive control means for each pixel so that high-contrast display can be performed without crosstalk.

[0003] As this semiconductor switch, a thin film transistor (TFT) can be used because a transmissive display is possible and the area can be easily increased.
Is formed on an insulating substrate.

FIG. 3 shows a schematic cross-sectional structure disclosed in Japanese Patent Application Laid-Open No. 56-162793 as an example of the above-mentioned liquid crystal display device. In this FIG.
2 is a transparent insulating substrate such as glass, and one of the insulating substrates 11
On one main surface, a plurality of thin film transistors 13 and display pixel electrodes 14 made of a transparent electrode film are arranged in a matrix. Also, on one main surface of the other insulating substrate 12,
A counter electrode 15 of a transparent conductive film is formed on the entire surface. These two insulating substrates 11 and 12 are arranged with a gap therebetween so that one main surface of each of the two insulating substrates 11 and 12 faces each other. And
The periphery of this gap is sealed with a sealing agent 16, and a liquid crystal 17 is sealed inside.

Next, an electric circuit for one pixel of a display pixel electrode array having a thin film transistor will be described with reference to FIG. In FIG. 4, reference numeral 21 denotes a signal line, 22 denotes a scanning line, and the signal line 21 and the scanning line 22 cross each other on one main surface of the insulating substrate 11 and are insulated from each other. It is arranged. A thin film transistor 13 is provided at each intersection of the signal line 21 and the scanning line 22. The gate of each thin film transistor 13 is a scanning line for each row.
The drain is connected to the signal line 21 for each column. Further, the source is connected to the display pixel electrode 14. The display pixel electrode 14 is connected to the liquid crystal 17 as described above.
Opposing the counter electrode 15 through the
Is connected to the positive electrode side of the DC power supply 24.

Next, a driving method for one pixel by a circuit configuration will be described.

When a video signal is applied from the signal line 21 to the drain during a period in which a scanning line selection voltage is applied from the scanning line 22 to the gate of the thin film transistor 13, that is, during a switching period, the display pixel electrode 14 connected to the source is Is set to the same potential as the video signal potential. The display pixel electrode 14 keeps this potential during the period when the scanning line non-selection voltage is applied to the gate. As a result, a potential difference corresponding to the video signal voltage is applied to the liquid crystal 17 sandwiched between the display pixel electrode 14 and the counter electrode 15 set to a predetermined potential. When the arrangement state of the liquid crystal 17 changes according to the potential difference, the light transmittance of the liquid crystal portion where the potential difference occurs changes, and an image is displayed.

[0008] Here, when a DC drive the liquid crystal 17, a liquid crystal 17
Is degraded by the electrolysis of molecules and its life is shortened, so that AC driving is performed. Generally, the potential of the counter electrode 15 is set to a DC potential, and the video signal voltage is set to be positive / negative symmetric with respect to this counter electrode potential in an even-odd frame.
AC drive. That is, the video signal voltage is obtained by adding a predetermined DC voltage and a positive / negative symmetric AC voltage corresponding to the video signal.

5 and 6 are cross-sectional views of one pixel of a display pixel electrode array provided with a thin film transistor. FIG. 5 shows a thin film transistor 13 portion, and FIG. 6 shows a signal line 21 portion.

First, the thin film transistor 13 will be described with reference to FIG. In FIG. 5, 13G is a gate electrode, and this gate electrode 13G is one of the insulating substrates 11 to be an array substrate 27.
It is formed above and is conductively connected to a scanning line (not shown).
The surface of the gate electrode 13G and the surface of the insulating substrate 11 including the gate electrode 13G are covered with a gate insulating film. A semiconductor layer 29 is formed on a portion facing the upper surface of the gate electrode 13G with the gate insulating film 28 interposed therebetween.
In the upper center of the semiconductor layer 29, an insulator layer as an insulating film
30 are formed.

A source electrode 13S is formed on the left half of the semiconductor layer 29 and the insulator layer 30 via an ohmic layer 31a. 13D is a drain electrode, and this drain electrode 13D is formed on the right half of the semiconductor layer 29 and the insulator layer 30 in the figure via an ohmic layer 31b. The display pixel electrode 14 is conductively connected so as to overlap one end of the drain electrode 13D, and is formed on the gate insulating film 28. These components are entirely covered with an alignment film 32.

As described above, the counter substrate 34 with respect to the array substrate 27 is provided over the entirety of one main surface of the insulating substrate 12.
Are formed, and an alignment film 35 is formed on the entire surface of the counter substrate 34 over the entire surface. The liquid crystal 17 is interposed between the array substrate 27 and the opposing substrate.

Next, the signal line 21 will be described with reference to FIG. The gate insulating film 28 is formed on the insulating substrate 11 as described above, and the signal line 21 is formed at a position avoiding the display pixel electrode 14 for each pixel. The signal line 21 is also covered with the alignment film 32 as described above.

By the way, in the liquid crystal display device having such a configuration, as shown, the drain electrode 13D, the source electrode 13S and the signal line 21 of the thin film transistor 13 are connected to the display pixel electrode.
14 is convex. In the manufacturing process of the liquid crystal display device, there is a so-called rubbing process in which the entire alignment film 32 is subjected to a liquid crystal alignment process using a roller. In this case, as described above, the drain electrode 13D, the source electrode 13S and the signal line 21 are provided.
Are convex with respect to the display pixel electrode 14, the alignment film 32 in these portions is rubbed more strongly than the alignment film 32 in the display pixel electrode 14. Therefore, these drain electrodes 13
D, the alignment film 32 of the source electrode 13S and the signal line 21 portion is likely to peel during rubbing, and when the peeling occurs, even if the thickness of the alignment film 32 is about several μm, these drain electrodes 13D, Source electrode 13S and signal line 21 are directly liquid crystal
Contact 17

Here, a chemically active low-resistance metal such as aluminum is often used as a material of the signal line 21, but when these metals come into direct contact with the liquid crystal 17, a metal component is contained in the liquid crystal 17. And the specific resistance of the liquid crystal 17 in the vicinity is lowered. For this reason, during the period in which the scanning line non-selection voltage is applied to the scanning line 22, the electric charge to be held by the display pixel electrode 14 leaks through the liquid crystal 17, so that the contrast and the gradation display capability are reduced. Causes poor image quality.

Also, for this reason, the signal line 21 and the source electrode 13
The passivation film and the like for the signal line 21 and the source electrode 13S so that the S and the drain electrode 13D do not directly contact the liquid crystal 17.
And on the surface in contact with the liquid crystal 17 including the surface of the drain electrode 13D.

[0017]

As described above, in the active matrix type liquid crystal display device using the thin film transistor 13 as the semiconductor switch, the rubbing is likely to occur on the alignment film 32 of the electrode or the wiring portion during the rubbing, and the peeling causes the image quality. Failure occurs.

In the case of forming a passivation film, there is a problem that the number of steps increases and the structure becomes complicated.

The present invention has been made in view of the above problems, and even if rubbing causes a part of the alignment film to peel off,
It is an object of the present invention to provide an active matrix type liquid crystal display device which can be easily configured without causing a decrease in specific resistance in the vicinity thereof and without causing image quality defects due to the decrease in specific resistance.

[0020]

According to the present invention, there are provided a plurality of scanning lines and signal lines arranged crossing each other on one main surface of an insulating substrate, and arranged near each intersection of the scanning lines and signal lines. iT is provided via the thin film transistor to be
An active matrix type liquid crystal display device comprising: an array substrate having a display pixel electrode formed of O; a counter substrate facing the array substrate; and a liquid crystal disposed between the array substrate and the counter substrate. The thin film transistor may include a gate electrode connected to the scanning line, an insulating film provided on the gate electrode, a semiconductor film provided on the insulating film, a semiconductor film provided on the insulating film, and a signal line provided on the signal line. a source electrode electrically connected, wherein the semiconductor film and includes a drain electrode, wherein connected to the display pixel electrodes electrically, the signal lines, each of the source electrode and the drain electrode, wherein the pixel electrode the same the material protective layer formed of ITO is coated, the array substrate, an alignment layer disposed directly on said display pixel electrode and the protective layer and Only contains, said the source electrode semiconductor
Between the film, and between the drain electrode and the semiconductor film.
In between, ohmic layers are arranged.
The end of the backing layer is covered with the protective layer .

Then, between the source electrode and the semiconductor film,
Ohmic between the drain electrode and the semiconductor film.
Arrange the backing layer so that the end of this ohmic layer and the source
Electrodes and drain electrodes, respectively,
Covered with a protective layer made of ITO of the same material as
Therefore, the orientation on these source and drain electrodes
Even if the film comes off during rubbing, these source electrodes and
The drain electrode no longer directly contacts the liquid crystal,
The alignment film on the protective layer that covers the edge of the
When peeling off during the
Source and drain electrodes no longer directly contact the liquid crystal.
Lowers the contrast caused by contamination of the liquid crystal
And image quality defects such as a decrease in gradation display capability are prevented. Ma
The end of the ohmic layer is covered with a protective layer, and the protective layer
Direct alignment of array substrate on display and display pixel electrodes
Required to cover the end of the ohmic layer
Process increases.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

1 and 2 are cross-sectional views of one pixel of a display pixel electrode array provided with a thin film transistor. FIG. 1 shows a thin film transistor 13 portion, and FIG. 2 shows a signal line 21 portion. Note that these configurations have many parts in common with the conventional configuration shown in FIGS. 5 and 6, and therefore, the common parts will be described with the same reference numerals.

First, the portion of the thin film transistor 13 will be described with reference to FIG.

As shown in FIG. 1, the gate electrode 13G is formed on one of the insulating substrates 11 to be the array substrate 27, and is conductively connected to a scanning line (not shown). Then, the surface of the gate electrode 13G and the insulating substrate 11 including the gate electrode 13G
Is covered with a gate insulating film. A semiconductor layer 29 as a semiconductor film is formed at a portion facing the upper surface of the gate electrode 13G via the gate insulating film 28, and an insulator layer 30 is formed at the upper center of the semiconductor layer 29. .

The source electrode 13S is formed on the semiconductor layer 29 and a part of the insulator layer 30 via an ohmic layer 31a, and the drain electrode 13D is formed on the semiconductor layer 29 and the insulator layer 3.
It is formed on the other part on 0 through the ohmic layer 31b. The display pixel electrode 14 is conductively connected so as to overlap one end of the drain electrode 13D, and is formed on the gate insulating film 28.

Further, the surface of the source electrode 13S and the drain electrode 13D and the signal line 21, that is, the surface of the liquid crystal 17 sandwiched between the counter substrate 34 is made of the same material as the display pixel electrode 14, for example. Protective film of ITO (Indium Tin Oxide)
Is covered with a protective layer 14a. This protective layer 14a
The end of the ohmic layer 31b is covered. Further, the whole of the display pixel electrode 14 and the protective layer 14a is directly arranged and covered by the alignment film 32.

Further, deflection plates 36 and 37 are formed on both outer sides of the insulating substrates 11 and 12 of the array substrate 27 and the counter substrate 34.

The counter substrate 34 with respect to the array substrate 27
Is the same as that shown in FIG. 5 and FIG. 6, in which an opposing electrode 15 is formed over the entire main surface of the insulating substrate 12, and an alignment film 35 is further formed on the upper surface of the insulating substrate 12. Is formed over.

The signal line 21 is, as shown in FIG.
Display pixel electrode for each pixel on the gate insulating film 28 on 11
It is formed in a state avoiding 14. And this signal line
21 is also covered with the same material as the display pixel electrode 14, for example, the protective layer 14a of ITO, and then covered with the alignment film 32 as described above. The signal lines 21 are provided with a plurality of scanning lines 22 crossing each other and insulated from each other. The thin film transistor 13 is provided at the intersection of the signal line 21 and the scanning line 22.

In the above configuration, the drain electrode 13D, the source electrode 13S, and the signal line 21 of the thin film transistor 13
Generally, the same material is used, and has a convex shape with respect to the display pixel electrode 14. Therefore, at the time of rubbing, the alignment film 32 of the drain electrode 13D, a source electrode 13S and the signal line 21 portion is rubbed strongly than the orientation film 32 of the pixel electrode 14 portion, peeling occurs in the orientation film 32 of these portions Sometimes.

Here, a part of the alignment film 32, for example, a signal line
If the alignment film 32 in the portion 21 is completely or partially peeled off, the signal line 21 is placed on the display pixel electrode 14 in a portion in contact with the liquid crystal 17 on the surface of the signal line material, for example, aluminum.
Since the protective layer 14a of ITO made of the same material as that of the first embodiment is formed, the aluminum signal line 21 does not directly contact the liquid crystal 17 without forming a passivation film.
Therefore, unlike the conventional case, a metal component such as aluminum is mixed into the liquid crystal 17, the specific resistance of the liquid crystal 17 in the vicinity is reduced, and the image quality defect such as a decrease in contrast and a decrease in gradation display capability does not occur. The ITO of the protective layer 14a
Is an oxide, is chemically very stable and has a protective layer
Even if 14a itself comes into direct contact with the liquid crystal 17, the ITO component
Therefore, the specific resistance in the vicinity of the peeling of the alignment film 32 does not decrease, and the image quality does not deteriorate due to the decrease in the specific resistance.
Further, the same applies to a case where a part of the alignment film 32 on the surface of the drain electrode 13D and the source electrode 13S of the thin film transistor 13 has peeled off.

Further, due to the double structure in which the ITO of the protective layer 14a is formed on the aluminum surface of the signal line 21, even if the wiring portion of the aluminum signal line 21 is disconnected, the disconnection portion of the ITO is applied to the aluminum wire. The presence of the wiring of the protective layer 14a does not cause a disconnection, the reduction in yield due to the disconnection of the signal line 21 can be suppressed, and the reliability of the liquid crystal display device itself improves. Further, since the manufacturing process itself is the same as that of the related art, an effect can be expected without complicating the manufacturing process, which is a new factor for lowering the yield.

Further, as shown in FIG.
Between the source electrode 13S of the star 13 and the semiconductor layer 29,
Drain electrode 13D of thin film transistor 13 and semiconductor layer 2
The ohmic layers 31a and 31b are arranged between
Of the ohmic layers 31a and 31b, and the source electrode 13S and
Each of the drain electrodes 13D is covered with an ITO protective layer 14a.
By covering, the source electrode 13S and the
If the alignment film 32 on the rain electrode 13D is rubbed during rubbing
If the source electrode 13S and the drain
Each of the electrodes 13D is covered with an ITO protective film 14a.
The source electrode 13S and the drain electrode 13D
Does not come into direct contact with the liquid crystal 17.

Further , the ends of the ohmic layers 31a and 31b are covered.
If the alignment film 32 on the protective layer 14a
In any case, the ends of these ohmic layers 31a and 31b are
These ohmic layers 31a, 31b
Source electrode 13S and drain electrode 13D
There is no direct contact with the liquid crystal 17. Therefore, the contamination of the liquid crystal 17 is
The reduction in contrast caused by dyeing and the
Poor image quality such as deterioration can be prevented.

Further, the ends of the ohmic layers 31a and 31b are retained.
Protective layer 14a, and the protective layer 14a and the display pixel electrode 14
Since the alignment film 32 of the array substrate 27 was directly disposed on the
For covering the edges of the ohmic layers 31a, 31b, etc.
The increase in required processes can be eliminated.

According to the present embodiment, the protective layer 14a of ITO is formed on the aluminum of the signal line 21, but SnO ₂ (tin oxide) and In ₂ O ₃ (indium oxide) are used instead of ITO.
Can also be used.

[0038]

According to the present invention, a source electrode and a semiconductor film
And between the drain electrode and the semiconductor film.
The ohmic layer is placed on the end of the ohmic layer.
And each of the source and drain electrodes
The protective layer made of ITO of the same material as the pixel electrode
The source and drain electrodes.
Even if the uppermost alignment film comes off during rubbing, these sources
When the electrode and drain electrode stop contacting the liquid crystal directly
Both orientations on the protective layer covering the edges of the ohmic layer
Even if the film comes off during rubbing, the edge of this ohmic layer
The source and drain electrodes are in direct contact with the liquid crystal through
Because it does not touch, contra
Prevents image quality defects such as reduced cost and reduced gradation display capability
it can. In addition, the end of the ohmic layer is covered with a protective layer,
An alignment film of an array substrate is formed on the protective layer and the display pixel electrodes.
Directly covers the end of the ohmic layer
This eliminates the need for additional processes.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a thin film transistor portion showing an embodiment of an active matrix type liquid crystal display device of the present invention.

FIG. 2 is a cross-sectional view showing a signal line part according to the first embodiment;

FIG. 3 is a sectional view showing the internal structure of a conventional general active matrix type liquid crystal display device.

4 is an equivalent circuit diagram showing an electric circuit for one pixel of a display pixel electrode array in the active matrix liquid crystal display device shown in FIG.

FIG. 5 is a sectional view showing a thin film transistor portion of a conventional active matrix type liquid crystal display device.

FIG. 6 is a cross-sectional view showing a signal line part according to the first embodiment;

[Explanation of symbols]

 11,12 Insulating substrate 13 Thin film transistor 13D Drain electrode 13G Gate electrode 13S Source electrode 14 Display pixel electrode 14a Protective layer 17 Liquid crystal 21 Signal line 22 Scan line 27 Array substrate 28 Gate insulating film 29 Semiconductor layers as semiconductor film 31a, 31b Ohmic layer 32 Alignment film 34 Counter substrate

Claims (2)

(57) [Claims] 1. A plurality of scanning lines and signal lines arranged on one main surface of an insulating substrate so as to intersect with each other, and thin film transistors arranged near intersections of these scanning lines and signal lines. An active matrix type liquid crystal display device comprising: an array substrate having display pixel electrodes formed of ITO; a counter substrate facing the array substrate; and a liquid crystal disposed between the array substrate and the counter substrate. The thin film transistor may include a gate electrode connected to the scanning line, an insulating film disposed on the gate electrode, a semiconductor film disposed on the insulating film, and a semiconductor film and the signal line. A source electrode that is electrically connected, and a drain electrode that is electrically connected to the semiconductor film and the display pixel electrode, wherein the signal line, the source electrode, Of the serial drain electrode
Each is made of ITO, which is the same material as the display pixel electrode.
In is covered with a protective layer formed, the array substrate is viewed contains an alignment layer disposed directly on said display pixel electrode and the protective layer, between the source electrode and the semiconductor film, and the drain
An ohmic layer is provided between the in-electrode and the semiconductor film.
Each end of this ohmic layer is
An active matrix liquid crystal display device characterized by being covered with a layer . 2. The active matrix type liquid crystal display device according to claim 1, wherein the signal line, the source electrode and the drain electrode are made of aluminum.