JP3354267B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory having a redundant cell for repairing a defective memory cell, and more particularly to a semiconductor memory which requires a reduction in a standby current.

[0002]

2. Description of the Related Art Semiconductor memories are often required to reduce current consumption during standby (standby). That is, although the memory cell operates normally and has no functional problem, a leak current may flow more than an allowable value. If such a memory cell is present, the current at the time of standby increases. Therefore, it is desirable that the memory cell is regarded as a defective memory cell, is not used, and is switched to a redundant memory cell.

FIG. 7 shows a conventional means for preventing such inconvenience. In FIG. 7, 1 is a memory cell arranged in the row direction, 2 is a common power supply line, and 3 is a power supply voltage V.
A power supply terminal for supplying cc to the common power supply line 2 and a fuse 4 are provided.

[0004] Here, a memory cell in which a leak current exceeding the allowable value is found is found by using a tester, and the laser fuse 4 connected between the power supply terminal 3 and the memory cell which can be regarded as a defect is blown. As a result, the memory cell is replaced with a spare (redundant) memory cell by cutting off the leak path. Recently, the memory capacity has been increased, and when the wiring resistance of the common power supply line 2 increases due to such a situation, the supply of the power supply voltage to each memory cell 1 becomes longer from the terminal 3. As a result, the operation margin is reduced, which is a problem. That is, there is a problem in that the memory capacity has recently been increased, and the common power supply line 2 has been lengthened.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and in a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix, power is supplied to memory cells arranged in a row direction. A memory cell having a leak current larger than an allowable value can be replaced with a redundant cell, and stable operation can be expected without causing a decrease in power supply voltage and an increase in chip size due to an increase in wiring resistance of a common power supply line to be supplied. It is like that.

[0006]

According to the present invention, there is provided a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix form, wherein power is commonly supplied to a plurality of memory cells in a row direction. (N is an integer of 1 or more), and a common power supply line for supplying power from one end to the other end, and a common power supply line obtained by dividing the common power supply line into N portions between adjacent ones of the divided power supply lines. A power supply voltage level obtained by amplifying a voltage from a divided power supply line that is interposed and is closer to one side as viewed from one end side that supplies the power,
A power supply voltage supply means for supplying power to a divided power supply line which is farther from the power supply supply end, a power supply supply end on one end side of the common power supply line, and a division located first from the power supply supply end A fuse interposed between the power supply line and a potential holding means for holding the common power supply line at a ground potential after cutting the fuse; and And a redundant cell to be used.

That is, according to the present invention, the common power supply line is divided into N parts,
Power supply voltage supply means for increasing the side effect is provided so as to connect them at each boundary of the division point, and the power supply voltage dropped from the divided power supply line closer to the power supply end as viewed from the means is reduced to the power supply voltage before dropping. The power supply voltage to each memory cell in the row direction is kept high by raising the voltage to prevent a voltage drop on the side remote from the power supply end. For this reason, the operation of each memory cell is ensured, and the fluctuation of the power supply can be suppressed even in the transient response of the operation. Since the floating state of the common power supply line, which has been disconnected, is eliminated, the operation can be stabilized. Further, since a single common power supply line and a single fuse can be used for a plurality of row selection lines, the area occupied by the chip can be reduced, and the number of fuses to be cut becomes extremely small. And the reliability is improved. This is because the number of memory cells attached to one common power supply line and row selection line increases under the recent trend of large-capacity memory, and if the number of fuses increases, the number of fuse cuts increases. This can be said from the fact that as the number increases, the reliability decreases.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows only one column of a common power supply line accompanied by memory cells in a row direction in a memory cell array in which memory cells are arranged in a matrix, and corresponds to FIG. This is an example. Therefore, in FIG. 1, the same reference numerals are given to portions corresponding to those in FIG.

FIG. 1 shows an example in which the common power supply line 2 is divided into two parts. The boundary of the division point between the divided power supply lines 2a and 2b is connected by the power supply voltage supply means 11. This means 1
1 uses a CMOS inverter 11a, 11b cascaded here. CMOS inverters
Usually, since a PMOS transistor is arranged on the power supply Vcc side, the power supply Vcc is connected to the output terminal of the CMOS inverter.
Levels are obtained and preferred.

A divided power supply line 2a between the fuse 4 connected to the supply terminal 3 of the power supply Vcc and the memory cell 1 closest to the fuse has a potential holding means 12 for holding the common power supply line 2 at the ground potential. Are connected to the output terminal 12a. The means 12 includes a flip-flop portion corresponding to transistors 13 to 15 and a coupling capacitor 16. The operation of this means 12 is such that when the fuse 4 is not blown, the power supply Vc from the terminal 3 via the fuse 4
c (“1”) level continues to be supplied, and the other node 1
2b is at the “0” level. On the other hand, when a leak failure is detected in any of the memory cells 1 in FIG. 1, the fuse 4 is cut by laser fusing or the like, and switching to the redundant cell is performed. When cutting the fuse 4,
The power supply Vcc is not applied at all. Therefore, when the power supply Vcc is turned on again after the fuse 4 is cut, the capacity 1
6, the node 12b becomes "1" level, the node 12a is kept at "0", that is, the ground level, and the common power supply line 2 is kept at the ground level.

FIG. 2 and FIG. 3 are for explaining the operation and effect of the configuration of FIG. Here, FIG. 2A does not interpose the power supply voltage supply means 11 of FIG. 1, and is equivalent to a conventional example. FIG. 2B shows FIG. 1 as an equivalent circuit. Here, L is the length of the common power supply line 2,
L / 2 is the length of each of the divided power supply lines 2a and 2b, i is the current flowing through the common power supply line 2, R is the wiring resistance of the common power supply line, and Va and Va 'are FIGS. 2A and 2B, respectively. ) Is the far end voltage. FIG. 3 shows a voltage drop state due to the resistance of the power supply line 2.

That is, as shown in FIG. 2 (b), by dividing the common power supply line 2 into two parts and arranging the power supply voltage supply means 11 by amplification, the means 11 allows the divided power supply line 2b to be divided from the start end to the end. By supplying Vcc again, the voltage drop becomes Va ′ = Va / 2 as shown in FIG. 3 as compared with the conventional example, and the voltage drop can be reduced to half of the conventional example.
Therefore, each memory cell 1 can be supplied with a relatively high power supply voltage having a smaller voltage effect than the conventional example. For this reason, even in the transient response of the operation, the fluctuation of the power supply becomes small, and the operation margin is improved. In addition, since the common power supply line 2 is kept at the ground level, the operation can be expected to be stabilized.

FIGS. 4 and 5 show a memory cell array (for one common power supply line) when the memory capacity is increased and the wiring resistance of the common power supply line is increased. FIG. 4 shows an embodiment in which the present invention is further embodied, and FIG. 5 shows an embodiment using a common power supply line voltage drop prevention means (supplying Vcc via fuses 4) which can be considered by using ordinary means. Is shown. 4 and 5, the common power supply line that can be integrated into one in the present invention is divided into N here.

4, 21 are row selection circuits (row decoders), 22, 22,... Are row selection lines or word lines, and 23, 23,. , 2, 2, ... also indicate power lines divided into N. The memory cells 1, 1,... Are assumed here to be static RAM cells having a flip-flop configuration. The memory cells 1, 1,... Are divided into N divided common power supply lines 23, 23,.
(FIG. 4) and 2, 2,... (FIG. 5). One of the two lines connected to the row line 22 is focused on one memory cell 1, and one of the two lines is the storage data of the memory cell 1. For controlling the opening and closing of a switch (transfer gate) (not shown) for supplying a current to a bit line (not shown).
The other of these lines is for controlling the opening and closing of a switch for supplying data complementary to the stored data to a bit line (not shown) complementary to the bit line.

In recent years, the memory capacity has been increased. However, since the memory shown in FIG. 5 is a large-capacity memory, the number of common power supply lines 2 and the number of fuses 4 associated therewith and the number of row selection lines 22 are large. Therefore, the number of memory cells 1 in these lines increases, so that the area occupied by the chip increases and the number of common power supply lines increases. There is a high possibility that a memory cell having a large leak exists in a line or a row selection line, and thus the necessity of blowing a plurality of fuses 4 in a cell array increases, thereby causing a problem in reliability. However, in FIG. 4, the common power supply line 23 common to each row selection line 22 can be regarded as one, and only one fuse 4 at the Vcc supply end needs to be cut off. The increase is small and the reliability at the time of fuse cutting is also improved.

FIG. 6 shows another embodiment of the power supply means 11. As in the case of the previous embodiment, this means 11 is also arranged so as to divide the common power supply line 23, and the power supply voltage which has dropped before this line 23 is supplied to the CMOS inverter 3
1. The voltage is increased to Vcc by the PMOS transistor 32.

In the case of FIG. 6, the circuit can be made smaller than the two-stage inverter shown in FIG. 1, and the power supply voltage Vcc is transmitted to the power supply line 23 through the PMOS transistor 32. The power supply voltage value can be transmitted to the power supply line 23 as it is.

[0018]

As described above, according to the present invention, in a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix, the wiring resistance of a common power supply line for supplying power to memory cells arranged in a row direction. It is possible to replace a memory cell having a leak current larger than an allowable value with a redundant cell and to expect a stable operation without causing a decrease in power supply voltage and an increase in chip size due to an increase in memory cell size.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of the operation and effect of FIG. 1;

FIG. 3 is an explanatory diagram of the operation and effect of FIG. 1;

FIG. 4 is a circuit configuration diagram of an embodiment that further embodies FIG. 1;

FIG. 5 is a circuit diagram in which a conventional example is improved for comparison with the circuit of FIG. 4;

FIG. 6 is a circuit diagram of a main part of another embodiment of the present invention.

FIG. 7 is a conventional memory circuit diagram.

[Explanation of symbols]

1 ... memory cell, 2, 23 ... common power supply line, 2a, 2b ...
Divided power supply lines, 3 power supply terminals, 4 fuses, 11 power supply voltage supply means, 12 potential holding means, 21 row decoders, 22 row selection lines.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-121687 (JP, A) JP-A-3-149867 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00 603

Claims (5)

(57) [Claims] 1. In a semiconductor memory having a memory cell array in which memory cells are arranged in a matrix, N (N is an integer of 1 or more) is used to supply power to a plurality of memory cells in a row direction in common. A common power supply line for a memory cell, which is divided and supplies power from one end to the other end, and is interposed between adjacent divided power supply lines obtained by dividing the common power supply line into N parts, respectively. A power supply voltage level obtained by amplifying a voltage from a divided power supply line adjacent to the power supply closer to the power supply end is supplied to a divided power supply line adjacent to the power supply end farther from the supply end of the power supply. A power supply voltage supply means, a fuse interposed between a power supply end on one end side of the common power supply line and a divided power supply line located first from the power supply end, , The common telephone The semiconductor memory for the potential holding means for holding the line at the ground potential, after cutting of the fuse, characterized by comprising a redundancy cell used in place of the line cut the fuse. 2. The semiconductor memory according to claim 1, wherein the fuse is cut for a common power supply line in which a memory cell having a leakage current in a standby state exceeding an allowable value exists. 3. The semiconductor memory according to claim 1, wherein the number of divisions of said common power supply line corresponds to the number of memory cell row selection lines associated with said common power supply line. 4. The semiconductor memory according to claim 1, wherein said power supply voltage supply means supplies power to a divided power supply line via a PMOS transistor. 5. The semiconductor memory according to claim 1, wherein said memory cell is a flip-flop type static cell.